SMP04 Analog Devices, SMP04 Datasheet
SMP04
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SMP04 Summary of contents
Page 1
... TTL/CMOS logic compatibility. Its output swing includes the negative supply. The SMP04 is ideally suited for a wide variety of sample-and- hold applications, including amplifier offset or VCA gain adjust- ments. One or more can be used with single or multiple DACs to provide multiple setpoints within a system ...
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... SMP04–SPECIFICATIONS ELECTRICAL CHARACTERISTICS specified in Absolute Maximum Ratings, unless otherwise noted.) Parameter Symbol Linearity Error Buffer Offset Voltage V Hold Step V Droop Rate 1 Output Source Current I 1 Output Sink Current I Output Voltage Range OVR LOGIC CHARACTERISTICS Logic Input High Voltage V Logic Input Low Voltage ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the SMP04 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... V SINK IN OVR INH V INL I IN PSRR 10 DIS –4– IN4 V IN3 SMP04G Limits Units 10 mV max 4 mV max 25 mV/s max 1.2 mA min 0.5 mA min 0.06/10.0 V min/max 0.06/9.5 V min/max 2.4 V min 0.8 V max 1 A max 13 min 7 mA max 84 mW max REV. D ...
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... Figure 4. Hold Step vs. Input Voltage +12V 20k –1 L – 10k L –3 – INPUT VOLTAGE – Volts Figure 7. Offset Voltage vs. Input Voltage ( REV. D Typical Performance Characteristics–SMP04 +12V –1 –3 – INPUT VOLTAGE – Volts Figure 2. Droop Rate vs. Input Voltage ( +12V +5V IN ...
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... SMP04 +12V +5V IN – 10k L –2 –3 –4 –5 –55 –33 – 105 125 TEMPERATURE – C Figure 10. Offset Voltage vs. Temperature –45 –1 PHASE –90 –2 –3 –135 GAIN –180 –4 –225 –5 100 1k 10k 100k 1M 10M FREQUENCY – Hz Figure 13. Gain, Phase Shift vs. ...
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... The signal inputs should be driven from a low impedance voltage source such as the output amp. The op amp should have a high slew rate and fast settling time if the SMP04’s fast acquisition time characteristics are to be maintained. As with all CMOS devices, all input voltages should be kept within range of the supply rails (V ity of setting up a latch-up condition ...
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... See Figure 16a for typical 86.1 kHz sample rate and an 8 kHz input signal. Typically, the SMP04 can sample at rates kHz. In addition to the maximum sample rate, a minimum sample pulsewidth will also be acceptable for a given design. Our testing shows a drop in performance as the sample pulsewidth becomes less than 4 s ...
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... CENTER 10 500.0 Hz SPAN 19 000 Figure 18. SMP04 Spectral Response with a 1.8 kHz Carrier Frequency. (a) Shows the Sampling Frequency at 14.4 kHz; it Exhibits a S/N Ratio of 58.2 dB. (b) Shows a 59 Sampling Frequency of 8.6 kHz. (c) Shows S/N at 7.2 kHz. REV. D different sampling frequencies of 14.4 kHz, 9.6 kHz and 7 ...
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... SMP04 APPLICATIONS MULTIPLEXED QUAD DAC (Figure 20) The SMP04 can be used to demultiplex a single DAC converter’s output into four separate analog outputs. The circuit is greatly simplified by using a voltage output DAC such as the DAC8228. To minimize output voltage perturbation should be allowed to settle to its final voltage before a sample signal is asserted. ...
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... S SD214 GAIN OF 10 SAMPLE-AND-HOLD (Figure 22) This application places the SMP04 in a feedback loop of an amplifier. Because the SMP04 has no sign inversion and the amplifier has very high open-loop gain, the gain of the circuit is set by the ratio of the sum of the source and feedback resistances ...
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... SS 1/2 SMP04 DGND SINGLE SUPPLY, SAMPLING, INSTRUMENTATION AMPLIFIER (Figure 24) and t . The This application again uses two channels of the SMP04 and instrumentation amplifier to provide a sampled difference signal. sets the gain of The sample-and-hold signals in this circuit are tied together to G sample at the same point in time. The other two parts of the SMP04 are used as amplifiers by grounding their control lines so they are always sampling ...
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... DAC output to change. Any glitch that occurs at the DAC output is effectively blocked by the SMP04. As soon as the WR strobe goes HIGH, the digital data is latched; at the same time the S/H goes LOW, allowing the SMP04 to track to the new DAC output voltage. Figure 26b shows the deglitching operation. The top trace shows the DAC output during a transition, while the bottom trace shows the deglitched output of the SMP04 ...
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... SMP04 N- P- S/H LOGIC V SS DGND C H Figure 27. Simplified Schematic of One Channel V DD +15V SMP04 10k 10k Figure 28. Burn-In Circuit –14– OUT LOAD 10k 10k REV. D ...
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... SEATING 0.0099 (0.25) (1.27) 0.0138 (0.35) PLANE BSC 0.0075 (0.19) –15– SMP04 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 15° 0.008 (0.20) 0° 0.325 (8.26) 0.195 (4.95) 0.300 (7.62) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204) 0.0196 (0.50) x 45° ...