AD1846JP Analog Devices, AD1846JP Datasheet
AD1846JP
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... R_AUX2 REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. ...
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AD1846–SPECIFICATIONS STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED Temperature 25 Digital Supply (V ) 5.0 DD Analog Supply (V ) 5.0 CC Word Rate ( Input Signal 1007 Analog Output Passband kHz FFT Size ...
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DIGITAL DECIMATION AND INTERPOLATION FILTERS* Passband Passband Ripple Transition Band Stopband Stopband Rejection Group Delay Group Delay Variation Over Passband ANALOG-TO-DIGITAL CONVERTERS Resolution Dynamic Range (–60 dB Input, THD+N Referenced to Full Scale, A-Weighted) THD+N (Referenced to Full Scale) Signal-to-Intermodulation ...
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AD1846 DAC ATTENUATOR Step Size ( –60 dB) (Tested at Steps 0 dB, –19.5 dB and –60 dB) Step Size (– –94.5 dB)* Output Attenuation Range Span* ANALOG OUTPUT Full-Scale Output Voltage Output Impedance* External Load ...
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TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE) WR/RD Strobe Width (t ) STW WR/RD Rising to WR/RD Falling (t BWND Write Data Setup to WR Rising (t ) WDSU RD Falling to Valid Read Data (t ) RDDV CS Setup ...
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... Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ADR0 CDAK CDRQ PDAK PDRQ V GNDD XTAL1I XTAL1O V GNDD XTAL2I XTAL2O PWRDWN V GNDD R_FILT Units Model V V AD1846JP +70 C +150 C 68-Lead Plastic Leaded Chip Carrier Pinout ...
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PIN DESCRIPTION Parallel Interface Pin Name PLCC I/O CDRQ 12 O CDAK 11 I PDRQ 14 O PDAK 13 I ADR1:0 9 & DATA7:0 3–6 & I/O 65–68 DBEN ...
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AD1846 Analog Signals Pin Name PLCC I/O L_LINE 30 I R_LINE 27 I L_MIC 29 I R_MIC 28 I L_AUX1 39 I R_AUX1 42 I L_AUX2 38 I R_AUX2 43 I L_OUT 40 O R_OUT 41 O Miscellaneous Pin Name ...
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ADDRESS AD1846 DECODE DATA7:0 4 DBDIR DIR 2 4 DBEN PDRQ CDRQ PDAK CDAK INT Figure 1. Interface to ISA Bus The pair of 16-bit outputs ...
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AD1846 Sixty-four steps of –1.5 dB attenuation are supported to –94.5 dB. The digital mix datapath can also be completely muted, preventing any mixing of the analog input with the digi- tal input. Note that the level of the mixed ...
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CONTROL REGISTERS Control Register Architecture The AD1846 SoundPort Stereo Codec accepts both data and control information through its byte-wide parallel port. Indirect addressing minimizes the number of external pins required to access all 21 of its byte-wide internal registers. Only ...
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AD1846 Direct Control Register Definitions Index Register (ADR1 ADR1:0 Data 7 Data 6 0 INIT MCE IXA3:0 Index Address. These bits define the address of the AD1846 register accessed by the Indexed Data Register. These bits are read/write. ...
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Status Register (ADR1 ADR1:0 Data 7 Data 6 2 CU/L CL/R INT Interrupt Status. This sticky bit (the only one) indicates the status of the interrupt logic of the AD1846. This bit is cleared by any host write ...
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AD1846 PIO Data Registers (ADR1 ADR1:0 Data 7 Data 6 3 CD7 CD6 3 PD7 PD6 The PIO Data Registers are two registers mapped to the same address. Writes send data to the PIO Playback Data Register (PD7:0). ...
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Right Input Control (IXA3 IXA3:0 Data 7 Data 6 1 RSS1 RSS0 RIG3:0 Right Input Gain Select. The least significant bit of this gain select represents +1.5 dB. Maximum gain is +22.5 dB. res Reserved for future expansion. ...
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AD1846 Left Auxiliary #2 Input Control (IXA3 IXA3:0 Data 7 Data 6 4 LMX2 res LX2A4:0 Left Auxiliary Input #2 Attenuate Select. The least significant bit of this gain/attenuate select represents –1.5 dB. LX2A4 produces a ...
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Clock and Data Format Register (IXA3 IXA3:0 Data 7 Data 6 8 res FMT The contents of the Clock and Data Format Register cannot be changed except when the AD1846 is in Mode Change Enable (MCE) state. Write ...
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AD1846 Interface Configuration Register (IXA3 IXA3:0 Data 7 Data 6 9 CPIO PPIO The contents of the Interface Configuration Register cannot be changed except when the AD1846 is in Mode Change Enable (MCE) state. Write attempts to this ...
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Test and Initialization Register (IXA3:0 = 11) IXA3:0 Data 7 Data 6 11 COR PUR ORL1:0 Overrange Left Detect. These bits indicate the overrange on the left input channel. This bit changes on a sample-by- sample basis. This bit is ...
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AD1846 Digital Mix Control Register (IXA3:0 = 13) IXA3:0 Data 7 Data 6 13 DMA5 DMA4 DME Digital Mix Enable. This bit will enable the digital mix of the ADCs’ output with the DACs’ input. When enabled, the data from ...
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DATA AND CONTROL TRANSFERS The AD1846 SoundPort Stereo Codec supports a DMA re- quest/grant architecture for transferring data with the host com- puter bus. One or two DMA channels can be supported. Programmed I/O (PIO) mode is also supported for ...
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AD1846 CDRQ/ PDRQ OUTPUTS t SUDK1 PDAK INPUT t CSSU CS INPUT t DBDL DBEN OUTPUT DBDIR HI OUTPUT t STW WR INPUT t WDSU DATA7:0 INPUTS t ADSU ADR1:0 INPUTS Figure 12. Control Register/PIO Write Cycle Direct Memory Access ...
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DMA Timing Below, timing parameters are shown for 8-Bit Mono Sample Read/Capture and Write/Playback DMA transfers in Figures 13 and 14. Note that in single-channel DMA mode, the Read/ Capture cycle timing shown in Figure 13 applies to the PDRQ ...
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... Status Register’s INT bit may be set. POWER UP AND RESET The PWRDWN pin should be held in its active LO state when power is first applied to the AD1846. Analog Devices recom- mends waiting one full second after deasserting PWRDWN be- fore commencing audio activity with the AD1846. This will allow the analog outputs to fully settle to the V prior to system autocalibration ...
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... The AD1846 Stereo Codec has been designed to require a mini- mum of external circuitry. The recommended circuits are shown in Figures 17 through 25. Analog Devices estimates that the to- tal cost of all the components shown in these figures, including crystals but not including connectors less than $10 in the U ...
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... SUPPLY 1.0 F Figure 24. Recommended Power Supply Bypassing Analog Devices recommends a split ground plane as shown in Figure 25. The analog plane and the digital plane are connected directly under the AD1846. Splitting the ground plane directly under the SoundPort Codec is optimal because analog pins will ...
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INDEX PRODUCT OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ELECTRICAL SPECIFICATIONS . . . . . . . ...
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AD1846 –28– REV. A ...