TMP91C820AF TOSHIBA Semiconductor CORPORATION, TMP91C820AF Datasheet
TMP91C820AF
Related parts for TMP91C820AF
TMP91C820AF Summary of contents
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... Micro controller TLCS-900/L1 series TMP91C820AF Data Book Rev. 2.5 07/December/2001 ...
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... Contents --------- TLCS-900/L1 LSI DEVICES TMP91C820AF 1. Outline and Device Characteristics 2. Pin Assignment and Pin Functions 2.1 Pin Assignment Diagram 2.2 Pin Name and Functions 3. Operation 3.1 CPU 3.1.1 Reset 3.2 Memory Map 3.3 Triple Clock, Stand-by Function 3.4 Interrupts 3.5 Functions of Ports 3 ...
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Data Book modification history Rev./Date page 16 Rev110/15-Mar-2001 508 717 718 Rev1.3/03-July-2001 704 705 721 420 725 132 135 136 156 17 259,260 145 tytle 500 Rev2.0/07-August-2001 14,17 24,25 262 13,16, 23,24 17 320 127 25,26 172 184 178 Rev2.1/15-August-2001 ...
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Note : Each page number corresponds to each revision when modified. LCDC ：TA3OUT equation modify SPEC : t ,t modify DW WW contents ...
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... OUTLINE AND FEATURES TMP91C820AF is a high-speed 16-bit microcontroller designed for the control of various mid- to large-scale equipment. TMP91C820AF comes in a 144-pin flat package. Listed below are the features. (1) High-speed 16-bit CPU (900/L1 CPU) Instruction mnemonics are upward-compatible with TLCS-90/900 16 Mbytes of linear address space General-purpose registers and register banks 16-bit multiplication and division instructions ...
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LCD controller Shift register/built-in RAM LCD driver Supported 16,8 and 4 Gray-levels and Black and White Hardware Blinking Cursor (10) SDRAM Controller Supported 16M,64M and 128Mbit-SDRAM with 16bit Data-bus (11) Timer for real-time clock (RTC) Based on TC8521A (12) ...
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ADTRG(P83) AN0 AN7 10-BIT 8CH (P80 P87) A/D CONVERTER AVCC, AVSS VREFH, VREFL TXD0 (PC0) SIO/UART/IrDA RXD0 (PC1) (SIO0) SCLK0/CTS0 (PC2) TXD1 (PC3) SIO/UART RXD1 (PC4) (SIO1) SCLK1/ CTS1(PC5) OPTRX0,SCK (P70) SERIAL BUS (P71) OPTTX0,SO/SDA I/F(SBI) (P72) SI/SCL 8BIT TIMER ...
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... PIN ASSIGNMENT AND PIN FUNCTIONS The assignment of input/output pins for the TMP91C820AF, their names and functions are as follows: 2.1 Pin Assignment Diagram Figure 2.1 shows the pin assignment of the TMP91C820AF. P81/AN1 1 P82/AN2 P83/AN3/ADTRG P84/AN4 5 P85/AN5 P86/AN6 P87/AN7 AVSS AVCC KI2/P92 10 KI3/P93 ...
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PAD layout (Chip size 5.75mm ×5.63mm) PIN Name point point 1 P81 -2742 2128 2 P82 -2742 2004 3 P83 -2742 1888 4 P84 -2742 1774 5 P85 -2742 1660 6 P86 -2742 1546 7 P87 -2742 ...
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Pin Names and Functions The names of the input/output pins and their functions are described below. Table 2.2 Pin names and functions. Number Pin Name I/O of Pins P00 to P07 8 I I/O P10 to ...
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Pin Name Number I/O of Pins P70 I/O 1 SCK I/O OPTRX0 Input P71 1 I/O S0 Output SDA I/O OPTRX0 Output P72 1 I/O SI Output SCL Output P73 1 I/O /CS2F Output P74 1 I/O /CS2G Output P75 ...
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Pin Name Number I/O of Pins PB5 1 I/O INT2 Input TA3OUT Output PB6 1 I/O INT3 Input TB0OUT0 Outout PC0 1 I/O TXD0 Output PC1 1 I/O RXD0 Input PC2 1 I/O SCLK0 I/O CTS0 Input PC3 1 I/O ...
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... Fixed to AM1=”0”,AM0=”0” when using external-ROM by 8-bit external bus. Open pin Open pin Reset: initializes TMP91C820AF. (With pull-up resistor) Pin for reference voltage input to AD converter (H) Pin for reference voltage input to AD converter (L) High-frequency oscillator connection pins ...
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OPERATION This following describes block by block the functions and operation of the TMP91C820A. Notes and restrictions for eatch book are outlined in “ 6, Precautions and Restrictions“ at the end of this manual. 3.1 CPU The TMP91C820A incorporates ...
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Figure 3.1.1 TMP91C820A Reset Timing Example (the case of using external-ROM) 91C820A-11 write TMP91C820A ...
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Memory Map Figure 3.2 memory map of the TMP91C820A. 000000H 000100H 000FE0H 001000H 003000H 010000H FFE000H FFFF00H Vector table (256 Byte) FFFFFFH (note) : Address 000FE0H – 000FEFH is assigned for the external memory area of Built-in ...
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Triple Clock Function and Standby Function TMP91C820A contains (1) a clock gear, (2) clock doubler (DFM), (3) standby controller and (4) noise-reducing circuit used for low-power, low-noise systems. This chapter is organized as follows: 3.3.1 Block diagram ...
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The clock operating modes are as follows: (a) Single Clock Mode (X1, X2 pins only), (b) Dual Clock Mode (X1, X2, XT1 and XT2 pins) and (c) Triple Clock Mode (the X1, X2, XT1 and XT2 pins and DFM). Figure ...
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Block diagram of system clock SYSCR0<WUEF> SYSCR2<WUPTM1, WUPTM 0> DFMCR0<ACT1, ACT 0, DLUPTM> Warming up timer (High/Low frequency oscillator), Lock up timer (DFM) SYSCR0 <XTEN, RXTEN> XT1 Low-Frequency fs oscillator XT2 f DFM SYSCR0 <XEN, RXTEN> Clock Doubler (DFM) ...
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SFR 7 SYSCR0 bit Symbol XEN XTEN (00E0H) Read/Write After reset 1 High-frequen Low-frequen cy oscillator cy oscillator (fc) (fs) 0: Stop 0: Stop 1: Oscillation 1: Oscillation (Note2) Function 7 SYSCR1 bit Symbol (00E1H) Read/Write After reset Function ...
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Symbol Name Address 7 ACT1 R/W 0 DFM DFM Control E8H DFMCR0 00 STOP Register 0 01 RUN 10 RUN 11 RUN DFM Control E9H DFMCR1 Register 0 Limitation point on the use of DFM 1. It’s prohibited to execute ...
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EMCCR0 bit Symbol PROTECT TA3LCDE (00E3H) Read/Write R After reset 0 Protect flag LCDC 0: OFF Source clock Function 1: ON 0:32KHz 1:TA3OUT EMCCR1 bit Symbol (00E4H) Read/Write After reset Function EMCCR2 bit Symbol (00E5H) Read/Write After reset Function ...
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System clock controller The system clock controller generates the system clock signal (f It contains two oscillation circuits and a clock gear circuit for high-frequency (fc) operation. The register SYSCR1<SYSCK> changes the system clock to either fc or fs, ...
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Example 1-Setting the cloc k Changing from high frequency (fc) to low frequency (fs). SYSCR0 EQU 00E0H SYSCR1 EQU 00E1H SYSCR2 EQU 00E2H LD (SYSCR2 SET 6, (SYSCR0) SET 2, (SYSCR0) WUP: BIT 2, (SYSCR0) JR NZ, WUP ...
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Example 2-Setting the clock Changing from low frequency (fs) to high frequency (fc). SYSCR0 EQU 00E0H SYSCR1 EQU 00E1H SYSCR2 EQU 00E2H LD (SYSCR2 SET 7, (SYSCR0) SET 2, (SYSCR0) WUP: BIT 2, (SYSCR0) JR NZ, WUP RES ...
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Clock gear controller When the high-frequency clock fc is selected by setting SYSCR1<SYSCK> according to the contents of the Clock Gear Select Register SYSCR1<GEAR0 to GEAR2> to either fc, fc/2, fc/4, fc/8 or fc/16. Using the ...
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Prescaler clock controller For the internal I/O (TMRA01 to 23, SIO0 to 1,SBI) there is a prescaler which can divide the clock. The T clock input to the prescaler is either the clock f The setting of the SYSCR0 ...
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Limitation point on the use of DFM 1. It’s prohibited to execute DFM enable/disable control in the SLOW mode(fs) (write to DFMCR0<ACT1:0>=”10”). You should control DFM in the NORMAL mode you stop DFM operation during using DFM (DFMCR0<ACT1:0>=”10”) ...
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Change / Stop Control (OK) DFM use mode (f DFM → Low frequency oscillator operation mode(f LD (DFMCR0),11------B LD (DFMCR0),00------B LD (SYSCR1), ----1---B LD (SYSCR0), 0-------B (NG) DFM use mode (f DFM →High frequency oscillator stop LD (SYSCR1), ----1---B ...
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Noise reduction circuits Noise reduction circuits are built in, allowing implementation of the following features. (1) Reduced drivability for high-frequency oscillator (2) Reduced drivability for low-frequency oscillator (3) Single drive for high-frequency oscillator (4) SFR protection of register contents ...
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Reduced drivability for low-frequency oscillator (Purpose) Reduces noise and power for oscillator when a resonator is used. (Block diagram) XT1 pin C1 Resonato C2 XT2 pin (Setting method) The drivability of the oscillator is reduced by writing 0 to ...
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Runaway provision with SFR protection register (Purpose) Provision in runaway of program by noise mixing. Write operation to specified SFR is prohibited so that provision program in runaway prevents that the state which is fetch ...
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Runaway provision with ROM protection register (Purpose) Provision in runaway of program by noise mixing. (Operation explanation) When writes operation was executed for external three kinds of ROM by runaway of program, INTP1 is occurred and detects runaway function. ...
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Standby controller (1) Halt Modes When the HALT instruction is executed, the operating mode switches to Idle2, Idle1 or Stop Mode, depending on the contents of the SYSCR2<HALTM1,HALTM0> register. The subsequent actions performed in each mode are as follows: ...
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How to release the Halt mode These HALT states can be released by resetting or requesting an interrupt. The halt release sources are determined by the combination between the states of interrupt mask register <IFF2-0> and the halt modes. ...
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Table 3.3.4 Source of Halt state clearance and Halt clearance operation Status of Received Interrupt Halt mode NMI INTWDT INT0 to? 3 (Note1) INTALM0 to 4 INTTA0 to 3,INTTB00 to 01 INTRX0 to 2,TX0 to 2 INTSS0 to 2 INTAD ...
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Operation ① IDLE2 Mode In Idle2 Mode only specific internal I/O operations, as designated by the Idle2 Setting Register, can take place. Instruction execution by the CPU stops. Figure 3.3 6 illustrates an example of the timing for clearance ...
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Stop Mode When Stop Mode is selected, all internal circuits stop, including the internal oscillator Pin status in Stop Mode depends on the settings in the SYSCR2<DRVE> register. Table 3.3.6 summarizes the state of these pins in Stop Mode. ...
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Example) The Stop mode is entered when the low frequency operates, and high frequency operates after releasing due to NMI. Address SYSCR0 EQU SYSCR1 EQU SYSCR2 EQU 8FFDH LD 9000H LD 9002H LD 9005H HALT NMI 9006H LD Note: ...
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Table 3.3.6 Pin states in IDLE1/Stop Mode Pin name input/output P00 to P07( Input mode Output mode I/O P10 to 17(D8 to 15) Input mode Output mode I/O P20 to 27(A16 to 23), Output pin P30 to 37(A8 ...
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Interrupts Interrupts are controlled by the CPU Interrupt Mask Register SR<IFF2:0> and by the built-in interrupt controller. The TMP91C820A has a total of 43 interrupts divided into the following five types: Interrupts generated by CPU: 9 sources (Software interrupts,Illegal ...
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Interrupt processing Interrupt specified by micro DMA start vector? No Interrupt vector value “V” read Interrupt request F/F clear General-purpose PUSH PC interrupt PUSH SR processing SR<IFF2:0> Level of accepted interrupt INTNEST INTNEST PC (FFFF00H Interrupt processing program RETI instruction ...
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General-purpose interrupt processing When the CPU accepts an interrupt, it usually performs the following sequence of operations. However, in the case of software interrupts and Illegal Instruction interrupts generated by the CPU, the CPU skips steps and ƒ ...
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Table 3.4.1 TMP91C820A interrupt vectors and micro DMA start vectors Default Type Interrupt source and source of micro DMA request Priority "Reset" or ｢SWI 0」instruction 1 「SWI 1」instruction 2 INTUNDEF: illegal instruction or ｢SWI 2」instruction 3 「SWI 3」instruction 4 「SWI ...
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Micro DMA processing In addition to general-purpose interrupt processing, the TMP91C820A supprots a micro DMA function. Interrupt requests set by micro DMA perform micro DMA processing at the highest priority level for maskable interrupts (level 6), regardless of the ...
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While the register for setting the transfer source/transfer destination addresses is a 32-bit control register, this register can only effectively output 24-bit addresses. Accordingly, micro DMA can access 16M bytes (the upper eight bits of the 32 bits are not ...
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Soft start function In addition to starting the micro DMA function by interrupts, TMP91C820A includes a micro DMA software start function that starts micro DMA on the generation of the write cycle to the DMAR register. Writing “1” to ...
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Detailed description of the Transfer Mode Register 8 bits DMAM0 Mode DMAM3 Number of Transfer Bytes 000 000 00 Byte transfer (fixed) 01 Word transfer 10 4-byte transfer 001 00 Byte transfer 01 Word transfer ...
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Interrupt controller operation The block diagram in Figure 3.4.3 shows the interrupt circuits. The left-hand side of the diagram shows the interrupt controller circuit. The right-hand side shows the CPU interrupt request signal circuit and the halt release circuit. ...
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Interrupt controller Interrupt request F/F NMI S Q RESET R interrupt vector read INTWD Decoder Priority setting register CLR Interrupt request F/F ...
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Interrupt level setting registers Symbol NAME Address 7 INT0 & IADC INTAD 90h INTE0AD R Enable 0 INT1 & I2C INT2 91h INTE12 R Enable 0 INT3& IA4C INTE3 INTALM 92h R ALM4 4Enable 0 INTALM 0 & IA1C ...
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Symbol NAME Address 7 INTRX1 & ITXT1C 99H INTTX1 INTES1 R Enable 0 INTES2 & INTES2 ILCD1C 9AH INTLCD LCD R Enable 0 INTTC0 & ITC1C INTET 9BH INTTC1 R C01 Enable 0 INTTC2 & ITC3C INTET 9CH INTTC3 R ...
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External interrupt control Symbol NAME Address 7 8CH 0 Interrupt Write”0” Input IIMC Mode (no RMW) control INT0 level Enable 0 Rising edge detect INT 1 “H” level INT NMI rising edge Enable 0 INT request generation at falling ...
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Symbol NAME Address 7 DMA0 80H DMA0V Start Vector (no RMW) DMA1 81H DMA1V Start Vector (no RMW) DMA2 82H DMA2V Start Vector (no RMW) DMA3 83H DMA3V Start Vector (no RMW) (5) Micro DMA burst specification Specifying the micro ...
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Notes The instruction execution unit and the bus interface unit of this CPU operate independently. Therefore, immediately before an interrupt is generated, if the CPU fetches an instruction that clears the corresponding interrupt request flag, the CPU may execute ...
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Port Functions The TMP91C820A features 126 bit settings which relate to the various I/O ports. As well as general-purpose I/O port functionality, the port pins also have I/O functions which relate to the built-in CPU and internal I/Os. Table ...
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Table 3.5.1 Port functions (1/2) (R: PU with programmable pull-up resistor) Number of Port name Pin name pins Port D PD0 1 PD1 1 PD2 1 PD3 1 PD4 1 PD6 1 PD7 1 Port E PD0 to PD7 8 ...
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Table 3.5.2 I/O Registers and Specifications (1/3) Port Pin name Port 0 P00 to P07 Input port Output port bus Port 1 P10 to P17 Input port Output port D8 to D15 bus Port 2 P20 to ...
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Table 3.5.2 I/O Registers and Specifications (2/3) Port Pin name P70 to P77 Port 7 Input port Output port P70 SCK input SCK output OPTRX0 input P71 SDA input SDA output So output OPTTX0 output P72 SI input SCL input ...
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Table 3.5.2 I/O Registers and Specifications (3/3) Port Pin name Port C PC0 to PC5 Input port Output port PC0 TXD0 output PC1 RXD0 input PC2 SCLK0 input SCLK0 output input CTS 0 PC3 TXD1 output PC4 RXD1 input PC5 ...
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Port 0 (P00 to P07) Port 8-bit general-purpose I/O port. Each bit can be set individually for input or output using the control register P0CR. Resetting resets all bits of the output latch P0, the control ...
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Port 1 (P10 to P17) Port 8-bit general-purpose I/O port. Each bit can be set individually for input or output using the control register P1CR and the function register P1FC. Resetting resets all bits of the ...
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P0 P1 bit Symbol P17 (0000H) (0001H) Read/Write After Reset 7 P1CR bit Symbol P17C (0004H) Read/Write After Reset 0 Function 7 P1FC bit Symbol P17F (0005H) Read/Write After Reset 0/1 Function Note: Read-modify-write is prohibited for and P1CR.and ...
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Port 2 (P20 to P27) Port 8-bit general-purpose I/O port. Each bit can be set individually for input or output using the control register P2CR and the function register P2FC. In addition to functioning as a ...
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P0 P2 bit Symbol P27 (0000H) (0006H) Read/Write After Reset 7 P2CR bit Symbol P27C (0008H) Read/Write After Reset 0/1 Function 7 P2FC bit Symbol P27F (0009H) Read/Write After Reset 0/1 Function Note: Read-modify-write is prohibited for and P2CR.and ...
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Port 3 (P30 to P37) Port 8-bit general-purpose I/O port. Each bit can be set individually for input or output using the control register P3CR and the function register P3FC. In addition to functioning as a ...
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P0 P3 bit Symbol P37 (0000H) (0007H) Read/Write After Reset 7 P3CR bit Symbol P37C (000AH) Read/Write After Reset 0/1 Function 7 P3FC bit Symbol P37F (000BH) Read/Write After Reset 0/1 Function Note: Read-modify-write is prohibited for and P3CR.and ...
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Port 4 (P40 to P47) Port 8-bit general-purpose I/O port. Each bit can be set individually for input or output using the control register P4CR and the function register P4FC. In addition to functioning as a ...
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P0 P4 bit Symbol P47 (0000H) (000CH) Read/Write After Reset 7 P4CR bit Symbol P47C (000EH) Read/Write After Reset 0/1 Function 7 P4FC bit Symbol P47F (000FH) Read/Write After Reset 0/1 Function Note: Read-modify-write is prohibited for and P4CR.and ...
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Port Z (PZ0 to PZ3) Port 4-bit general-purpose I/O port(P50 and P51 are used for output only). I/O is set using control register PZCR and PZFC. Resetting resets all bits of the output latch PZ to ...
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Reset Function control (on bits basis) PZFC write S A Output latch B PZ write PZ read /WR Internal address area Reset Direction control (on bit basis) PZCR Write Function conrtol (on bit basis) PZFC Write Output ...
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Reset Direction control (on bit basis) PZCR Write Function conrtol (on bit basis) PZFC Write Output latch B Output buffer C PZ Write R/W /SRWE P5 Read Figure3.5.13 Port Z (PZ3) 91C820A- (Programmable P-ch Pull-up) PZ3(R/W,/SRWE) 68 ...
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PZ bit Symbol (007DH) Read/Write After reset 7 PZCR bit Symbol (007EH) Read/Write After reset 7 Bit Symbol PZFC (007FH) Read/Write After reset (Note) Function Always fixed to “0” Note 1: Read-Modify-write is prohibited for registers PZCR and PZFC. ...
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Port 5 (P56) Port 1-bit general-purpose I/O port. I/O is set using control register P5CR and P5FC. Resetting resets all bits of the output latch P5 to “1”. In addition to functioning as a general-purpose I/O ...
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P5 bit Symbol (000DH) Read/Write After reset 7 P5CR bit Symbol P56C (0010H) Read/Write After reset Note 1: When the P53/WAIT pin use as the WAIT pin, P5CR<P53C> must be set to 0 and <Bn W2 ...
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Port6 (P60 to P67) Port60 to 67 are 8bit output ports. Resetting sets output latch of P62 to “0” and output latches of P60 to P61, P63 to P67 to “1”. Port6 also function as chip-select output (/CS0 to ...
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Port7 (P70 to P77) Port 8-bit general-purpose I/O port. I/O can be set on bit basis using the control register. Resetting sets Port 7 to input port and all bits of output latch to”1”. In addition ...
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Port71 (SO/SDA/OPTTX0) Port71 is a general-purpose I/O port also used as SDA (data input for I output for SIO mode) for serial bus interface and OPTTX0 (transmit output for IrDA mode of SIO0). Used as OPTTX0, it ...
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Port 72 (SI/SCL) Port72 is a general-purpose I/O port also used as SI (data input for SIO mode), SCL (clock 2 input/output for I C mode) for serial bus interface. Reset Direction control (on bit basis) P7CR ...
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Port 73 (/CS2F),74(/CS2G),75(/CSEXA) Port73 to 75 are general-purpose I/O ports. These are also used as control signal for extend chip-select output. Reset Function control 2 (on bit basis) P7FC2 write Direction control (on bit basis) P7CR write Funtcion control ...
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Port 76(MSK),77(VEECLK) Port76 and 77 are general-purpose I/O ports. These are also used as clock control function for voltage booster of external LCD driver. MSK pin (P76 input pin from external LCD driver, clock output from VEECLK ...
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P7 bit Symbol P77 (0013H) Read/Write After reset 1 7 P7CR bit Symbol P77C P76C (0016H) Read/Write 0 After reset 7 bit Symbol P77F P76F P7FC (0017H) Read/Write After reset 0:PORT MSK 1:VEECLK select Function 0: ”1” enable 1: ...
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Port 8 (P80 to P87) Port 8-bit input port and can also be used as the analog input pins for the internal AD converter. P83 can also be used as ADTRG pin for the AD converter. ...
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Port 9 (P90 to P97) Port are 8-bit input ports with pull-up resistor. In addition to functioning as general-purpose I/O port, port can also Key-on wake-up function as Key board interface. The various ...
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Port A (PA0 to PA7) Port A0 to PA7 are 8-bit output ports, and also used key-board interface pin KO0 to KO7 which can set open drain output buffer. Writing “1” in the corresponding bit of the port A ...
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Port B (PB0 to PB6) Port 6-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets Port input port. In addition to functioning as a general-purpose ...
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PB1 (TA1OUT, RXD2) Port B1 is I/O port pins and can also is used as RXD input for the serial channels. In case of use RXD2 possible to logical invert by setting the register PB<PB1>. Reset Direction ...
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PB4 (INT1), PB5 (INT2, TA3OUT), PB6 (INT3, TB0OUT0) Reset Direction Control (on bits basis) PBCR write Function control (On bit basis) PBFC write S Output latch PB write PB read INT1 Reset Direction Control (on bits basis) PBCR write ...
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PB bit Symbol (0022H) Read/Write After Reset 7 PBCR bit Symbol PB6C (0024H) Read/Write After Reset 7 bit Symbol PB6F PBFC (0025H) Read/Write After Reset 0: PORT Function 1: INT3 TB0OUT0 7 bit Symbol PBODE (002BH) Read/Write After Reset ...
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Port C (PC0 to PC5) Port are 6-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets PC0 to PC5 input ports. It also sets all bits ...
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Port C1, C4 (RXD0, 1) Port C1 and C4 are I/O port pins and can also is used as RXD input for the serial channels. In case of use RXD0/RXD1 possible to logical invert by setting the ...
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PC bit Symbol (0023H) Read/Write After Reset 7 PCCR bit Symbol (0026H) Read/Write After Reset 7 bit Symbol PCFC (0027H) Read/Write After Reset Function 7 bit Symbol PCODE (0028H) Read/Write After Reset Function Note 1: Read-Modify-Write is prohibited for ...
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Port D (PD0 to PD7) Port 8-bit output port. Resetting sets the output latch PD to “1”, and PD0 to PD7 pin output “1”. In addition to functioning as output port, Port D also function as ...
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PD bit Symbol PD7 (0029H) Read/Write After Reset 1 7 PDFC bit Symbol PD7F PD6F (002AH) Read/Write After Reset 0: PORT 0: PORT 1: MLDALM 1: /ALARM Function @<PD6>=1 1: /MLDALM @<PD6>=0 Note 1: Read-Modify-Write is prohibited for the ...
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Port E (PE0 to PE7) Port 8-bit general-purpose I/O ports. Each bit can be set individually for input or output using the control register PECR. Resetting , the control register PECR to “0” and sets Port ...
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Port F (PF0 to PF7) Port 8-bit output port. Resetting sets the output latch PF to “1”, and PF0 to PF7 pin output “1”. In addition to functioning as output port, Port F also function as ...
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Chip Select/Wait Controller On the TMP91C820A, four user-specifiable address areas (/CS0 to /CS3) can be set. The data bus width and the number of waits can be set independently for each address area (/CS0 to /CS3 and others). The ...
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Memory Start Address Registers Figure 3.6.1 shows the Memory Start Address Registers. The Memory Start Address Registers MSAR0 to MSAR3 set the start addresses for the CS0 to CS3 areas. Set the upper eight bits (A23 to A16) of ...
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Memory Address Mask Registers Figure 3.6.3 shows the Memory Address Mask Registers. Memory address mask registers MAMR0 to MAMR3 are used to set the size of the CS0 to CS3 areas by specifying a mask for each bit of ...
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Setting Memory Start Addresses and Address Areas Figure 3.6.4 show an example of specifying a 64-Kbyte-address area starting from 010000H using the CS0 areas. Set “01H” in memory start address register MSAR0<S23: 16>(corresponding to the upper 8 bits of ...
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Address Area Size Specification Table 3.6.1 shows the relationship between CS area and area size.△ Indicates areas that cannot be set by memory start address register and address mask register combinations. When setting an area size using a combination ...
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B0CS Bit symbol B0E (00C0H) Read/Write W After Reset 0 Read- 0: Disable Modify- 1: Enable Write instructions Function are prohibited. B1CS Bit Symbol B1E (00C1H) Read/Write W After Reset 0 Read- 0: Disable Modify- 1: Enable Write instructions ...
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Master Enable bits Bit 7 (<B0E>, <B1E>, <B2E> or <B3E> chip select/wait control register is the master bit, which is used to enable or disable settings for the corresponding address area. Writing “1” to this bit enables ...
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Operand CPU Data Operand Memory Data CPU Start Data Bus Bus Address Width Address D15 Width 2n+0 8 bits 2n+0 XXXX b7-b0 (Even 2n+0 XXXX b7-b0 16 bits number) 8 bits 2n+1 8 bits 2n+1 ...
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Wait control Bits (<B0W0 to B0W2>, <B1W0 to B1W2>, <B2W0 to B2W2>, <B3W0 to B3W2>, <BEXW0 to BEXW2> chip select/wait control register specify the number of waits that are to be inserted when the ...
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Setting example: In this example CS0 is set to be the 64-Kbyte area 010000H to 01FFFFH. The bus width is set to 16 bits and the number of waits is set to 0. MSAR0 01H............... Start address: 010000H MAMR0 07H.............. ...
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Timers (TMRA) The TMP91C820A features 4 built-in 8-bit timers. These timers are paired into four modules: TMRA01 and TMRA23. Each module consists of two channels and can operate in any of the following four operating modes. 8-Bit Interval ...
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Prescaler Prescaler Run/Clear 128 256 512 clock T16 T256 TA01RUN<TA0RUN> Selector External input clock: TA0IN T1 8-bit up counter T4 (UC0) T16 Over flow TA01MOD TA01MOD <PWM01, <TA0CLK1, ...
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Prescaler Prescaler Run/clea 128 256 512 clock T16 T256 TA23RUN<TA2RUN> Selector T1 8-bit Up-Counter T4 (UC2) T16 Over flow TA23MOD TA23MOD <TA2CLK1, TA2CLK 0> <PWM21, PWM20> Match 8-bit ...
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Operation of each circuit (1) Prescaler A 9-bit prescaler generates the input clock to TMRA01. The clock φT0 is divided by 4 and input to this prescaler. φT0 can be either f selected using the Prescaler Clock Selection Register ...
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Timer registers (TA0REG and TA1REG) These are 8-bit registers, which can be used to set a time interval. When the value set in the timer register TA0REG or TA1REG matches the value in the corresponding up-counter, the Comparator Match ...
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Comparator (CP0) The comparator compares the value counter with the value set in a timer register. If they match, the up counter is cleared to zero and an interrupt signal (INTTA0 or INTTA1) is generated. If ...
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SFR 7 TA01RUN Bit symbol TA0RDE (0100H) Read/Write R/W After Reset 0 Double buffer Function 0: Disable 1: Enable TA0REG double buffer control 0 Disable 1 Enable Note: The values of bits TA01RUN are undefined ...
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TA01MOD Bit symbol TA01M1 TA01M0 (0104H) Read/Write After Reset 0 Operation mode 00: 8-Bit Timer Mode 01: 16-Bit Timer Mode Function 10: 8-Bit PPG Mode 11: 8-Bit PWM Mode TMRA01 Mode Register PWM01 PWM00 TA1CLK1 ...
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TA23MOD Bit Symbol TA23M1 TA23M0 (010CH) Read/Write After Reset 0 Operation mode 00: 8-Bit Timer Mode 01: 16-Bit Timer Mode Function 10: 8-Bit PPG Mode 11: 8-Bit PWM Mode TMRA23 Mode Register PWM21 PWM20 TA3CLK1 ...
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TA1FFCR Bit symbol (0105H) Read/Write After Reset Read- Modify-Write Function instructions are prohibited. Note: The values of bits TA1FFCR are undefined when read. TMRA1 Flip-Flop Control Register TAFF1C1 1 00: Invert ...
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TA3FFCR Bit symbol (010DH) Read/Write After Reset Read- Modify-Write Function instructions are prohibited. Note: The values of bits TA3FFCR are undefined when read. TMRA3 Flip-Flop Control Register TAFF3C1 1 00: Invert ...
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Operation in each mode (1) 8-Bit Timer Mode Both TMRA0 and TMRA1 can be used independently as 8-bit interval timers. Q Generating interrupts at a fixed interval (using TMRA1) To generate interrupts at constant intervals using TMRA1 (INTTA1), first ...
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R Generating a 50% duty ratio square wave pulse The state of the timer flip-flop (TA1FF) is inverted at constant intervals and its status output via the timer output pin (TA1OUT). Example: To output a 3.0- s square wave pulse ...
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S Making TMRA1 count up on the match signal from the TMRA0 comparator Select 8-Bit Timer Mode and set the comparator output from TMRA0 to be the input clock to TMRA1. Comparaot output (TMRA0 match) TMRA0 up-counter 1 (when TA0REG ...
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The comparator match signal is output from TMRA0 each time the up-counter UC0 matches TA0REG, though the up-counter UC0 is not be cleared. In the case of the TMRA1 comparator, the match detect signal is output on each comparator pulse ...
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In this mode a programmable square wave is generated by inverting the timer output each time the 8-bit up-counter (UC0) matches the value in one of the timer registers TA0REG or TA1REG. The value set in TA0REG must be smaller ...
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Example: To generate 1/4-duty 50-kHz pulses ( MHz Clock state System clock: High frequency (fc) Clock gear: 1 (fc) Prescaler clock: f Calculate the value, which should be set in the timer register. To obtain ...
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PWM Output Mode This mode is only valid for TMRA0. In this mode, a PWM pulse with the maximum resolution of 8 bits can be output. When TMRA0 is used the PWM pulse is output on the TA1OUT ...
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In this mode the value of the register buffer will be shifted into TA0REG if 2 detected when the TA0REG double buffer is enabled. Use of the double buffer facilitates the handling of low duty ratio waves. Match with TA0REG ...
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Select System Select Prescaler Gear Value Clock Clock <GEAR2 GEAR0> <SYSCK> <PRCK1 PRCK0> 1 (fs) XXX 000 (fc) 001 ( 010 ( FPH 0 (fc) 011 ( 100 ( 10 XXX (fc/16 clock) XXX: Don't care (5) ...
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LCDC and MELODY/ALARM circuit supply mode This function can operate only TMRA3. It can use LCDC or MELODY/ALARM souce clock TA3 clock generated by TMRA3. But this function is special mode, without low clock (XTIN,XTOUT), so keep the rule ...
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External memory extension function (MMU) This is MMU function which can expand program / data area to 136M byte by having 4 local area. Address pins to external memory are 2 extended address bus pins (EA24,EA25) and 8 extended ...
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Recommendable memory map The recommendation logic address memory map at the time of variety extension memory correspondence is shown in Fig. 3.8.1 (1). And, a physical-address map is shown in Fig. 3.8.1 (2). However, when memory area is less ...
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LOCAL0 91CM20 /CS3 for Data-RAM (SDRAM non-support) (8MB) 000000H BANK0 BANK1 BANK2 BANK3 BANK4 Internal-I/O & RAM BANK5 BANK6 BANK7 800000H 1000000H : Internal Area : Overlapped with COMMON-Area LOCAL1 LOCAL2 /CS1 /CS2A for Option for Program-ROM Program-ROM (SDRAM support) ...
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Block diagram A2 to A16 CPU out Address A23 to A8 A23 to A20 LOCAL0 register L0E EA22 to EA20 LOCAL1 register EA23 to EA21 L1E LOCAL2 register L2E EA23 to EA21 LOCAL3 register L3E EA26 to EA22 Internal ...
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Control registers 7 LOCAL0 bit Symbol L0E (0350H) Read/Write R/W After reset 0 Use BANK for Function LOCAL0 0: not use 1: use 7 LOCAL1 bit Symbol L1E (0351H) Read/Write R/W After reset 0 Use BANK for Function LOCAL1 ...
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Operational description Set up bank value and bank use in bank setting-register of each local area of LOCAL register in common area. Moreover, in that case, a combination pin is set up and the CS/WAIT controller simultaneously sets up ...
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Data Address TMP91C815 /RD,(/WR,/HWR:SRAM) /CS2 EA24,EA25 /CS3 *In case of 16bit Bus memory MEMORY TMP91C820A Control signals Control signals D[0:15] D[0:15] open A16 A15 At Figure 3.8.4.1, it shows example of ...
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Setting ;CS0 LD (MSAR0),00H LD (MAMR0),FFH LD (B0CS),89H ;CS1 LD (MSAR1),40H LD (MAMR1),FFH LD (B1CS),83H ;CS2 LD (MSAR2),C0H LD (MAMR2),7FH LD (B2CS),C3H ;CS3 LD (MSAR3),80H LD (MAMR3),7FH LD (B3CS),85H ;CSX LD (BEXCS),00H ;Port LD (P6FC),3FH LD (P6FC2),02H ∼ LDW ...
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Operation ;***** /CS2 ***** ORG 000000H ORG 200000H ORG 400000H ORG 600000H ORG 800000H ORG a00000H ORG c00000H ORG E00000H LD (LOCAL3),85H LDW HL,(800000H) LD (LOCAL3),88H LDW BC,(800000H) ∼ ORG FFFFFFH ;***** /CS3 ***** ORG 0000000H ORG 0400000H ORG ...
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Operation ;***** /CS2 ***** ORG 000000H ORG 200000H NOP ∼ JP E00100H ORG 400000H ORG 600000H NOP ∼ JP E00200H ORG 800000H ORG a00000H ORG c00000H !!!! Program Start !!!! ORG E00000H LD (LOCAL2),81H JP C00000H ∼ ORG E00100H ...
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At Figure 3.8.4.4, it shows example of program jump. In the same way with before example, two dot line squares show each /CS2’s program ROM and /CS1’s(SDCS) SDRAM. Program start from E00000H common address, firstly, write to BANK register of ...
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Serial Channels TMP91C820A includes three serial I/O channels. For each channels either UART Mode (asynchronous transmission) or I/O Interface Mode (synchronous transmission) can be selected. (Channel 2 can be selected only UART mode.) I/O Interface Mode UART Mode In ...
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Mode 0 (I/O Interface Mode) bit Transfer direction Mode 1 (7-Bit UART Mode) No parity start bit Parity start bit Mode 2 (8-Bit UART Mode) start bit 0 No parity ...
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Block diagrams Figure 3.9 block diagram representing Serial Channel 0. prescaler T32 Serial clock generation circuit BR0CR <BR0CK1, 0> BR0CR <BR0S3 to 0> T32 BR0CR ...
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T32 Serial clock generation circuit BR1CR <BR1CK1, BR1CK0> BR1CR <BR1S3 to BR1S0> T32 BR1CR <BR1ADDE> Baud rate generator f SYS SCLK1 shared with PC5 I/O Interface Mode ...
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T32 Serial clock generation circuit BR2CR <BR2CK1, BR2CK0> BR1CR <BR2S3 to BR2S0> T32 BR2CR <BR2ADDE> Baud rate generator f SYS Receive Counter (UART only 16) RXDCLK SC2MOD0 ...
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Operation of each circuit (1) Prescaler, Prescaler clock selects There is a 6-bit prescaler for waking serial clock. The clock selected using SYSCR<PRCK1:PRCK0> is divided by 4 and input to the prescaler as φT0. The prescaler can be run ...
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Baud rate generator The baud rate generator is a circuit, which generates transmission and receiving clocks that determine the transfer rate of the serial channels. The input clock to the baud rate generator, T0, T2 T32, is ...
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Integer divider (N divider) For example, when the source clock frequency (fc) = 12.288 MHz, the input clock frequency = φT2 (fc/16), the frequency divider N (BR0CR<BR0S3 to BR0S0> and BR0CR<BR0ADDE> the baud rate in UART ...
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Table 3.9.3 Transfer rate selection (when baud rate generator Is used and BR0CR <BR0ADDE> fc [MHz] Frequency Divider 2 4 9.830400 12.288000 A 3 14.745600 6 C Note 1: Transfer rates in I/O Interface Mode are eight ...
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Serial clock generation circuit This circuit generates the basic clock for transmitting and receiving data. In I/O Interface Mode In SCLK Output Mode with the setting SC0CR<IOC> the basic clock is generated by dividing the output of ...
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The Receiving Buffers To prevent Overrun errors, the Receiving Buffers are arranged in a double-buffer structure. Received data is stored one bit at a time in Receiving Buffer 1 (which is a shift register). When bits ...
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Handshake function Serial Channels 0, 1 each has a CTS pin. Use of this pin allows data can be sent in units of one frame; thus, Overrun errors can be avoided. The handshake functions is enabled or disabled by the ...
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Transmission Buffer The Transmission Buffer (SC0BUF) shifts out and sends the transmission data written from the CPU form the least significant bit (LSB) in order. When all the bits are shifted out, the Transmission Buffer becomes empty and generates ...
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Timing generation In UART Mode Receiving Mode (Note) Interrupt timing Center of last bit (bit 8) Framing error timing Center of stop bit Parity error timing ― Overrun error timing Center of last bit (bit 8) Note: In ...
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SFR 7 Bit symbol TB8 SC0MOD0 Read/Write (0202H) After Reset 0 Transfer Hand shake data bit 8 0: CTS 1: CTS Function Figure 3.9.8 Serial Mode Control Register (channel 0, SC0MOD0 CTSE RXE WU R/W 0 ...
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Bit symbol TB8 SC1MOD0 Read/Write (020AH) After Reset 0 Transfer Hand shake data bit 8 0: CTS 1: CTS Function Figure 3.9.9 Serial Mode Control Register (channel 1, SC1MOD0 CTSE RXE WU R ...
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Bit symbol TB8 SC2MOD0 Read/Write (0212H) After Reset 0 Transfer (Note) data bit 8 always fixed to "0" Function Figure 3.9.10 Serial Mode Control Register (channel 2, SC2MOD0 − RXE WU SM1 R ...
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Symbol RB8 EVEN SC0CR Read/Write R (0201H) After Reset Received Parity data bit 8 0: odd 1: even Function Note: As all error flags are cleared after reading do not test only a single bit with a bit-testing ...
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BR8 EVEN SC1CR Read/W rite R (0209H) After Reset 0 Received Parity data bit 8 0: odd 1: even Function Note: As all error flags are cleared after reading do not test only a single bit with ...
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BR8 EVEN SC2CR Read/W rite R (0211H) After Reset 0 Received Parity data bit 8 0: odd 1: even Function Note: As all error flags are cleared after reading do not test only a single bit with ...
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Bit symbol BR0ADDE BR0CR Read/Write (0203H) After Reset 0 Always (16 K)/16 fixed to “0” division 0: Disable Function 1: Enable (16 K)/16 division enable 0 Disable 1 Enable 7 BR0ADD bit Symbol (0204H) Read/Write After reset Function Sets ...
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Symbol BR1ADDE BR1CR Read/Write (020BH) After reset 0 (Note) +(16 K)/16 Always division fixed to “0” 0: Disable Function 1: Enable +( division enable 0 Disabled 1 Enabled 7 BR1ADD Bit symbol (020CH) ...
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Symbol BR2ADDE BR2CR Read/Write (0213H) After reset 0 (Note) +(16 K)/16 Always division fixed to “0” 0: Disable Function 1: Enable +( division enable 0 Disabled 1 Enabled 7 BR2ADD Bit symbol (0214H) ...
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TB7 TB6 SC0BUF (0200H RB7 RB6 Note: Prohibit read modify write for SC0BUF. Figure 3.9.17 Serial Transmission/Receiving Buffer Registers (channel 0, SC0BUF) 7 Bit symbol I2S0 SC0MOD1 (0205H) Read/Write R/W After Reset 0 IDLE2 Function 0: ...
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TB7 TB6 SC2BUF (0210H RB7 RB6 Note: Prohibit read modify write for SC2BUF. Figure 3.9.21 Serial Transmission/Receiving Buffer Registers (channel 2, SC2BUF) 7 bit Symbol I2S0 SC2MOD1 (0215H) Read/Write R/W After Reset 0 IDLE2 Function 0: ...
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Operation in each mode (1) Mode 0 (I/O Interface Mode) This mode allows an increase in the number of I/O pins available for transmitting data to or receiving data from an external shift register. This mode includes the SCLK ...
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Transmission In SCLK output mode 8-bit data and a synchronous clock are output on the TXD0 and SCLK0 pins respectively each time the CPU writes the data to the Transmission Buffer. When all data is output, INTES0 <ITX0C> will ...
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Receiving In SCLK output mode, the synchronous clock is outputted from SCLK0 pin and the data is shifted to Receiving Buffer 1. This starts when the Receive Interrupt flag INTES0<IRX0C> is cleared by reading the received data. When 8-bit ...
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Transmission and Receiving (Full Duplex Mode) When the full duplex mode is used, set the level of Receive Interrupt to "0" and set enable the level of Transmit interrupt. In the transmit interrupt program, read the receiving buffer before ...
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Mode 1 (7-bit UART Mode) 7-Bit UART Mode is selected by setting the Serial Channel Mode Register SC0MOD0<SM1, SM0> field to 01. In this mode a parity bit can be added. Use of a parity bit is enabled or ...
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Clock state System clock: High frequency (fc) Clock gear: 1 (fc) Prescaler clock: System clock Main settings P9CR SC0MOD SC0CR ...
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Protocol Select 9-Bit UART Mode on the master and slave controllers. ‚ Set the SC0MOD0<WU> bit on each slave controller enable data receiving. ƒ The master controller transmits one-frame data including the 8-bit select code for ...
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Setting example: To link two slave controllers serially with the master controller using the internal clock f as the transfer clock. SYS TXD RXD TXD Master Slave 1 Select code 00000001 Since Serial Channels 0 and 1 operate in exactly ...
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Support for IrDA SIO0 includes support for the IrDA 1.0 infrared data communication specification. Figure 3.9.30 shows the block diagram. Transmisison data IR modulator SIO0 Modem Receive data IR demodulator TMP91C820A (1) Modulation of the transmission data When the ...
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SFR Figure 3.9.33 shows the control register SIRCR. Set the data SIRCR during SIO0 is stopping. The following example describes how to set this register: 1) SIO setting 2) LD (SIRCR), 07H 3) LD (SIRCR), 37H 4) Start transmission ...
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Bit symbol PLSEL RXSEL SIRCR (0207H) Read/Write After reset 0 Select Receive transmit pulse width 0: “H” pulse Function 0: 3/16 1: “L” pulse 1: 1/ TXEN RXEN SIRWD3 R Transmit ...
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Serial Bus Interface (SBI) The TMP91C820A has a 1-channel serial bus interface which employs a clocked-synchronous 8-bit SIO 2 mode and bus mode. The serial bus interface is connected to an external device through P71 (SDA) ...
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Serial Bus Interface (SBI) Control The following registers are used to control the serial bus interface and monitor the operation status. Serial bus interface control register 1 (SBI0CR1) Serial bus interface control register 2 (SBI0CR2) Serial bus interface data ...
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I C Bus Mode Control The following registers are used to control and monitor the operation status when using the serial bus interface (SBI) in the I 7 Bit symbol BC2 SBI0CR1 (0240H) Read/Write After Reset 0 Number ...
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Bit symbol MST SBI0CR2 (0243H) Read/Write After Reset 0 Master/Slave Transmitter/ Prohibit selection Receiver Read- selection modify-write Function Note1: Reading this register function as SBI0SR register. Note2: Switch a mode to port mode after confirming that the bus is ...
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Symbol MST SBI0SR (0243H) Read/Write After reset 0 Master/ Transmitter/ Prohibit Slave Receiver Read- status status modify-write monitor monitor Function Note1: Writing in this register functions as SBI0CR2. Figure 3.10.5 Registers for the I Serial Bus Interface Status ...
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Symbol SBI0BR0 (0244H) Read/Write After Reset Write ‘0’ IDLE2 0: Stop Function 1: Run 7 Bit symbol P4EN SBI0BR1 (0245H) Read/Write R/W After Reset 0 Internal clock Function 0: Stop 1: Operate 7 Bit symbol DB7 SBI0DBR (0241H) ...
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Control Bus Mode (1) Acknowledge Mode Specification Set the SBI0CR1<ACK> for operation in the acknowledge mode. The TMP91C820A generates an additional clock pulse for an Acknowledge signal when operating in Master Mode, it ...
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Clock synchronization 2 In the I C bus mode, in order to wired-AND a bus, a master device which pulls down a clock line to low-level, in the first place, invalidate a clock pulse of another master device which ...
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Transmitter/Receiver selection Set the SBI0CR2<TRX> to “1” for operating the TMP91C820A as a transmitter. Clear the <TRX> to “0” for operation as a receiver. When data with an addressing format is transferred in Slave Mode, when a slave address ...
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Interrupt service requests and interrupt cancellation When a serial bus interface interrupt request (INTS2) occurs, the SBI0CR2 <PIN> is cleared to “0”. During the time that the SBI0CR2<PIN> is “0”, the SCL line is pulled down to the Low ...
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The TMP91C820A compares the levels on the bus’s SDA line with those of the internal SDA output on the rising edge of the SCL line. If the levels do not match, arbitration is lost and SBI0SR<AL> is set to “1”. ...
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Software Reset function The software Reset function is used to initialize the SBI circuit, when SBI is rocked by external noises, etc. An internal Reset signal pulse can be generated by setting SBI0CR2<SWRST1, SWRST0> to “10” and “01”. This ...
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Data Transfer Bus Mode (1) Device initialization Set the SBI0BR1<P4EN>, SBI0CR1<ACK, SCK2 to SCK0>, Set SBI0BR1 to “1” and clear bits and 3 in the SBI0CR1 to “0”. Set a slave address ...
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Data Transfer Check the <MST> by the INTS2 interrupt process after the 1-word data transfer is completed, and determine whether the mode is a master or slave. QIf <MST> = “1” (Master Mode) Check the <TRX> and determine ...
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When the <TRX> is “0” (Receiver mode) When the next transmitted data is 8 bits, write the transmitted data to SBI0DBR. When the next transmitted data is other than 8 bits, set <BC2 to BC0> again. Set <ACK> to “1” ...
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R If <MST> (Slave Mode) In the slave mode, an INTS2 interrupt request occurs when the TMP91C820A receives a slave address or a GENERAL CALL from the master device, or when a GENERAL CALL is received and data ...
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Stop condition generation When SBI0SR<BB> the sequence for generating a stop condition can be initiated by writing “1” to SBI0CR2<MST,TRX,PIN> and “0” to SBI0CR2<BB>. Do not modify the contents of SBI0CR2<MST,TRX,PIN,BB> until a stop condition has been ...
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Restart Restart is used during data transfer between a master device and a slave device to change the data transfer direction. The following description explains how to restart when the TMP91CW12 is in Master Mode. Clear SBI0CR2<MST,TRX,BB> ...
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Serial Bus Interface Control Register Bit symbol SIOS SIOINH SBI0CR1 (0240H) Read/Write After Reset 0 0 Transfer start Continue/ 0: stop abort transfer 1: start 0: Continue Prohibit Function Read- transfer modify- 1: Abort write transfer Note: ...
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Bit symbol SBI0CR2 (0242H) Read/Write After Reset Prohibit Read- modify-write Function Note: Set the SBI0CR1<BC2 to 0> “000” before switching to a clocked-synchronous 8-bit SIO mode. 7 bit Symbol SBI0SR (0243H) Read/Write After reset Function Serial Bus Interface Control ...
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Bit symbol I2SBI0 SBI0BR0 (0244H) Read/Write After Reset Always Write IDLE2 “0”. 0: STOP Function 1: RUN 7 Bit symbol P4EN SBI0BR1 (0245H) Read/Write R/W After Reset 0 Internal clock Function 0: Stop 1: Operate Serial Bus Interface Baud ...
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Serial Clock Q Clock source SBI0CR1<SCK2 to SCK0> is used to select the following functions: Internal Clock In Internal Clock Mode one of seven frequencies can be selected. The serial clock signal is output to the outside on the ...
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R Shift edge Data is transmitted on the leading edge of the clock and received on the trailing edge. Leading edge shift Data is shifted on the leading edge of the serial clock (on the falling edge of the SCK ...
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Transfer modes The SBI0CR1<SIOM1 to SIOM0> is used to select a transmit, receive or transmit / receive mode. Q 8-Bit Transmit Mode Set a control register to a transmit mode and write transmit data to the SBI0DBR. After the ...
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Example: Program to stop data transmission (when an external clock is used) <SIOS> <SIOF> <SEF> SCK pin (output) SO pin * INTSBI interrupt request SBI0DBR a b Write transmitted data <SIOS> <SIOF> <SEF> SCK pin (input) SO ...
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R 8-Bit Receive Mode SCK pin SIOF SO pin bit 6 Figure 3.10.26 Transmitted data hold time at end of transmission Set the control register to receive mode and set SBI0CR1<SIOS> to “1” for switching to receive mode. Data is ...