GM82C765BPL Hynix Semiconductor, GM82C765BPL Datasheet
GM82C765BPL
Available stocks
Related parts for GM82C765BPL
GM82C765BPL Summary of contents
Page 1
General Description The GM82C765B is a CMOS LSI device which interfaces a host microprocessor to the floppy disk drive. It integrates the function of the Formatter/Controller, Data Separator. Write Precompensation, Data rate selection, Clock Generation, High Current Output Drivers, and ...
Page 2
Pin Configuration DACK DB0 7 8 DB1 9 DB2 10 DB3 GM82C765B 11 DB4 DB5 12 DB6 13 14 DB7 15 DMA IRQ 16 LDOR 17 18 LDCR RST ...
Page 3
PIN MENMO -MIC DIP PLCC TERMINAL COUNT DATA BUS 0 DBO thru 7-14 7-14 Thru DB7 DATA BUS 7 DIRECT 15 15 DMA MEMORY ACCESS INTERRUPT 16 16 IRQ REQUEST DISK 17 DCHGEN CHANGE ENABLE LOAD 17 ...
Page 4
DRV DRIVE TYPE XTAL 1 26 XT1 XTAL1 23 CLK1 CLOCK1 PRECOMPEN-SATION 24 27 PCVAL VALUE HEAD SELECT 26 29 WRITE ENABLE WRITE DATA DIRC DIRECTION ...
Page 5
PIN NO MNEMOMIC SIGNAL NAME DIP PLCC MOTOR DS 4 DRIVE 35 38 HDL HEAD LOADED 36 39 RWC REDUCED RPM WRITE CURRENT REVOLUTION PER 40 DCHG DISK CHANGE WRITE PROTECTED 38 ...
Page 6
Electrical Specifications. 2.1 Absolute Maximum Ratings — OPERATING TEMPERATURE ………………… — STORAGE TEMPERATURE ……………………………………… — VOLTAGE on any pin with respect to ground ………………………… — SUPPLY VOLTAGE with respect to ground ………………………………………… 2.2 DC ELECTRICAL CHARACTERISTICS NOTE: Maximum limits ...
Page 7
AC Timing Specifications 158 to SYMBOL t Clock Period CY t Clock Active (High or Low Clock Rise Time (Vin 0 Clock Fall ...
Page 8
SYMBOL t Index Pulse Width IDX IDX t Hold Time after STD DIRC t Delay from DMA Delay from DMA Response from DMA High RD MRW WR t Chip Access Delay from RST ...
Page 9
WRITE Timing CS , DACK ,A0 WR DATA IRQ (3) TERMINAL COUNT (TC) COUNTING DMA or IRQ TC (4) DMA TIMING DMA tMA DACK DATA tAW tWW tDW Data Valid tCR tCW tMCY tAM tAA tMRW ...
Page 10
RESET Timing RESET CS (6) DISK DRIVE SELECT TIMING DIRC STEP DSX IDX RDD WD (7) CLOCK Timing CLOCK tR tRST tDST tSTP tIDX tRDD tWDD tPH tF 10 GM82C765B tCA tSTD tSC tSTU tCY tPH ...
Page 11
ARCHITECTURE The GM82C765B Floppy Disk Subsystem Controller is a CMOS LSI device that provides all the needed functionality between the host u-processor peripheral Bus and the cable Connec-tor to the Floppy Disk Drive. This CHIP in-tegrates; Formatter/Controller Data Separation, ...
Page 12
MAIN MICROPROCESSOR INTERFACE BUS ADDRESS RECODE CKT CLOCK CKTS Fig 2. TYPICAL GM 82C765B APPLICATION SYSTEM Inputs, except the data bus, are Schmitt trig-ger receivers and can be hooked bus or backplane without any additional buffering. During ...
Page 13
If the processor can not handle interrupt fast enough (every 13uS for the MFM mode and 27uS for the FM mode), then it may poll the main status Register and bit D7 (RQM) ...
Page 14
TABLE 1. CONTROL REGISTER CR1 CR0 DRV MASTER STATUS REGISTER The Master Status Register is an eight-bit register that ...
Page 15
TABLE 3. STATUS REGISTER 0 BITs BIT NO NAME SYMBOL D7 INTERRUPT CODE D6 D5 SEEK END #D4 EQUIPMENT EC CHECK #D3 NOT READY NR D2 HEAD SELECT HS D1 UNIT SELECT 1 US1 D0 UNIT SELECT 0 US0 TABLE ...
Page 16
TABLE 4. STATUS REGISTER 1 BITs BIT NO NAME SYMBOL D0 MISSING MA ADDRESS MARK TABLE 5. STATUS REGISTER 2 BITs BIT NO NAME SYMBOL D7 D6 CONTROL CM MARK D5 DATA ERROR DD D4 WRONG WC CYLINDER D3 SCAN ...
Page 17
DATA REGISTER The eight-bit data Register stores data, comma- nds, parameters, and FDD status information. Data bytes are read out of, or written into, the Data Register in order to program or obtain the results after a particular command. ...
Page 18
BASE, SPECIAL, AND PC AT MODES Base, Special, and PC AT modes allow subtle differences which the user may find desirable. The Control Register may be used in any mode without altering functionality. * BASE MODE After a hardware ...
Page 19
HARDWARE RESET READ MASTER STATUS REG. BASE MODE WRITE TO OPER REG MODE Fig. 3 Flow Diagram Depicting Relationship of Base, Special, and PC AT modes. l POLLING ROUTINE DS1 DS2 DS3 DS4 * DEVECE RESETS The GM82C765B ...
Page 20
DATA SEPARATOR The Data Separator is a Digital Phase Lock Loop Floppy Disk Data Separator (DPLL). It was designed to address high performance error rates on floppy disk drives, and to performance in terms of available bit jitter tolerance. It ...
Page 21
CLOCK GENERATION This logical block provides all the clocks needed by the GM82C765B. They are: Sampling clock (SCLK), Write clock (WCLK), and the MASTER CLOCK (MCLK). SCLK drives the DPLL Data Separator used during data recovery. This Clocks’s frequency ...
Page 22
COMMAND PARAMETERS The GM82C765B is capable of performing 15 different commands. Each command is initiated by a multibyte transfer from the processor. The results after execution of the command may also be a multibyte transfer back to the processor. The ...
Page 23
TABLE 12. READ DELETED DATA R COMMAND EXECUTION RESULTS TABLE 13. WRITE DATA PHASE R COMMAND W X ...
Page 24
TABLE 14. WRITE DELETED DATA PHASE R COMMAND EXECUTION RESULTS TABLE 15. READ A TRACK PHASE R COMMAND ...
Page 25
TABLE 16. READ ID PHASE R COMMAND W X EXECUTION RESULTS TABLE 17. FORMAT A TRACK PHASE R COMMAND EXECUTION RESULTS ...
Page 26
TABLE 18. SCAN EQUAL PHASE R COMMAND EXECUTION RESULTS TABLE 19. SCAN LOW OR EQUAL PHASE R COMMAND ...
Page 27
TABLE 20. SCAN HIGH OR EQUAL PHASE R COMMAND EXECUTION RESULTS TABLE 21. RECALIBARTE PHASE R COMMAND W ...
Page 28
TABLE 24. SENSE DRIVE STATUS PHASE R COMMAND W X EXECUTION TABLE 25. SEEK R COMMAND EXECUTION Table 26 defines, in alphabetical order, the symbols used in Command Tables 11 through ...
Page 29
SYMBOL NAME N NUMBER NCN NEWCYLINDER NUMBER ND NON-DMA MODE PCN PRESENT CYLINDER R RECORD R/W READ/WRITE SC SECTOR SK SKIP SRT STEP RATE TIME ST0 STATUS 0 ST1 STATUS 1 STATUS 2 ST2 ST3 STATUS 3 STP US0, US1 ...
Page 30
DTL in the sector is not sent to the Data Bus. The FDC reads (internally) the complete sector performing the CRC check, and depending upon the manner of command termination, may perform a Multi-Sector Read operation. When N ...
Page 31
Write Data A set of nine bytes is required to set the into DC the Write Data mode, after the commawrite data and has been issued the FDC loads the head ( the unloaded state), waits the specified ...
Page 32
READ ID The Read ID command is used to give the present position of the recording head. The FDC stores the values from the first ID field it is able to read proper ID Address mark is found ...
Page 33
Scan Commands The Scan commands allow data which is being read from the diskette to be compared against data which is being supplied from the main system. The FDC compares the data on a byte-by-byte basis and looks for a ...
Page 34
The Read/Write head within the FDD is moved from cylinder to cylinder under control of the Seek command. FDC has four independent Present Cylinder Registers for each drive. They are cleared only after the Recalibrate command. The FDC compares the ...
Page 35
TABLE 31. INTERRUPT CAUSE Seek End Interrupt Code Bit Ready Line dhanged state, Bit 6 Bit 7 5 either polarity Normal Termination of Seek Recalibrate command Abnormal Termination Seek or Recalibrate command ...
Page 36
The Specify command sets the initial values for each of the three internal timers. The HUT(Head Unload Time) defines the time from the end of the Execution phase of one of the Read Write commands to the head unload state ...