HY57V161610ETP-7I Hynix Semiconductor, HY57V161610ETP-7I Datasheet

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HY57V161610ETP-7I

Manufacturer Part Number
HY57V161610ETP-7I
Description
Manufacturer
Hynix Semiconductor
Datasheet
DESCRIPTION
THE Hynix HY57V161610E is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the main memory and graphic appli-
cations which require large memory density and high bandwidth. HY57V161610E is organized as 2banks of 524,288x16.
HY57V161610E is offering fully synchronous operation referenced to a positive edge clock. All inputs and outputs are synchronized
with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 1,2 or 3), the number of consecutive read or write cycles initi-
ated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A
burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a
new burst read or write command on any cycle. (This pipeline design is not restricted by a `2N` rule.)
FEATURES
ORDERING INFORMATION
Note :
1. VDD(min) of HY57V161610ETP-5I/55I is 3.15V
2.
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for
use of circuits described. No patent licenses are implied
Rev. 0.1 / Nov. 2003
HY57V161610ETP-5I
HY57V161610ETP-55I
HY57V161610ETP-6I
HY57V161610ETP-7I
HY57V161610ETP-8I
HY57V161610ETP-10I
HY57V161610ETP-15I
Hynix supports lead free part for each speed grade with same specification.
Single 3.0V to 3.6V power supply
All device pins are compatible with LVTTL interface
JEDEC standard 400mil 50pin TSOP-II with 0.8mm of pin
pitch
All inputs and outputs referenced to positive edge of system
clock
Data mask function by UDQM/LDQM
Internal two banks operation
Part No.
Clock Frequency
200MHz
183MHz
166MHz
143MHz
125MHz
100MHz
66MHz
2 Banks x 512K x 16 Bit Synchronous DRAM
2Banks x 512Kbits x 16
Organization
Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
Programmable CAS Latency ; 1, 2, 3 Clocks
Pb-free Package
- 1, 2, 4, 8 and Full Page for Sequence Burst
- 1, 2, 4 and 8 for Interleave Burst
Interface
LVTTL
HY57V161610ETP-I
50pin TSOP II
Package
(Pb free)
400mil
1

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HY57V161610ETP-7I Summary of contents

Page 1

... Data mask function by UDQM/LDQM • Internal two banks operation ORDERING INFORMATION Part No. HY57V161610ETP-5I HY57V161610ETP-55I HY57V161610ETP-6I HY57V161610ETP-7I HY57V161610ETP-8I HY57V161610ETP-10I HY57V161610ETP-15I Note : 1. VDD(min) of HY57V161610ETP-5I/55I is 3.15V Hynix supports lead free part for each speed grade with same specification. 2. This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described ...

Page 2

... RAS, CAS and WE define the operation. Refer function truth table for details DQM control output buffer in read mode and mask input data in write mode Multiplexed data input / output pin Power supply for internal circuit and input buffer Power supply for DQ No connection HY57V161610ETP ...

Page 3

... Mode Register Rev. 0.1 / Nov. 2003 Refresh Counter Sense AMP & I/O gates Address Register Overflow Burst Length Counter Sense AMP & I/O gates HY57V161610ETP-I 512Kx16 Bank 0 Column Decoder Column Addr. Latch & Counter Column Decoder 512Kx16 Bank 1 Test Mode I/O Control ...

Page 4

... Output load capacitance for access time measurement Note : 1. Output load to measure access times is equivalent to two TTL gates and one capacitance(30pF). For details, refer to AC/DC output load circuit (min) is 3.15V when HY57V161610ETP-7I operates at CAS latency=2 and tCK2=8.9ns (min) of HY57V161610ETP-5I/55I is 3.15V‘ DD Rev. 0.1 / Nov. 2003 ...

Page 5

... Input leakage current IL Output leakage current IO Output high voltage V OH Output low voltage V OL Note : 1.V (min) is 3.15V when HY57V161610ETP-7I operates at CAS latency=2 and tCK2=8.9ns. DD 2.V (min) of HY57V161610ETP-5I/55I is 3.15V DD 3 3.6V, All other pins are not under test = 0V IN 4.D is disabled 3.6V OUT OUT Rev ...

Page 6

... All banks active Auto Refresh Current IDD5 Self Refresh Current IDD6 CKE Note : 1.V (min) is 3.15V when HY57V161610ETP-7I operates at CAS latency=2 and tCK2=8.9ns. DD 2.V (min) of HY57V161610ETP-5I/55I is 3.15V DD 3.I and I depend on output loading and cycle rates. Specified values are measured with the output open. ...

Page 7

... CLK to data output in low Z- tOLZ time CLK to data output in high tOHZ Z-time Rev. 0.1 / Nov. 2003 (TA=-40°C to 85°C, V =3.0V to 3.6V -55 Min Max Min Max 5 5 4.5 1.5 2 1.5 1 1.5 1 1.5 1 1.5 1 5.5 HY57V161610ETP-I Note1,2 = Min Max Min 2.5 1 1 ...

Page 8

... Note : 1.V (min) is 3.15V when HY57V161610ETP-7I operates at CAS latency=2 and tCK2=8.9ns. DD 2.V (min) of HY57V161610ETP-5I/55I is 3.15V DD 3.tCK2 is 8.9ns only when tAC2 is 7.9ns in HY57V161610ETP-6I and HY57V161610ETP-7I. 4.Assume (input rise and fall time ) is 1ns. Rev. 0.1 / Nov. 2003 (TA=-40°C to 85°C, V =3.0V to 3.6V ...

Page 9

... HY57V161610ETP-I Note1,2 = Max Min Max Min Max 100K 40 100K 45 100K ...

Page 10

... Precharge to data output Hi-Z Power down exit time Self refresh exit time Refresh Time Note : 1. V (min) is 3.15V when HY57V161610ETP-7I operates at CAS latency=2 and tCK2=8.9ns. DD 2.V (min) of HY57V161610ETP-5I/55I is 3.15V new command can be given tRRC after self refresh exit. DEVICE OPERATING OPTION TABLE ...

Page 11

... HY57V161610ETP-55I CAS Latency 183MHz 3CLKs 166MHz 3CLKs 143MHz 3CLKs HY57V161610ETP-6I CAS Latency 166MHz 3CLKs 143MHz 3CLKs 125MHz 3CLKs HY57V161610ETP-7I CAS Latency 143MHz 3CLKs 125MHz 3CLKs 100MHz 2CLKs HY57V161610ETP-8I CAS Latency 125MHz 3CLKs 100MHz 3CLKs 83MHz 2CLKs HY57V161610ETP-10I CAS Latency 100MHz 3CLKs ...

Page 12

... Exiting Self Refresh occurs by asynchronously bringing CKE from low to high. 2. X=Do not care, L=Low, H=High, BA=Bank Address, RA= Row Address, CA=Column Address, Opcode=Operand Code, NOP=No Operation. Rev. 0.1 / Nov. 2003 CKEn CS RAS CAS HY57V161610ETP-I A10/ WE DQM A0~ code Row Address Column Address Column Address Pin High (Other Pins OP code Note ...

Page 13

... PACKAGE INFORMATION 400mil 50pin Thin Small Outline Package (TC) 1Mx16 Synchronous DRAM 1.2(0.0472) 1.0(0.0394) 0.646 REF GAGE PLANE 0~5deg Rev. 0.1 / Nov. 2003 10.262(0.4040) 10.059(0.3960) 0.45(0.0177) 0.8(0.0315 BSC) 0.30(0.0118) 21.057(0.8290) 20.879(0.8220) 0.210(0.0083) 0.597(0.0235) 0.120(0.0118) 0.406(0.0160) HY57V161610ETP-I UNIT : mm(inch) 11.938(0.4700) 11.735(0.4620) 0.150(0.0059) 0.050(0.0020) 13 ...

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