HY57V64820HGLT-P Hynix Semiconductor, HY57V64820HGLT-P Datasheet

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HY57V64820HGLT-P

Manufacturer Part Number
HY57V64820HGLT-P
Description
Manufacturer
Hynix Semiconductor
Datasheet

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HY57V64820HGLT-P
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DESCRIPTION
The Hynix HY57V64820HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which
require large memory density and high bandwidth. HY57V64820HG is organized as 4banks of 2,097,152x8.
HY57V64820HG is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-
nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by
a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of read
or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or
write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
ORDERING INFORMATION
This document is a general product description and is subject to change without notice.Hynix Semiconductor does not assume any responsibility for use
of circuits described. No patent licenses are implied.
Rev. 0.5/Sep. 02
HY57V64820HGLT-5/55/6/7
HY57V64820HGT-5/55/6/7
Single 3.3 0.3V power supply
All device pins are compatible with LVTTL interface
JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin
pitch
All inputs and outputs referenced to positive edge of sys-
tem clock
Data mask function by DQM
Internal four banks operation
HY57V64820HGLT-H
HY57V64820HGLT-K
HY57V64820HGLT-P
HY57V64820HGLT-S
HY57V64820HGLT-8
HY57V64820HGT-K
HY57V64820HGT-H
HY57V64820HGT-P
HY57V64820HGT-S
HY57V64820HGT-8
Part No.
200/183/166/143MHz
200/183/166/143MHz
Clock Frequency
133MHz
133MHz
125MHz
100MHz
100MHz
133MHz
133MHz
125MHz
100MHz
100MHz
Low power
Power
Normal
4Banks x 2Mbits x8
4 Banks x 2M x 8Bit Synchronous DRAM
Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
Programmable CAS Latency ; 2, 3 Clocks
Organization
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
Interface
LVTTL
HY57V64820HG
400mil 54pin TSOP II
Package
1

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HY57V64820HGLT-P Summary of contents

Page 1

... HY57V64820HGT-P HY57V64820HGT-S HY57V64820HGLT-5/55/6/7 200/183/166/143MHz HY57V64820HGLT-K HY57V64820HGLT-H HY57V64820HGLT-8 HY57V64820HGLT-P HY57V64820HGLT-S This document is a general product description and is subject to change without notice.Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.5/Sep Banks 8Bit Synchronous DRAM • ...

Page 2

PIN CONFIGURATION PIN DESCRIPTION PIN PIN NAME CLK Clock CKE Clock Enable CS Chip Select BA0, BA1 Bank Address A0 ~ A11 Address Row Address Strobe, RAS, CAS, WE Column Address Strobe, Write Enable DQM Data Input/Output Mask DQ0 ~ ...

Page 3

FUNCTIONAL BLOCK DIAGRAM 2Mbit x 4banks x 8 I/O Synchronous DRAM Self refresh logic & timer CLK Row active CKE CS RAS CAS refresh WE Column Active DQM Bank Select A0 Address Registers A1 A11 BA0 BA1 Mode Registers Rev. ...

Page 4

ABSOLUTE MAXIMUM RATINGS Parameter Ambient Temperature Storage Temperature Voltage on Any Pin relative Voltage on V relative Short Circuit Output Current Power Dissipation Soldering Temperature Time Note : Operation at above absolute maximum ...

Page 5

CAPACITANCE (TA=25 C, f=1MHz) Parameter Input capacitance CLK A0 ~ A11, BA0, BA1, CKE, CS, RAS, CAS, WE, DQM Data input / output capacitance DQ0 ~ DQ7 OUTPUT LOAD CIRCUIT Output DC Output Load Circuit DC CHARACTERISTICS I Parameter Symbol ...

Page 6

... I depend on output loading and cycle rates. Specified values are measured with the output open DD1 DD4 2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II 3.HY57V64820HGT-7/K/H/8/P/S 4.HY57V64820HGLT-7/K/H/8/P/S Rev. 0.5/Sep. 02 =3.3 0.3V, V =0V Test Condition Burst length=1, One bank active ...

Page 7

AC CHARACTERISTICS I (AC operating conditions unless otherwise noted) -6 Parameter Symbol Min CAS tCK3 6 Latency = 3 System clock cycle time CAS tCK2 10 Latency = 2 Clock high pulse width tCHW 2.5 Clock low pulse width tCLW ...

Page 8

AC CHARACTERISTICS II Parameter Symbol Min t Operation RC 60 RAS Cycle Time Auto t RRC 60 Refresh t RAS to CAS Delay RCD 18 t RAS Active Time RAS 42 t RAS Precharge Time RAS to ...

Page 9

DEVICE OPERATING OPTION TABLE HYHY57V64820(L)T-6 CAS Latency 166MHz(6ns) 3CLKs 143MHz(7ns) 3CLKs 133MHz(7.5ns) 2CLKs 57V64820HG(L)T-7 CAS Latency 143MHz(7ns) 3CLKs 133MHz(7.5ns) 3CLKs 100MHz(10ns) 2CLKs HY57V64820HG(L)T-K CAS Latency 133MHz(7.5ns) 2CLKs 125MHz(8ns) 3CLKs 100MHz(10ns) 2CLKs HY57V64820HG(L)T-H CAS Latency 133MHz(7.5ns) 3CLKs 125MHz(8ns) 3CLKs 100MHz(10ns) 2CLKs ...

Page 10

COMMAND TRUTH TABLE Command CKEn-1 Mode Register Set No Operation Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Burst Stop DQM Auto Refresh Burst-READ-Single-WRITE Entry 1 Self Refresh Exit Entry Precharge power ...

Page 11

PACKAGE INFORMATION 400mil 54pin Thin Small Outline Package 22.327(0.8790) 22.149(0.8720) 0.150(0.0059) 0.050(0.0020) 0.400(0.016) 0.80(0.0315)BSC 0.300(0.012) Rev. 0.5/Sep. 02 UNIT : mm(inch) 11.938(0.4700) 11.735(0.4620) 10.262(0.4040) 10.058(0.3960) 5deg 0.597(0.0235) 0.210(0.0083) 0deg 0.120(0.0047) 0.406(0.0160) HY57V64820HG 1.194(0.0470) 0.991(0.0390) 11 ...

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