HY57V283220T-6 Hynix Semiconductor, HY57V283220T-6 Datasheet

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HY57V283220T-6

Manufacturer Part Number
HY57V283220T-6
Description
Manufacturer
Hynix Semiconductor
Datasheet

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This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume
any responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.9 / July 2004
Revision History
Revision No.
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Defined Preliminary Specification
1) Modified FBGA Ball Configuration Typo.
2) Changed Functional Block Diagram from A10 to A11.
3) Changed V
4) Changed Cap. Value from C11, 3, 5 to 4pf & C12, 3.8 to 4pf.
5) Insert t
6) Insdrt t
Defined I
Delited Preliminary.
Changed I
133MHz Speed Added
Changed FBGA Package Size from 11x13 to 8x13.
1) Changed V
2) Changed V
Modified of size erra. (Page15)
(Equation :
DD
AC2
RAS
DD
13.00 ± 10
Spec.
DD
DD
IL
Spec.
Value.
& CLK Value.
min from V
HY57V283220(L)T(P)/ HY5V22(L)F(P)
min from 3.0V to 3.135V.
min from 3.135V to 3.0V.
-> 13.00 ± 0.10)
4 Banks x 1M x 32Bit Synchronous DRAM
SSQ
History
-0.3V to -0.3V.
Remark

Related parts for HY57V283220T-6

HY57V283220T-6 Summary of contents

Page 1

... Changed V Modified of size erra. (Page15) 0.9 (Equation : This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.9 / July 2004 HY57V283220(L)T(P)/ HY5V22(L)F(P) 4 Banks 32Bit Synchronous DRAM History min from 3 ...

Page 2

... HY5V22(L)F(P)-S Note) Hynix supports lead free part for each speed grade with same specification. This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. ...

Page 3

PIN CONFIGURATION ( HY57V283220(L)T(P) Series) PIN DESCRIPTION PIN CLK Clock CKE Clock Enable CS Chip Select BA0, BA1 Bank Address A0 ~ A11 Address Row Address Strobe, RAS, CAS, WE Column Address Strobe, Write Enable DQM0~3 Data Input/Output Mask DQ0 ...

Page 4

Ball CONFIGURATION ( HY5V22(L)F(P) Series DQ26 DQ26 DQ26 DQ26 DQ26 DQ26 DQ26 DQ26 DQ26 DQ26 DQ26 DQ26 DQ26 DQ26 DQ26 DQ26 DQ26 DQ26 DQ26 DQ26 ...

Page 5

FUNCTIONAL BLOCK DIAGRAM 1Mbit x 4banks x 32 I/O Synchronous DRAM Self Refresh Logic Self Refresh Logic & Timer & Timer CLK CLK Row Active Row Active CKE CKE CS CS RAS RAS CAS CAS WE WE Column Column DQM0 ...

Page 6

ABSOLUTE MAXIMUM RATINGS Parameter Ambient Temperature Storage Temperature Voltage on Any Pin relative Voltage on V relative Short Circuit Output Current Power Dissipation Soldering Temperature Þ Time Note : Operation at above absolute ...

Page 7

... CAPACITANCE ( HY57V283220T Series) Parameter Input capacitance Data input / output capacitance OUTPUT LOAD CIRCUIT Output DC Output Load Circuit DC CHARACTERISTICS I Parameter Input leakage current Output leakage current Output high voltage Output low voltage Note : 1 3.6V, All other pins are not under test = ...

Page 8

... Specified values are measured with the output open DD1 DD4 2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II 3.HY57V283220T(P)(HY5V22F(P))-5/55/6/7/H/8/P/S 4.HY57V283220LT(P)(HY5V22LF(P))-5/55/6/7/H/8/P/S Rev. 0.9 / July 2004 HY57V283220(L)T(P) / HY5V22(L)F(P) (DC operating conditions unless otherwise noted) ...

Page 9

AC CHARACTERISTICS I Parameter Symbol CAS Latency = 3 tCK3 System clock cycle time CAS Latency = 2 tCK2 Clock high pulse width tCHW Clock low pulse width tCLW CAS Latency = 3 tAC3 Access time from clock CAS Latency ...

Page 10

AC CHARACTERISTICS II Parameter Symbol Operation tRC RAS cycle time Auto Refresh tRRC RAS to CAS delay tRCD RAS active time tRAS RAS precharge time tRP RAS to RAS bank active delay tRRD CAS to CAS delay tCCD Write command ...

Page 11

DEVICE OPERATING OPTION TABLE HY5xxxxxxxxx(P)-5 CAS Latency 200MHz(5ns) 3CLKs 183MHz(5.5ns) 3CLKs 166MHz(6ns) 3CLKs HY5xxxxxxxxx(P)-55 CAS Latency 183MHz(5.5ns) 3CLKs 166MHz(6ns) 3CLKs 143MHz(7ns) 3CLKs HY5xxxxxxxxx(P)-6 CAS Latency 166MHz(6ns) 3CLKs 143MHz(7ns) 3CLKs 125MHz(8ns) 3CLKs HY5xxxxxxxxx(P)-7 CAS Latency 143MHz(7ns) 3CLKs 125MHz(8ns) 3CLKs 100MHz(10ns) 2CLKs ...

Page 12

HY5xxxxxxxxx(P)-P CAS Latency 100MHz(10ns) 2CLKs 83MHz(12ns) 2CLKs 66MHz(15ns) 2CLKs HY5xxxxxxxxx(P)-S CAS Latency 100MHz(10ns) 3CLKs 83MHz(12ns) 2CLKs 66MHz(15ns) 2CLKs Rev. 0.9 / July 2004 HY57V283220(L)T(P) / HY5V22(L)F(P) tRCD tRAS tRC 2CLKs 5CLKs 7CLKs 2CLKs 5CLKs 7CLKs 2CLKs 4CLKs 6CLKs tRCD tRAS ...

Page 13

COMMAND TRUTH TABLE Command CKEn-1 Mode Register Set H No Operation H Bank Active H Read H Read with Autoprecharge Write H Write with Autoprecharge Precharge All Banks H Precharge selected Bank Burst Stop H DQM H Auto Refresh H ...

Page 14

... PACKAGE INFORMATION (HY57V283220T(P) Series) 400mil 86pin Thin Small Outline Package 22.327(0.8790) 22.149(0.8720) 0.50(0.0197) Rev. 0.9 / July 2004 HY57V283220(L)T(P) / HY5V22(L)F(P) 11.938(0.4700) 11.735(0.4620) 10.262(0.4040) 10.058(0.3960) 0.150(0.0059) 0.050(0.0020) 5deg 0.21(0.008) 0deg 0.18(0.007) Unit : mm(inch) 1.194(0.0470) 0.991(0.0390) 0.210(0.0083) 0.597(0.0235) 0.120(0.0047) 0.406(0.0160) 14 ...

Page 15

PACKAGE INFORMATION (HY5V22F(P) Series) 90Ball FBGA with 0.8mm of pin pitch (Ball-side view) 11.20 5.60 ± 0.5 1.20max seating plane Rev. 0.9 / July 2004 HY57V283220(L)T(P) / HY5V22(L)F(P) 6.40 3.20 ± 0.5 4.00 ± 0.5 8.00 0.80(typ) pin#1 ID 0.80 ...

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