MB91302A Fuji Electric holdings CO.,Ltd, MB91302A Datasheet

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... Kbytes and RAM of 4 Kbytes( for data) are included for high-speed execution of CPU instructions. The MB91302A and MB91V301A are FR60 products based on the FR30/40 CPU with enhanced bus access for higher speed operation. The device specifications include a D/A converter to facilitate motor control and are ideal for use in DVD players that support fly-by transfer ...

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... Permission/prohibition setting of fetch into built-in cache • Permission/prohibition setting of prefetch function • DMA supports fly-by transfer with independent I/O wait control • External bus arbitration can be used using BRQ and BGRNT. 3. Built-in memory • 4 Kbytes DATA RAM • 4 Kbytes RAM (MB91302A (Continued) ...

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Instruction cache • Size : 4 Kbytes • 2-way set associative • 128 blocks/way, 4 entries/block • Lock function enables program code to be made cache-resident • Areas not used for instruction cache can be used as instruction RAM ...

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... Package *1 : The Fujitsu product of real time OS REALOS/FR by conforming to the ITRON 3.0 is stored and optimized with the MB91302A The ROM stores the IPL (Internal Program Loader) . Loading various programs can be executed from the external system by the internal UART/SIO. Using this function, for example, writing on board to the Flash memory connected to the external can be executed ...

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... PIN ASSIGNMENTS • MB91302A 1 P13/D11 2 P14/D12 P15/D13 3 4 P16/D14 5 P17/D15 P20/D16 8 9 P21/D17 10 P22/D18 11 P23/D19 P24/D20 12 13 P25/D21 14 P26/D22 15 P27/D23 D24 19 D25 D26 20 21 D27 22 D28 23 D29 D30 24 25 D31 P80/RDY 29 P81/BGRNT 30 P82/BRQ DQMUU/WR0(UUB) P85/DQMUL/WR1(ULB P86/DQMLU/WR2(LUB) 35 P87/DQMLL/WR3(LLB) 36 P90/SYSCLK MB91301 Series (TOP VIEW) ...

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MB91301 Series • MB91V301A 5 1 178 174 7 2 179 177 ...

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MB91V301A Pin No. Table No. PIN Pin Name No N. P13/D11 P14/D12 P15/D13 P16/D14 37 8 ...

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MB91301 Series (Continued) No. PIN Pin Name 91 L11 ICD2 92 N13 ICD1 93 N12 ICD0 94 P13 R15 M11 BREAK 97 R14 ICLK 98 N11 ICS2 99 P12 ICS1 100 R13 ICS0 101 ...

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... PIN DESCRIPTIONS • Except for Power supply, GND, and Tool pins Pin no. Pin name MB91302A MB91V301A D00 to D07 166 to 169, 132 to 139 172 to 175 P00 to P07 D08 to D15 142 to 144, 178 to 180 P10 to P17 D16 to D23 P20 to P27 D24 to D31 ...

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... MB91301 Series Pin no. Pin name MB91302A MB91V301A WR1/ (ULB WR2/ (LUB WR3/ (LLB SYSCLK I/O circuit type External bus write strobe output. The pin has this function when WR1 output is enabled. When WR is used as the write strobe, this becomes the byte- DQMUL enable pin (ULB) ...

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... Pin no. Pin name MB91302A MB91V301A AS LBA 40 49 SRAS P94 BAA 41 50 SCAS P95 SWE P96 A00 to A07 A08 to A15 A16 to A19 P60 to P63 MB91301 Series I/O circuit Function type Address strobe output. The pin has this function when ASE bit of port function register 9 is enabled “ ...

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... CLK input pin for I enable when typical operation of I SCL0 port output must remains off unless intentionally turned on. (open drain output) (This function is only for MB91302A, MB91V301A.) T External address bus bit 21. A21 This function is enable during prohibited I operation and using external bus. ...

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... C bus function. This function is enable when typical operation of I port output must remains off unless intentionally turned on. (open drain output) (This function is only for MB91302A, MB91V301A.) T External address bus bit 21. This function is enable during prohibited I operation and using external bus. ...

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... MB91301 Series Pin no. Pin name MB91302A MB91V301A 87 117 88 118 90 120 91 121 92 122 93 123 94 124 95 125 96 126 14 I/O circuit type External interrupt input. This input is used continuously when the corresponding external INT6 interrupt is enabled. In this case, do not output to these ports unless doing so intentionally. ...

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... Pin no. Pin name MB91302A MB91V301A TRG0 97 127 PJ7 TIN0 98 128 PH0 TIN1 99 129 PPG3 PH1 TIN2 100 130 TRG3 PH2 DREQ0 103 133 PB0 DACK0 104 134 PB1 DEOP0 105 135 PB2 MB91301 Series I/O circuit Function type External trigger input for PPG timer. ...

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... MB91301 Series Pin no. Pin name MB91302A MB91V301A DREQ1 106 136 DACK1 107 137 DEOP1 108 138 109 139 110 140 112 143 113 144 116 to 118 147 to 149 MD0 to MD2 119 152 120 053 16 I/O circuit type DMA External input for DMA transfer requests. This input is used continuously when selected as a DMA activation trigger ...

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... Pin no. Pin name MB91302A MB91V301A CS0 122 156 PA0 CS1 123 157 PA1 CS2 124 158 PA2 CS3 125 159 PA3 CS4 126 160 TRG2 PA4 CS5 PPG2 127 161 PA5 CS6 128 162 PA6 CS7 129 163 PA7 MB91301 Series ...

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MB91301 Series I/O CIRCUIT TYPE Type Standby control P- Standby control D Control 18 Circuit Clock input P-ch N-ch Digital input P-ch Digital output N-ch Digital output Digital input P-ch N-ch Analog input Remarks Oscillation ...

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Type Circuit P-ch N-ch G P-ch J Standby control P-ch K Standby control P-ch L P-ch N-ch M CMOS level output No standby control Digital input With Pull-up control Pull-up control CMOS level I/O P-ch with standby control Digital output ...

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MB91301 Series Type N- Circuit P-ch Digital output N-ch Digital output Digital input Digital input Digital input P-ch Digital output N-ch Digital output Digital input P-ch Digital output N-ch Digital output ...

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Type P- Circuit N-ch open-drain output CMOS level I/O with standby control Pull-up control P-ch Without pull-up control Digital output with I OL open-drain control N-ch Digital output Digital input CMOS level output CMOS level hysteresis ...

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MB91301 Series HANDLING DEVICES MB91301 series Operation at start-up Always apply a settings initialization (INIT) to the INIT pin immediately after turning on the power. Also, in order to provide a delay while the oscillator circuits stabilize immediately after start-up, ...

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Preventing Latchup When CMOS integrated circuit devices are subjected to applied voltages higher than V pins voltages lower than well as when voltages in excess of rated levels are applied between V SS and V ...

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MB91301 Series Notes on during operation of PLL clock mode If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. ...

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I-bus memory Do not set a stack area or vector table in I-bus memory. It may cause a hang during EIT processing (including RETI). Recovery from the hang requires a reset. Do not perform DMA transfer to I-bus memory. Low-power ...

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MB91301 Series R15 (General purpose register) When any of the following instructions is executed, the SSP* or USP* value is not used as R15, resulting in an incorrect value written to memory. AND R15, @Ri OR R15, @Ri EOR R15, ...

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Unique to the evaluation chip MB91V301A Tool reset On an evaluation board, use the chip with INIT and TRST connected together. Simultaneous occurrences of a software break and a user interrupt/NMI When a software break and a user interrupt /NMI ...

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MB91301 Series Configuration batch file The example batch file below sets the mode vector and sets up the CS0 configuration register for the download area. Use values appropriate to the hardware in the wait, timing, and other settings. #--------------------------------------------------------- # ...

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... BLOCK DIAGRAM • MB91302A, MB91V301A Bit search module MB91302A : RAM 4 KB MB91V301A : RAM 8 KB (stack) MB91302A : ROM 4 KB* MB91V301A : RAM 8 KB X0, X1 MD0 to MD2 Clock INIT control Interrupt controller 8 channels INT0 to INT7 External interrupts NMI SIN0 to SIN2 3 channels SOT0 to SOT2 UART ...

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MB91301 Series CPU 1. Memory Space The FR family has 4 Gbytes (2 Direct Addressing Areas The following areas of address space are used for I/O operations. These areas are called direct addressing areas, in which the address of an ...

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... FFFF FFFF H MB91302A has non-ROM model, the optimal real time OS internal model, and the IPL (Internal program Loader) internal model by adding the user ROM model specific area between 10000 Refer to “ INSTRUCTION CACHE” The real time OS internal model stores the real time OS kernel. The program loader internal model stores the program loader ...

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MB91301 Series 2. Registers The FR series has two types of registers: application-specific registers in the CPU and general purpose registers in memory. Dedicated registers Program counter (PC) : 32-bit register. Stores the current instruction address. Program status (PS) : ...

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Return pointer (RP) The RP is the return pointer and stores the subroutine return address. RP System stack pointer (SSP) The SSP is the system stack pointer and functions as R15 when the S flag is “0”. SSP User stack ...

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MB91301 Series Program status (PS) This register holds the program status and is divided into the ILM, SCR, and CCR. Bit position 31 Condition code register (CCR) S flag : Specifies which stack pointer to use as R15. I flag ...

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GENERAL PURPOSE REGISTERS General purpose registers R0 to R15 are used by the CPU. The registers are used as the accumulator and memory access pointers for CPU operations R12 R13 R14 R15 The following three registers are treated ...

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... External ROM vector mode Values other than those listed in the table are prohibited Single chip mode is able to set only MB91302A. 2. Mode Register (MODR) • Details of mode register (MODR) The data written to the mode register by the mode vector fetch operation (see “3.11.3 reset sequences”) is called the mode data ...

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... The MB91V301A supports only bus mode 2 (external-ROM, external-bus mode). See “1. Memory Space” in CPU for details. • Bus mode0 (single chip mode) (only MB91302A) The internal I/O, 4 Kbytes D-bus RAM, 32 Kbytes F-bus RAM (FRAM) and 96 Kbytes F-bus ROM are valid, while access to any other areas is invalid under this mode ...

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MB91301 Series I/O MAP This shows the location of the various peripheral resource registers in the memory space. [How to read the table] Address 0 PDR0 [R/W] B PDR1 [R/W] B 000000 H XXXXXXXX Read/write attribute, Access type Initial value ...

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Address 0 PDR0 [R/W] B PDR1 [R/W] B 000000 H XXXXXXXX 000004 H PDR8 [R/W] B PDR9 [R/W] B 000008 H XXXXXXXX 00000C H PDRG [R/W] B PDRH [R/W] B 000010 H XXXXXXXX 000014 H to 00003C H EIRR [R/W] ...

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MB91301 Series Address 0 SSR2 [R/ 000070 H 00001000 UTIM2 [ (UTIMR2 [ 000074 H 00000000 00000000 ADCR [ 000078 H 000000XX XXXXXXXX ADCR0 [ 00007C ...

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Address 0 IPCP3 [R/ 0000DC H XXXXXXXX_XXXXXXXX ICS23 [R/ 0000E0 H 0000E4 H to 000114 H GCN10 [R/W] H 000118 H 00110010 00010000 000011C H PTMR0 [R] H 000120 H 11111111 11111111 PDUT0 [W] H, ...

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MB91301 Series Address 0 000214 H 00000000 00000000 XXXXXXXX XXXXXXXX 000218 H 00000000 0000XXXX XXXXXXXX XXXXXXXX 00021C H 00000000 00000000 XXXXXXXX XXXXXXXX 000220 H 00000000 0000XXXX XXXXXXXX XXXXXXXX 000224 H 00000000 00000000 XXXXXXXX XXXXXXXX 000228 H to 00023C H 000240 ...

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Address 0 000404 H to 00040C H PFRG [R/W] B PFRH [R/W] B 000410 000414 H to 00041C H PCRH [R/W] B 000420 H 000424 H to 00043C H ICR00 [R/W] B, ...

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MB91301 Series Address 0 ICR44 [R/ 00046C 11111 000470 H to 00047C H RSRR [R, R/ 000480 10000000 (INIT (INIT) XXX - - ...

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Address 0 000630 H to 00063C H ASR0 [R/ 000640 H 00000000 00000000 ASR1 [R/ 000644 H XXXXXXXX XXXXXXXX ASR2 [R/ 000648 H XXXXXXXX XXXXXXXX ASR3 [R/ 00064C H XXXXXXXX XXXXXXXX ASR4 ...

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MB91301 Series Address 0 00068C H to 0007F8 H 0007FC H 000800 H to 000AFC H ESTS0 [R/W] B 000B00 H X0000000 ECTL0 [R/W] B 000B04 H 0X000000 ECNT0 [W] B 000B08 H XXXXXXXX EWPT [R] H 000B0C H 00000000 ...

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Address 0 000B48 H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B4C H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B50 H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B54 H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B58 H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B5C H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B60 H ...

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MB91301 Series (Continued) Address 0 001024 H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001028 H to 001FFC Byte access is not permitted for the lower 16 bits of DMAC0 to DMAC4 (DTC15 to DTC0 This register ...

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INTERRUPT VECTORS Interrupt Reset Mode vector System reserved System reserved System reserved System reserved System reserved Coprocessor absent trap Coprocessor error trap INTE instruction Instruction break exception Operand break trap Step trace trap NMI request (tool) Undefined instruction exception NMI ...

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MB91301 Series Interrupt DMAC0 (end, error) DMAC1 (end, error) DMAC2 (end, error) DMAC3 (end, error) DMAC4 (end, error) A/D PPG0 PPG1 PPG2 PPG3 System reserved U-TIMER0 U-TIMER1 U-TIMER2 Time base timer overflow I/ I/F1 ...

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Interrupt System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved Used by INT instruction *1 : ICRs are registers built in the ...

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MB91301 Series INSTRUCTION CACHE The instruction cache is a fast local memory for temporary storage. Once an instruction code is accessed from external slower memory, the instruction cache holds the instruction code inside to increase the speed of access- ing ...

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Instruction Cache Tags Way 1 31 Address tag Way 2 31 Address tag [bit 31 to bit 9] Address tag The address tag stores the upper 23 bits of the memory address of the instruction cached in the corresponding block. ...

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MB91301 Series Control Registers Cache Size Register (ISIZE) bit 7 Address : 00000307 H Instruction Cache Control Register (ICHCR) The instruction cache (I-cache) control register (ICHCR) controls the operations of the instruction cache. Writing a value to the ICHCR has ...

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Address Cache 4 K Cache 2 K 000 H $RAM1 200 H $RAM1 400 H IRAM1 600 H 000 H $RAM2 200 H $RAM2 400 H IRAM2 600 H ROMA 1 ROMA 0 (ROM present) (ROM absent) Address 00000000 H ...

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MB91301 Series PERIPHERAL RESOURCES 1. External Bus Interface Controller External Bus Interface Controller Features • Maximum output address width = 32-bit (4 Gbytes memory space) • Various different types of external memory (8-bit, 16-bit, or 32-bit devices) can be directly ...

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Block Diagram Internal Internal address bus data bus 32 32 write buffer read buffer address buffer ASR ASZ switch MUX switch comparator SDRAM control RCR under flow refresh counter External pin controller All block control registers & ...

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MB91301 Series I/O pin External interface pin (Some pins are general purpose pins.) The following shows I/O pins of each interface. • Normal bus interface A23 to A00, D31 to D00 (AD15 to AD00) CS0, CS1, CS2, CS3, CS4, CS5, ...

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Register List ASR0 ACR0 ASR1 ACR1 ASR2 ACR2 ASR3 ACR3 ASR4 ACR4 ASR5 ACR5 ASR6 ACR6 ASR7 ACR7 AWR0 AWR1 AWR2 AWR3 AWR4 AWR5 AWR6 AWR7 MCRA MCRB Reserved Reserved Reserved Reserved IOWR0 ...

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MB91301 Series 2. I/O Ports MB91301 series pins can be used as I/O ports when not set for use by the external bus interface or the various peripheral I/O functions. I/O port (with pull-up resistor) block diagram Port Bus Peripheral ...

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Notes : Use byte access to access ports. The external bus function has priority for port 0 to port A when these are used as external bus pins. Accordingly, writing to the DDR has no effect on the pin input/output ...

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MB91301 Series Port Data Register (PDR) PDR0 7 P07 Address : 00000000 H R/W PDR1 7 P17 Address : 00000001 H R/W PDR2 7 P27 Address : 00000002 H R/W PDR6 7 P67 Address : 00000006 H R/W PDR8 7 ...

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Data Direction Register (DDR) DDR0 7 P07 P06 Address : 00000600 H R/W R/W DDR1 7 P17 P16 Address : 00000601 H R/W R/W DDR2 7 P27 P26 Address : 00000602 H R/W R/W DDR6 7 P67 P66 Address : ...

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MB91301 Series Pull-up Resistor Control Register (PCR) PCR0 bit Address : 00000620 H PCR1 bit Address : 00000621 H PCR2 bit Address : 00000622 H PCR6 bit Address : 00000626 H PCR8 bit Address : 00000628 H PCR9 bit Address ...

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Port Function Register (PFR) PFR6 bit Address : 00000616 H A23E R/W PFR8 bit Address : 00000618 H WR3XE R/W PFR9 bit Address : 00000619 H R/W PFRA1 bit Address : 0000061A H CS7XE R/W PFRB1 bit Address : ...

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MB91301 Series 3. Interrupt Controller The interrupt controller receives and processes interrupts. Hardware Configuration The interrupt controller consists of the following : • ICR register • Interrupt priority determination circuit • Interrupt level and interrupt number (vector) generator • Hold ...

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Register List bit 7 Address : 00000440 H Address : 00000441 H Address : 00000442 H Address : 00000443 H Address : 00000444 H Address : 00000445 H Address : 00000446 H Address : 00000447 H Address : 00000448 H ...

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MB91301 Series (Continued) bit 7 Address : 00000460 H Address : 00000461 H Address : 00000462 H Address : 00000463 H Address : 00000464 H Address : 00000465 H Address : 00000466 H Address : 00000467 H Address : 00000468 ...

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External Interrupt/NMI Control Block The external interrupt control block controls external interrupt requests input to the NMI and INT0 to INT7 pins. The interrupt trigger level can be selected from "H", "L", "rising edge", or "falling edge" (except for ...

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MB91301 Series 5. Delay Interrupt Module The delay interrupt module is used to generate interrupts for task switching. This module can be used to generate and cancel interrupts to the CPU via software. Block Diagram Interrupt request Register List Delay ...

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PPG Timer The PPG timer can output highly precise PWM waveforms efficiently. The MB91301 series contains four channels of PPG timer. Features of the PPG Timer • Each channel consists of a 16-bit down counter, a 16-bit data register ...

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MB91301 Series Block diagram 16-bit reload timer ch0 16 bit reload timer - ch1 General control register 2 External TRG0 to TRG3 Block diagram for 1 channel Prescaler ...

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Register List bit 15 7 GCN10 PTMR0 PCSR0 PDUT0 PCNH0 PTMR1 PCSR1 PDUT1 PCNH1 PTMR2 PCSR2 PDUT2 PCNH2 PTMR3 PCSR3 PDUT3 PCNH3 MB91301 Series 0 General control register 10 General control register 20 GCN20 ch0 timer register ch0 cycle setting ...

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MB91301 Series 7. 16-Bit Reload Timer The 16-bit timer consists of a 16-bit down-counter, 16-bit reload register, prescaler for generating the internal count clock, and a control register. The clock source can be selected from three internal clock signals (machine ...

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Register List Control status register (TMCSR) bit 15 14 bit 7 6 MOD0 16-bit timer register (TMR) bit 15 16-bit reload register (TMRLR) bit 15 MB91301 Series CSL1 CSL0 MOD2 ...

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MB91301 Series 8. U-TIMER (16 bit timer for UART baud rate generation) The U-TIMER is a 16-bit timer used to generate the baud rate for the UART. Any desired baud rate can be set using the combination of the chip ...

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Register List 15 • U-TIMER (UTIM) Address bit 15 14 000064 ( b15 b14 00006C ( 000074 ( UTIM contains the timer value. Use a 16-bit transfer instruction to access the register. ...

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MB91301 Series 9. UART The UART is a serial I/O port for asynchronous (start-stop synchronized) or CLK synchronized transmission. The MB91301 series has three UART channels. UART Features • Full duplex double buffer • Asynchronous (start-stop synchronized) or CLK synchronized ...

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Block Diagram Control signal From U-TIMER Clock selection circuit External clock SCK SI (Receive data) Receive status decision circuit Receive error signal for DMA (to DMAC) MD1 MD0 SMR register CS0 SCKE MB91301 Series TX clock RX clock RX control ...

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MB91301 Series Register List 15 Serial input data register Serial output data register (SIDR/SODR) bit 7 D7 Serial status register (SSR) bit 7 PE ORE Serial mode register (SMR) bit 7 MD1 MD0 Serial control register (SCR) bit 7 PEN ...

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A/D Converter (Successive Approximation Type) The A/D converter converts analog input voltages to digital values. A/D Converter Features • Peripheral clock (CLKP) 140 clock cycle • Minimum conversion time 4.1 s/ch (for machine clock 34 MHz • Built-in sample ...

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MB91301 Series Block Diagram Sample & hold circuit AN0 AN1 AN2 AN3 Channel decoder Timing generation circuit Machine clock (CLKP) ATG (External pin trigger) Reload timer ch2 (internal connection) Register List Control status register (ADCS) bit 15 BUSY bit 7 ...

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DMAC (DMA Controller) The DMA controller is used to perform DMA (direct memory access) transfer on the FR family device. Using DMA transfer under the control of the DMA controller improves system performance by enabling data to be transferred ...

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MB91301 Series Block Diagram DMA transfer request to bus controller DTC two-stage register Read/write Read Write control DDNO Access Write back ad- dress Write back 84 Counter DMA start trigger Buffer selection circuit & request Selector acknowledge control DTCR Counter ...

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Register List ch 0 control status ch 0 control status ch 1 control status ch 1 control status ch 2 control status ch 2 control status ch 3 control status ch 3 control status ch 4 control status ch 4 ...

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MB91301 Series 12 Interface interface is the serial I/O port that support INTER IC BUS and functions as the master/slave device on the bus. It has the features below. • Master/slave ...

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Block Diagram (1 ch) ICCR I EN IDBL DBL ICCR CS4 CS3 CS2 CS1 CS0 IBSR Bus busy BB Repeat start RSC Last Bit LRB Transmission/ reception TRX ADT AL IBCR BER BEIE INTE INT IBCR ...

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MB91301 Series Register List Bus control register (IBCR0/1) Address : 000094 /0000B4 H H Initial value Bus status register (IBSR0/1) Address : 000095 /0000B5 H H Initial value 10-bit slave address register (ITBA0/1) Address : 000096 /0000B6 H H Initial ...

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Address : 15 000098 /0000B8 H H ENTB R/W Initial value 0 Address : 7 000099 /0000B9 H H TM7 R/W Initial value 1 7-bit slave address register (ISBA0/1) Address : 7 00009B ...

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MB91301 Series 13. 16 bit Free Run Timer 16-bit free-run timer consists of a 16-bit up counter and a control status register. The timer count value is used as the base timer of output compare and input capture. • The ...

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Block Diagram ECLK IVF 16-bit Free run Timer Register List T15 T14 T13 T07 T06 T05 ECLK IVF IVFE Interrupt IVFE STOP MODE CLR CLK1 Clock (TCDT) Comparator0 ...

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MB91301 Series 14. Input Capture This module has a function that detects a rising edge, falling edge or both edges and holds a value of the 16-bit free-run timer in a register at the time of detection. It can also ...

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Block Diagram 16-bit timer count value (T15 to T00) Capture data register ch (0, 2) 16-bit timer count value (T15 to T00) Capture data register ch (1, 3) MB91301 Series ICU0, ICU2 Edge detection input pin EG11 EG10 EG01 EG31 ...

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MB91301 Series Register List CP15 CP14 CP13 CP07 CP06 CP05 ICP3 ICP2 ICE3 ICP1 ICP0 ICE1 CP12 CP11 CP10 CP09 CP08 4 ...

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Clock Generation Control The internal operating clock is generated as follows in MB91301 series. Source clock selection : Selects the clock source. Base clock generation : The base clock is generated by dividing the source clock ...

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MB91301 Series Block Diagram [Clock generator] Osc illa- X0 tion X1 it circu Internal interrupt Internal reset [Reset circuit] INIT pin [Watchdog controller] 96 DIVR0, 1 register CPU clock division Peripheral clock division External bus clock division CLKR register PLL ...

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Register List • RSRR : Reset initiation register/Watchdog timer control register bit 15 Address : 00000480 INIT H R Initial value (INIT pin) 1 Initial value (INIT) Initial value (RST) X • STCR : Standby control register bit 7 Address ...

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MB91301 Series (Continued) WPR : Watchdog reset generation delay register • bit 7 Address : 00000485 Initial value (INIT) X Initial value (RST) X DIVR0 : Base clock division setting register 0 • bit 15 Address : ...

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ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Symbol Supply voltage Analog supply voltage AVRH, Analog reference voltage Input voltage Analog pin input voltage Output voltage “L” level maximum output current “L” level average output current “L” level total maximum output ...

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MB91301 Series 2. Recommended Operating Conditions Parameter Supply voltage Analog supply voltage Analog reference voltage Operating temperature <Notes on turning the power on> The maximum power rising slope ( V/ t) must be 0. when the 3 V ...

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DC Characteristics Sym- Parameter Pin name bol Non-hystere sis input pin “H” level input voltage Hysteresis V IHS input pin Non-hystere sis input pin “L” level input voltage Hysteresis V ILS input pin “H” level ...

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MB91301 Series 4. AC Characteristics (1) Clock Timing Ratings Sym- Parameter bol Clock frequency (1) f Clock cycle time t Clock frequency ( Internal operation clock f CPP frequency f CPT t CP Internal operation clock t ...

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External/internal clock setting range fcp, f MHz CPT multiplier (CPU CPP 34 5 multiplier, 2 divide (CPU, peripheral 22.7 5 multiplier, 3 divide 20 (CPU, peripheral ...

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MB91301 Series (2) Clock Output Timing Sym- Parameter bol Cycle time t CYC SYSCLK SYSCLK t CHCL SYSCLK SYSCLK t CLCH V OH SYSCLK MCLK * the frequency of one clock cycle after gearing. CYC *2 : ...

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Normal Bus Access Read/Write Operation Sym- Parameter bol CS0 to CS7 setup t CSLCH CS0 to CS7 hold t CHCSH t ASCH Address setup t ASWL t ASRL t CHAX Address hold t WHAX t RHAX Valid address t ...

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MB91301 Series V OH MCLK SYSCLK AS (LBA) CS0 to CS7 A23 to A00 RD D31 to D00 WR0 to WR3 WR (at WR-control) D31 to D00 WR0 to WR3 (UUB, ULB, LUB, LLB) (at WR-control) 106 t CYC BA1 ...

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BAA Timing Sym- Parameter bol BAA setup t CHBAH BAA hold t CHBAL t CYC MCLK SYSCLK t CHBAL BAA ( Pin name Condition Min t 2 SYSCLK, ...

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MB91301 Series (6) Ready Input Timings Sym- Parameter RDY setup time SYSCLK SYSCLK RDY hold time SYSCLK MCLK RDY (Wait specified by RDY) RDY (No wait specified by RDY) 108 ( Pin name ...

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Hold Timing Sym- Parameter bol BGRNT delay time t CHBGL BGRNT delay time t CHBGH Pin floating t XHAL BGRNT time BGRNT pin valid time t HAHV Note : The time from receiving BRQ to BGRNT changing is one ...

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MB91301 Series (8) SDRAM Timing Parameter Symbol Output clock cycle time “H” level clock pulse width “L” level clock pulse width MCLKO output delay t ODSDCKE time Output hold time t OHSDCKE MCLKO output delay t ODSDRAS time Output hold ...

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MCLKO MCLKO MCLKE SRAS SCAS SWE CS6 CS7 A00 to A15 DQMUU DQMUL DQMLU DQMLL D00 to D31 output D00 to D31 input t ISSDD MB91301 Series t CYCSD t t CHSD CLSD t ODSDCKE t ODSDRAS t ODSDCAS t ...

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MB91301 Series (9) UART Timing Sym- Parameter bol Serial clock cycle time t SCK SO delay time t Valid SI SCK t SCK valid SIN hold time t Serial clock “H” pulse width t Serial clock “L” pulse width t ...

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Internal shift clock mode SCK0 to SCK2 SLOV SOT0 to SOT2 SIN0 to SIN2 External shift clock mode t SLSH SCK0 to SCK2 SLOV SOT0 to SOT2 SIN0 to SIN2 MB91301 Series t SCYC ...

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MB91301 Series (10) Reload Timer Clock and PPG Timer Input Timings Sym- Parameter Input pulse width * : t is the peripheral clock cycle time. CYCP TIN0 to TIN2 PPG0 to PPG3 TRG0 to TRG3 (11) Trigger Input Timing Parameter ...

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DMA Controller Timing [ For edge detection ] (Block/step transfer mode, burst transfer mode) Sym- Parameter bol DREQ input pulse width t DREQ 0, DREQ1 DRWL Note : When becomes same as t CPT CP ...

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MB91301 Series SYSCLK V MCLK V OL DACK0, DACK1 DEOP0, DEOP1 IORD IOWR DREQ0, DREQ1 DREQ0, DREQ1 116 t CYC CLDL CLEL CLIRL CLIWL V ...

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Timing • At master mode operation Sym- Parameter Pin bol SCL clock frequency f SCL0, SCL1 SCL “L” period of SCL clock t SCL0, SCL1 LOW “H” period of SCL clock t SCL0, SCL1 HIGH BUS ...

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MB91301 Series • At slave mode operation Sym- Parameter bol SCL clock frequency f SCL0, SCL1 SCL “L” period of SCL clock t SCL0, SCL1 LOW “H” period of SCL clock t SCL0, SCL1 HIGH BUS free time between “STOP ...

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Electrical Characteristics for the A/D Converter ( Parameter Resolution Total error Linearity error Differential linearity error Zero transition error Full-scale transition error Conversion time* 1 Analog port input current Analog ...

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... Minimum sampling time ( s) • If the sampling time cannot be sufficient, connect a capacitor of about 0 the analog input pin. • About errors As |AVRH AV | becomes smaller, values of relative errors grow larger. SS 120 R C MB91302A 100 k ) (External impedance Comparator R C 8.1 k (Max) 10.0 pF (Max MB91302A Minimum sampling time ( s) ...

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Power-on ratings Parameter Symbol Power rise time tr Power start time Voff Power end voltage Von Power shutdown time toff off MB91301 Series Value Unit Min Max 38 0.1 2 off ...

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MB91301 Series PIN STATUS IN EACH CPU STATE Terms used in the pin status list • Input ready Indicates that the input function can be used. • Input 0 fixed Indicates that the input level has been internally fixed to ...

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Pin Status List (External bus : 32 bit bus width) Function Specified name Port Pin no. function name name Bus width 32 bit P13 to P17 D11 to D15 D11 to D15 P20 ...

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MB91301 Series (Continued) Function Specified Port Pin no. function name name Bus width INT4/ATG/ 85 PG4 FRCK 86 PG5 INT5/SIN2 87 PG6 INT6/SOT2 88 PG7 INT7/SCK2 90 PJ0 SIN0 91 PJ1 SOT0 92 PJ2 SCK0 93 PJ3 SIN1 94 PJ4 ...

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Pin Status List (External bus : 16 bit bus width) Function Specified name Port Pin no. function name name Bus width 16 bit P13 to P17 D11 to D15 P13 to P17 P20 ...

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MB91301 Series (Continued) Function Specified Port Pin no. function name name Bus width 81 PG0 INT0/ICU0 82 PG1 INT1/ICU1 83 PG2 INT2/ICU2 84 PG3 INT3/ICU3 INT4/ATG/ 85 PG4 FRCK 86 PG5 INT5/SIN2 87 PG6 INT6/SOT2 88 PG7 INT7/SCK2 90 PJ0 ...

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Pin Status List (External bus : 8 bit bus width) Function Specified name Port Pin no. function name name Bus width 8 bit P13 to P17 D11 to D15 P13 to P17 P20 ...

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MB91301 Series (Continued) Function Specified Port Pin no. function name name Bus width 82 PG1 INT1/ICU1 83 PG2 INT2/ICU2 84 PG3 INT3/ICU3 INT4/ATG/ 85 PG4 FRCK 86 PG5 INT5/SIN2 87 PG6 INT6/SOT2 88 PG7 INT7/SCK2 90 PJ0 SIN0 91 PJ1 ...

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Pin Status List (Single chip mode) Specified func- Pin no. Port name tion name P13 to P17 P20 to P27 P30 to P37 28 P80 29 P81 30 P82 31 P83 ...

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MB91301 Series (Continued) Specified func- Pin no. Port name tion name 96 PJ6 PPG0 97 PJ7 TRG0 98 PH0 TIN0 99 PH1 TIN1/PPG3 100 PH2 TIN2/TRG3 103 PB0 104 PB1 105 PB2 106 PB3 107 PB4 TRG1 108 PB5 PPG1 ...

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EXAMPLE CHARACTERISTICS I Internal frequency (PLL On) CC External V 3 140 120 100 Internal frequency [MHz] V External V OL ...

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... Without ROM Optional real time OS internal model 144-pin Plastic LQFP Built-in IPL (Internal Program Loader) (FPT-144P-M12) version User ROM version Development pack for MB91302A real 179-pin Ceramic PGA time OS internal model (MB91V301A (PGA-179C-A03) and CD-ROM for development) 179-pin Ceramic PGA Evaluation chip ...

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PACKAGE DIMENSIONS 144-pin Plastic LQFP (FPT-144P-M12) 18.00±0.20(.709±.008)SQ +0.40 +.016 * 16.00 .630 – 0.10 – .004 108 109 INDEX 144 LEAD No. 1 0.40(.016) 2003 FUJITSU LIMITED F144024S-c-3-3 C Note These dimensions include resin protrusion. Resin protrusion ...

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MB91301 Series (Continued) 179-pin Ceramic PGA (PGA-179C-A03) INDEX AREA (1.500±.020) 1994 FUJITSU LIMITED R179004SC-3-2 C 134 2.54±0.25 (.100±.010) 35.56(1.400) REF +0.18 0.46 DIA –0.05 +.007 .018 –.002 38.10±0.51 SQ 1.27±0.25 (.050±.010) +0.41 6.10(.240) 3.40 –0.36 MAX +.016 .134 –.014 Dimensions ...

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MB91301 Series The information for microcontroller supports is shown in the following homepage. http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ...