MC68HC705X32 Motorola, MC68HC705X32 Datasheet

no-image

MC68HC705X32

Manufacturer Part Number
MC68HC705X32
Description
Manufacturer
Motorola
Datasheet

Specifications of MC68HC705X32

Case
QFP-64L
MC68HC05X16/D
Rev. 1
HC05
MC68HC05X16
MC68HC05X32
MC68HC705X32
TECHNICAL
DATA

Related parts for MC68HC705X32

MC68HC705X32 Summary of contents

Page 1

... HC05 MC68HC05X16 MC68HC05X32 MC68HC705X32 TECHNICAL DATA MC68HC05X16/D Rev. 1 ...

Page 2

...

Page 3

... MODES OF OPERATION AND PIN DESCRIPTIONS MOTOROLA CAN MODULE (MCAN) SERIAL COMMUNICATIONS INTERFACE PULSE LENGTH D/A CONVERTERS ANALOG TO DIGITAL CONVERTER CPU CORE AND INSTRUCTION SET ELECTRICAL SPECIFICATIONS INTRODUCTION MEMORY AND REGISTERS INPUT/OUTPUT PORTS PROGRAMMABLE TIMER RESETS AND INTERRUPTS MECHANICAL DATA ORDERING INFORMATION ...

Page 4

... INTRODUCTION 2 MODES OF OPERATION AND PIN DESCRIPTIONS 3 MEMORY AND REGISTERS 4 INPUT/OUTPUT PORTS 5 MOTOROLA CAN MODULE (MCAN) 6 PROGRAMMABLE TIMER 7 SERIAL COMMUNICATIONS INTERFACE 8 PULSE LENGTH D/A CONVERTERS 9 ANALOG TO DIGITAL CONVERTER 10 RESETS AND INTERRUPTS 11 CPU CORE AND INSTRUCTION SET 12 ELECTRICAL SPECIFICATIONS 13 MECHANICAL DATA 14 ORDERING INFORMATION ...

Page 5

... The Customer should ensure that it has the most up to date version of the document by contacting its local Motorola office. This document supersedes any earlier documentation relating to the products referred to herein. The information contained in this document is current at the date of publication. It may subsequently be updated, revised or withdrawn. MOTOROLA LTD., 1997 MC68HC05X16 MC68HC05X32 MC68HC705X32 are registered ...

Page 6

Where abbreviations are used in the text, an explanation can be found in the glossary, at the back of this manual. Register and bit mnemonics are defined in the paragraphs describing them. An overbar is used to designate an active-low ...

Page 7

... CUSTOMER FEEDBACK QUESTIONNAIRE (MC68HC05X16/D) Motorola wishes to continue to improve the quality of its documentation. We would welcome your feedback on the publication you have just received. Having used the document, please complete this card (or a photocopy of it, if you prefer). 1. How would you rate the quality of the document? Check one box in each category. ...

Page 8

... We would be grateful if you would supply the following information (at your discretion), or attach your card. Name: Position: Department: Company: Address: Thank you for helping us improve our documentation, Graham Forbes, Technical Publications Manager, Motorola Ltd., Scotland . Excellent Poor 3–5 years More than 5 years – Second fold back along this line – REPONSE PAYEE GRANDE-BRETAGNE Motorola Ltd ...

Page 9

... MDS................................................................................................................. 2-12 2.3.5 TCAP1 ............................................................................................................. 2-12 2.3.6 TCAP2 ............................................................................................................. 2-12 2.3.7 TCMP1............................................................................................................. 2-12 2.3.8 TCMP2............................................................................................................. 2-12 2.3.9 RDI (Receive data in)....................................................................................... 2-12 2.3.10 TDO (Transmit data out) .................................................................................. 2-12 2.3.11 SCLK ............................................................................................................... 2-13 MC68HC05X16 Rev. 1 TITLE 1 INTRODUCTION 2 MODES OF OPERATION AND PIN DESCRIPTIONS TABLE OF CONTENTS Page Number MOTOROLA i ...

Page 10

... EEPROM during WAIT mode ................................................................................ 3-8 3.8 Miscellaneous register.......................................................................................... 3-11 4.1 Input/output programming ..................................................................................... 4-1 4.2 Ports A and B ........................................................................................................ 4-2 4.3 Port C .................................................................................................................... 4-3 4.4 Port D .................................................................................................................... 4-4 4.5 Port registers ......................................................................................................... 4-4 MOTOROLA ii TITLE 3 MEMORY AND REGISTERS 4 INPUT/OUTPUT PORTS TABLE OF CONTENTS Page Number MC68HC05X16 Rev. 1 ...

Page 11

... A/D status/control register ............................................................................... 4-5 4.5.5 Data direction registers (DDRA, DDRB and DDRC)........................................ 4-6 4.6 Other port considerations ...................................................................................... 4-6 MOTOROLA CAN MODULE (MCAN) 5.1 TBF – Transmit buffer ............................................................................................ 5-4 5.2 RBF – Receive buffer ............................................................................................ 5-4 5.3 Interface to the MC68HC05X16 CPU.................................................................... 5-4 5 ...

Page 12

... SCI during STOP mode......................................................................................... 7-21 7.14 SCI during WAIT mode.......................................................................................... 7-21 PULSE LENGTH D/A CONVERTERS 8.1 Miscellaneous register........................................................................................... 8-3 8.2 PLM clock selection............................................................................................... 8-4 8.3 PLM during STOP mode ....................................................................................... 8-4 8.4 PLM during WAIT mode ........................................................................................ 8-4 MOTOROLA iv TITLE 7 8 TABLE OF CONTENTS Page Number MC68HC05X16 Rev. 1 ...

Page 13

... CPU CORE AND INSTRUCTION SET 11.1 Registers ............................................................................................................. 11-1 11.1.1 Accumulator (A) ............................................................................................. 11-1 11.1.2 Index register (X) ........................................................................................... 11-2 11.1.3 Program counter (PC).................................................................................... 11-2 11.1.4 Stack pointer (SP).......................................................................................... 11-2 11.1.5 Condition code register (CCR)....................................................................... 11-2 11.2 Instruction set ...................................................................................................... 11-3 MC68HC05X16 Rev. 1 TITLE 9 10 RESETS AND INTERRUPTS 11 TABLE OF CONTENTS Page Number MOTOROLA v ...

Page 14

... EPROMS............................................................................................................. 14-2 14.2 Verification media ................................................................................................ 14-2 14.3 ROM verification units (RVU) .............................................................................. 14-2 MOTOROLA vi TITLE 12 13 MECHANICAL DATA 14 ORDERING INFORMATION TABLE OF CONTENTS Page ...

Page 15

... DC electrical characteristics ............................................................................B-24 B.9.3 EPROM electrical characteristics ....................................................................B-26 B.9.4 Control timing...................................................................................................B-27 B.9.5 A/D converter characteristics...........................................................................B-28 B.9.6 MCAN bus interface DC electrical characteristics ...........................................B-29 B.9.7 MCAN bus interface control timing characteristics ..........................................B-29 MC68HC05X16 Rev. 1 TITLE A MC68HC05X32 B MC68HC705X32 TABLE OF CONTENTS Page Number MOTOROLA vii ...

Page 16

... Paragraph Number C.1 DC electrical characteristics ..................................................................................C-1 C.2 Control Timing .......................................................................................................C-2 MOTOROLA viii TITLE C MC68HC05X32 HIGH SPEED OPERATION TABLE OF CONTENTS Page Number MC68HC05X16 Rev. 1 ...

Page 17

... SCI sampling technique used on all bits ................................................................ 7-7 7-6 Artificial start following a framing error ................................................................... 7-8 7-7 SCI start bit following a break................................................................................. 7-8 7-8 SCI example of synchronous and asynchronous transmission .............................. 7-9 7-9 SCI data clock timing diagram (M=0) ..................................................................... 7-12 MC68HC05X16 Rev. 1 TITLE LIST OF FIGURES Page Number MOTOROLA ix ...

Page 18

... A-2 Memory map of the MC68HC05X32 ...................................................................... A-3 A-3 Timer relationship................................................................................................... A-11 B-1 MC68HC705X32 block diagram............................................................................. B-3 B-2 Memory map of the MC68HC705X32 .................................................................... B-5 B-3 Modes of operation flow chart ................................................................................ B-15 B-4 Timing diagram with handshake............................................................................. B-18 B-5 Parallel EPROM loader timing diagram.................................................................. B-18 B-6 EPROM parallel bootstrap schematic diagram ...

Page 19

... IRQ and WOI sensitivity ....................................................................................... 10-10 11-1 MUL instruction .................................................................................................... 11-5 11-2 Register/memory instructions............................................................................... 11-5 11-3 Branch instructions............................................................................................... 11-6 11-4 Bit manipulation instructions................................................................................. 11-6 11-5 Read/modify/write instructions ............................................................................. 11-7 11-6 Control instructions............................................................................................... 11-7 MC68HC05X16 Rev. 1 TITLE /2.................................. 7-20 OSC /8.................................. 7-20 OSC /10................................ 7-20 OSC LIST OF TABLES Page Number MOTOROLA xi ...

Page 20

... EPROM electrical characteristics........................................................................... B-26 B-10 Control timing ......................................................................................................... B-27 B-11 A/D characteristics ................................................................................................. B-28 B-12 MCAN bus interface DC electrical characteristics.................................................. B-29 B-13 MCAN bus interface control timing characteristics................................................. B-29 C-1 DC electrical characteristics................................................................................... C-1 C-2 Control timing ......................................................................................................... C-2 MOTOROLA xii TITLE LIST OF TABLES Page Number MC68HC05X16 Rev. 1 ...

Page 21

... This data sheet is structured such that devices similar to the MC68HC05X16 are described in a set of appendices (see Table 1-1). Table 1-1 Data sheet appendices Device Appendix MC68HC05X32 MC68HC705X32 MC68HC05X32 Note: Appendix C contains only electrical characteristics exclusive to the high speed operation of the MC68HC05X32. For all other information concerning this device, refer to Appendix A ...

Page 22

... Three 8-bit parallel I/O ports and one 8-bit input-only port; wired-OR interrupt capability on all port B pins • Motorola controller area network (MCAN) with line interface circuitry • Software option available to output the internal E-clock to port pin PC2 • 16-bit timer with 2 input captures and 2 output compares • ...

Page 23

... Resistive pull-downs on ports B and/or C Note recommended that an external clock is always used if t will prevent any problems arising from oscillator stability when the device is put into STOP mode. MC68HC05X16 Rev 4064 cycles PORL PORL INTRODUCTION 1 is set to 16 cycles. This MOTOROLA 1-3 ...

Page 24

... TX1 RX0 RX1 NWOI MDS VDD VSS PD0/AN0 PD1/AN1 PD2/AN2 PD3/AN3 PD4/AN4 PD5/AN5 PD6/AN6 PD7/AN7 VRH VRL MOTOROLA 1-4 256 bytes EEPROM 15118 bytes user ROM Charge pump (including 16 bytes user vectors) COP watchdog Oscillator 576 bytes bootstrap ROM Line ...

Page 25

... I/O ports and the 8-bit input-only port, available to the user. All address and data activity occurs within the MCU. MC68HC05X16 MODES OF OPERATION AND PIN DESCRIPTIONS Rev TCAP1 TCAP2 PD3 PD4 Table 2-1 shows Mode Single-chip Reserved for Motorola use Bootstrap mode: Serial RAM loader Jump to RAM + 1 Jump to any address is equivalent to holding DD MOTOROLA 2-1 2 ...

Page 26

... The bootstrap software is implemented in the following locations: • RAM load and execute from $03B0 to $03FD • Vectors and program select from $7F80 to $7FEF PD4 set ? NO Reserved for Motorola use. Figure 2-1 Bootstrap mode function selection flow chart MOTOROLA MODES OF OPERATION AND PIN DESCRIPTIONS 2-2 OR MDS pin ...

Page 27

... SCI is configured for the NRZ data format (idle line, start bit, eight data bits and stop bit). The baud rate is 9600 with a 4 MHz crystal. A program to convert ASCII S-records to the format required by the RAM loader is available from Motorola. When the last byte is loaded, the firmware halts operation expecting additional data to arrive. At this point, the reset switch is placed in the reset position which resets the MCU, but keeps the RAM program intact ...

Page 28

... Note: These eight resistors are optional; direct connection is possible if pins PA0-PA7, PB0-PB7 and PC0-PC7 are kept in input mode during application. Figure 2-2 MC68HC05X16 ‘jump to any address’ schematic diagram MOTOROLA MODES OF OPERATION AND PIN DESCRIPTIONS 2 VDD OSC1 RESET ...

Page 29

... MODES OF OPERATION AND PIN DESCRIPTIONS Rev VDD OSC1 OSC2 MHz IRQ 10 k PD3 10 k PD4 10 k TCAP1 optional VRH VRL VPP1 PLMA PLMB SCLK Connect as required for the application TCMP2 TCAP2 TCMP1 PD7 PD6 PD5 PD2 PD1 PD0 VSS P1 2 GND +5V 2xV MOTOROLA 2-5 ...

Page 30

... All SCI activity stops; see – The timer stops counting; see – The PLM outputs remain at current levels; see – The A/D converter is disabled; see – The I-bit in the CCR is cleared MOTOROLA MODES OF OPERATION AND PIN DESCRIPTIONS 2-6 Section 5.5. ...

Page 31

... If a reset exit from WAIT mode is performed the entire system reverts to the disabled reset state. Note: The stacking corresponding to an eventual interrupt to leave WAIT mode will only be executed when leaving WAIT mode. MC68HC05X16 MODES OF OPERATION AND PIN DESCRIPTIONS Rev MOTOROLA 2-7 ...

Page 32

... Warning: The SLOW mode function should not be enabled while using the A/D converter or while erasing/programming the EEPROM unless the internal A/D RC oscillator is turned on. MOTOROLA MODES OF OPERATION AND PIN DESCRIPTIONS 2-8 Section 3.7 Section 7 ...

Page 33

... Oscillator active. Timer, SCI, A/D, EEPROM clocks active. Processor clocks stopped. Clear I-bit NO Reset ? YES NO WOI ? YES Timer interrupt ? YES Restart processor clock (1) Fetch reset vector or (2) Service interrupt: a. stack b. set I-bit c. vector to interrupt routine SCI ? NO YES CIRQ ? YES MOTOROLA 2-9 ...

Page 34

... The SM bit is cleared by external or power-on reset. The SM bit is automatically cleared when entering STOP mode. Note: The bits shown shaded in the above representation are explained individually in the relevant sections of this manual. The complete register plus an explanation of each bit can be found in MOTOROLA MODES OF OPERATION AND PIN DESCRIPTIONS 2-10 OSC2 pin f ...

Page 35

... When a reset condition occurs internally, i.e. from the COP watchdog, the RESET pin provides an active-low open drain output signal that may be used to reset external hardware. MC68HC05X16 MODES OF OPERATION AND PIN DESCRIPTIONS Rev. 1 3.8 only possible to change the interrupt option bits in 2 Table 10-3. MOTOROLA 2-11 ...

Page 36

... The TCMP2 pin is the output of the output compare 2 function of the timer system. 2.3.9 RDI (Receive data in) The RDI pin is the input pin of the SCI receiver. 2.3.10 TDO (Transmit data out) The TDO pin is the output pin of the SCI transmitter. MOTOROLA MODES OF OPERATION AND PIN DESCRIPTIONS 2-12 . See Section 2.1. DD ...

Page 37

... The equivalent specification of the external clock source should be used in lieu OXOV ILCH MC68HC05X16 MODES OF OPERATION AND PIN DESCRIPTIONS Rev. 1 Figure 2-6(a) is recommended when using either a crystal or a specifications (see Section 12.4) do not apply when using There is also a OP MOTOROLA 2-13 ...

Page 38

... OSC1 COSC1 (a) Crystal/ceramic resonator oscillator connections R (max – – 30 OSC1 C 15 – – 25 OSC2 Q 30 000 MOTOROLA MODES OF OPERATION AND PIN DESCRIPTIONS 2-14 OSC1 MCU OSC2 COSC2 (c) External clock source connections Crystal 2MHz 4MHz Unit 400 ƒ 000 — (d) Typical crystal and ceramic resonator parameters ...

Page 39

... The PLMB pin is the output of pulse length modulation converter B. MC68HC05X16 MODES OF OPERATION AND PIN DESCRIPTIONS Rev. 1 Section Figure 2-7. Mask option MCAN clock /2, / /10 OSC Control logic 1.2). This allows a CPU clock MCAN module 16 f /32, /64, OSC /128 or /160 Main internal clock MOTOROLA 2-15 2 ...

Page 40

... This 8-bit input only port (D) shares its pins with the A/D converter. When enabled, the A/D converter uses pins PD0/AN0 – PD7/AN7 as its analog inputs. On reset, the A/D converter is disabled which forces the port D pins to be input only port pins (see MOTOROLA MODES OF OPERATION AND PIN DESCRIPTIONS 2-16 Section 4 ...

Page 41

... During simultaneous transmission of dominant and recessive bits the resulting bus value will be dominant. For example with a positive logic wired-AND implementation of the bus, the dominant level would correspond to a logic 0 and the recessive level to a logic 1. MC68HC05X16 MODES OF OPERATION AND PIN DESCRIPTIONS Rev MOTOROLA 2-17 ...

Page 42

... THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA MODES OF OPERATION AND PIN DESCRIPTIONS 2-18 MC68HC05X16 Rev. 1 ...

Page 43

... The user ROM consists of 15118 bytes of ROM mapped as follows: • 15102 bytes of user ROM from $0300 to $3DFD • 16 bytes of user vectors from $3FF0 to $3FFF MC68HC05X16 Rev Figure 3-1. MCAN registers are contained in the next 30 Section 3.8 as this register contains bits which are relevant MEMORY AND REGISTERS 3 MOTOROLA 3-1 ...

Page 44

... Timer overflow $3FF4–5 Timer output compare 1& 2 $3FF6–7 Timer input capture 1& 2 $3FF8–9 WOI, External IRQ $3FFA–B SWI $3FFC–D Reset/power-on reset $3FFE–F MOTOROLA 3-2 Ports 7 bytes EEPROM/ECLK control 1 byte A/D converter 2 bytes PLM system 2 bytes ...

Page 45

... Data segment byte 8 $0034 Identifier $0035 $0036 Data segment byte 1 $0037 Data segment byte 2 $0038 Data segment byte 3 $0039 Data segment byte 4 $003A Data segment byte 5 $003B Data segment byte 6 $003C Data segment byte 7 $003D Data segment byte 8 MOTOROLA 3-3 3 ...

Page 46

... WOIE bit. 1 (set) – Wired-OR interrupts are enabled (provided that wired-OR interrupts have been selected as a mask option). 0 (clear) – Wired-OR interrupts are disabled. MOTOROLA 3-4 PP1 ; this will protect the EEPROM data but will also increase power DD Section 3.5.5). ...

Page 47

... E1LAT bit is at zero, resulting in a read condition. MC68HC05X16 Rev. 1 Section 5.5). The bit is cleared when the MCAN wakes up. programming time, the E1LAT bit has to be reset PROG1 Table 3-1, since the E1PGM and E1ERA bits are MEMORY AND REGISTERS 3 Table 3-1. MOTOROLA 3-5 ...

Page 48

... While an erase operation is being performed, any access of the EEPROM array will not be successful. The erased state of the EEPROM is $FF and the programmed state is $00. Note: Data written to the address to be erased is not used, therefore its value is not significant. MOTOROLA 3-6 Table 3-1 EEPROM control bits description E1LAT E1PGM Description ...

Page 49

... Address (1) Options (OPTR) $0100 (1) This register is implemented in EEPROM; therefore reset has no effect on the individual bits. MC68HC05X16 Rev. 1 bit 7 bit 6 bit 5 bit 4 bit 3 MEMORY AND REGISTERS Section 3.5.5. State bit 2 bit 1 bit 0 on reset EE1P SEC Not affected MOTOROLA 3-7 3 ...

Page 50

... Under normal operating conditions, the charge pump generator is driven by the internal CPU clocks. When the operating frequency is low, e.g. during slow mode (see WAIT mode, the clocking should be done by the internal A/D RC oscillator. The RC oscillator is enabled by setting the ADRC bit of the A/D status/control register at $0009. MOTOROLA 3-8 programming time in WAIT mode. PROG1 ...

Page 51

... RWU SBK 0000 0000 NF FE 1100 000u 0000 0000 Undefined Undefined Undefined Undefined Undefined 1111 1111 1111 1100 1111 1111 1111 1100 Undefined Undefined Undefined Undefined EE1P SEC Not affected MOTOROLA 3-9 3 ...

Page 52

... Receive data segment 5 (RDS5) Receive data segment 6 (RDS6) Receive data segment 7 (RDS7) Receive data segment 8 (RDS8) (1) These registers can only be accessed when the reset request bit in the control register is set. MOTOROLA 3-10 Table 3-3 MCAN register outline Address bit 7 bit 6 bit 5 ...

Page 53

... IRQ sensitivity WOI interrupt options Positive edge and high level sensitive Positive edge only Negative edge only Positive and negative edge sensitive Section 10.2) Section 8.1) MEMORY AND REGISTERS State bit 2 bit 1 bit 0 on reset (2) SFB SM WDOG u001 000u 10.2) MOTOROLA 3-11 3 ...

Page 54

... Following a watchdog reset the state of the WDOG bit is as defined by the mask option specified. 1 (set) – Watchdog counter cleared and enabled. 0 (clear) – The watchdog cannot be disabled by software; writing a zero to this bit has no effect. MOTOROLA 3-12 Section Section 2.2.3) /32). SLOW mode affects all sections of the device, including Section 10 ...

Page 55

... MCU. During the programmed output state, a read of the data register actually reads the value of the output data latch and not the I/O pin. The operation of the standard port hardware is shown schematically in MC68HC05X16 Rev Figure INPUT/OUTPUT PORTS 4 4-1. MOTOROLA 4-1 ...

Page 56

... Writing a ‘1’ to any DDR bit sets the corresponding port pin to output mode. Wired-OR interrupts are provided on all pins of port B. If WOIE is enabled, any combination of high logic levels on port B pins which are programmed as inputs will trigger an external interrupt. See Section 10.2.3.2. MOTOROLA 4-2 DDRn DATA Output buffer ...

Page 57

... Internal clock (PHI2) External clock (ECLK/PC2) Output port (if write to output port) Figure 4-2 ECLK timing diagram MC68HC05X16 Rev. 1 bit 7 bit 6 bit 5 bit 4 bit ECLK E1ERA E1LAT E1PGM 0000 0000 Figure 4-2. INPUT/OUTPUT PORTS 4 State bit 2 bit 1 bit 0 on reset MOTOROLA 4-3 ...

Page 58

... Port A data (PORTA) Port B data (PORTB) Each bit can be configured as input or output via the corresponding data direction bit in the port data direction register (DDRx). The state of the port data registers following reset is not defined. MOTOROLA 4 the port D pins will result in greater DD ...

Page 59

... COCO ADRC ADON 0 CH3 INPUT/OUTPUT PORTS State bit 2 bit 1 bit 0 on reset PC2/ Undefined ECLK State bit 2 bit 1 bit 0 on reset PD2 PD1 PD0 Undefined State bit 2 bit 1 bit 0 on reset CH2 CH1 CH0 0000 0000 MOTOROLA 4-5 4 ...

Page 60

... This would cause the ‘open-drain’ pin not to output a ‘zero’ when desired. Note: ‘Open-drain’ outputs should not be pulled above V MOTOROLA 4-6 Address bit 7 bit 6 ...

Page 61

... V DD VDD Px0 MC68HC05X16 Rev Normal operation – tri state 0 tri state 1 tri state 0 low 1 — ‘Open-drain’ 0 high 1 high ‘Open-drain’ output (c) DDRx, bit Portx, bit Figure 4-3 Port logic levels INPUT/OUTPUT PORTS Y 4 DDRx, bit Portx, bit MOTOROLA 4-7 ...

Page 62

... THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA 4-8 INPUT/OUTPUT PORTS MC68HC05X16 Rev. 1 ...

Page 63

... MOTOROLA CAN MODULE (MCAN) The MCAN includes all hardware modules necessary to implement the CAN transfer layer, which represents the kernel of the CAN bus protocol as defined by BOSCH GmbH, the originators of the CAN specification. For full details of the CAN protocol please refer to the published specifications. ...

Page 64

Arbitration field Control field Identifier Data length Acceptance code filtering Stored in buffers Stored in transmit/receive buffers Remote frame 12 6 Arbitration field Control field ...

Page 65

Error frame Data frame Echo or Error flag Error delimiter error flag remote frame Inter-frame space 3 8 Suspend INT ...

Page 66

... CPU merely places a message to be transmitted into the transmit buffer and sets the TR bit. The MCAN will begin transmitting the message when it has determined that the bus is idle. In the event of a transmission error, the MCAN will initiate a repeated transmission automatically. MOTOROLA 5-4 MOTOROLA CAN MODULE (MCAN) MC68HC05X16 Rev. 1 ...

Page 67

... MCAN transmit buffer 10 bytes $0033 $0034 MCAN receive buffer 10 bytes $003D Figure 5-3 MCAN module memory map MC68HC05X16 MOTOROLA CAN MODULE (MCAN) Rev. 1 Figure 5-3). MCAN registers Control register Command register Status register Interrupt register Acceptance code register Acceptance mask register ...

Page 68

... Disabled – The CPU will get no transmit interrupt request. MOTOROLA 5-6 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 OIE EIE TIE MOTOROLA CAN MODULE (MCAN) Reset State bit 1 bit 0 condition on reset External reset uuu1 RIE RR RR bit set uuu1 MC68HC05X16 ...

Page 69

... This is a write only register; a read of this location will always return the value $FF. This register may be written only when the RR bit in CCNTRL is clear. Do not use read-modify-write instructions on this register (e.g. BSET, BCLR). Address bit 7 MCAN command (CCOM) $0020 RX0 MC68HC05X16 MOTOROLA CAN MODULE (MCAN) Rev. 1 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 ...

Page 70

... A node that was sleeping and has been awakened by bus activity will not be able to receive any messages until its oscillator has started and it has found a valid end of MOTOROLA 5-8 Figure 5-6) Figure 5-6) 5-6). MOTOROLA CAN MODULE (MCAN) MC68HC05X16 Rev. 1 ...

Page 71

... No action. This will not cancel a previously requested transmission; the abort transmission command must be used to do this. MC68HC05X16 MOTOROLA CAN MODULE (MCAN) Rev. 1 5.3.3). It may be written at the same time as RRB. Section 5.3.3) becomes set. ...

Page 72

... Idle – If the transmit status bit is also clear then the MCAN is idle; otherwise transmit mode. MOTOROLA 5-10 bit 7 bit 6 bit 5 bit 4 bit 3 bit TCS TBA MOTOROLA CAN MODULE (MCAN) State bit 1 bit 0 Reset condition on reset External reset 0000 1100 DO RBS RR bit set uu00 1100 MC68HC05X16 Rev. 1 ...

Page 73

... CPU and RBS is immediately set again. The first receive buffer is then available for the next incoming message from the MCAN. 1 (set) – Full – A new message is available for the CPU to read. 0 (clear) – Empty – No new message is available. MC68HC05X16 MOTOROLA CAN MODULE (MCAN) Rev MOTOROLA 5-11 ...

Page 74

... Transmission complete, the transmit buffer is accessible. 0 (clear) – No transmit interrupt has occurred. MOTOROLA 5-12 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 WIF OIF EIF MOTOROLA CAN MODULE (MCAN) State bit 1 bit 0 Reset condition on reset External reset - - - 0 0000 TIF RIF RR bit set - - - u 0u00 MC68HC05X16 Rev. 1 ...

Page 75

... If there is no free buffer, the data overrun condition will be signalled. On acceptance the receive buffer status bit is set to full and the receive interrupt bit is set (provided RIE = enabled). MC68HC05X16 MOTOROLA CAN MODULE (MCAN) Rev. 1 bit 7 bit 6 bit 5 ...

Page 76

... AM7 AM6 AM5 AM4 Address bit 7 bit 6 bit 5 bit 4 $0026 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 Undefined MOTOROLA CAN MODULE (MCAN) State bit 3 bit 2 bit 1 bit 0 on reset AM3 AM2 AM1 AM0 Undefined State bit 3 bit 2 ...

Page 77

... BRP4 BRP3 osc Divide by OSC1 2 Divide by 10 Figure 5-4 Oscillator block diagram MC68HC05X16 MOTOROLA CAN MODULE (MCAN) Rev. 1 SJW0 Synchronization jump width cycle SCL cycles SCL cycles SCL cycles SCL ), which is used to build up the SCL Table 5-2 and the formula in Figure ...

Page 78

... SAMP TSEG22TSEG21TSEG20TSEG13TSEG12TSEG11TSEG10 Undefined BIT_TIME TSEG 1 1 clock cycle Sample point t SCL Figure 5-5 Segments within the bit time MOTOROLA CAN MODULE (MCAN) State bit 3 bit 2 bit 1 bit 0 on reset TSEG 2 SYNC_SEG Transmit point Table 5-3. MC68HC05X16 ...

Page 79

... SCL i.e. in terms SCL SYNC_SEG = 1 TSEG1 TSEG1 TSEG2 TSEG2 and TSEG2 or TSEG2 These boundary conditions result in minimum bit times three samples per bit. MC68HC05X16 MOTOROLA CAN MODULE (MCAN) Rev. 1 Time segment 1 TSEG22 TSEG21 TSEG20 2 t cycles 0 0 SCL 3 t cycles . . SCL 4 t cycles ...

Page 80

... Bit stream transmitted on both TX0 and TX1 Normal mode 2 1 TX0 - bit sequence TX1 - bus clock (t ) xclk ) is used to indicate the end of the bit time and will be high during xclk MOTOROLA CAN MODULE (MCAN) State bit 3 bit 2 bit 1 bit 0 on reset OCM1 OCM0 Undefined OCPOL0 Table 5-4 ...

Page 81

... Table 5-5 MCAN driver output levels Mode TD OCPOLi Float Pull-down Pull- Push-pull MC68HC05X16 MOTOROLA CAN MODULE (MCAN) Rev. 1 Figure 5-6). OCTPi OCTNi TPi TNi 0 0 Off Off 0 0 Off Off 0 0 Off Off 0 0 Off Off 0 1 Off Off Off 0 1 Off Off 0 1 Off On 1 ...

Page 82

... ID10 ID9 ID8 ID7 Address bit 7 bit 6 bit 5 bit 4 $002B ID2 ID1 ID0 RTR Table 5-6 MOTOROLA CAN MODULE (MCAN) State bit 3 bit 2 bit 1 bit 0 on reset ID6 ID5 ID4 ID3 Undefined State bit 3 bit 2 bit 1 bit 0 on reset ...

Page 83

... Address Receive buffer identifier (RBI) $0034 (Note that there are actually two receive buffer register sets, but switching between them is handled internally by the MCAN.) MC68HC05X16 MOTOROLA CAN MODULE (MCAN) Rev. 1 Table 5-6 Data length codes Data length code DLC2 DLC1 ...

Page 84

... A simple termination network is required for each CANH CANL Figure 5-6 the voltages on the MCAN bus are 3. 1.75 V CANH CANL 4.00 V CANH CANL MOTOROLA CAN MODULE (MCAN) Section 5.3.11). State bit 3 bit 2 bit 1 bit 0 on reset DLC3 DLC2 DLC1 DLC0 Undefined Section 5.3.12). State bit 3 ...

Page 85

... TX0 680 TX1 680 150k RX0 150k RX1 2 x 30k CANL CANH VDDH MCAN bus lines Figure 5-6 A typical physical interface between the MCAN and the MCAN bus lines MC68HC05X16 MOTOROLA CAN MODULE (MCAN) Rev – – & – – Internal to the MC68HC05X16 MCAN module ...

Page 86

... STOP instruction being executed and the oscillator stopping. During this time it is possible that the MCAN will come out of sleep mode, and hence prevent the oscillator from stopping. MOTOROLA 5-24 = 5.0 V, the common mode range will be DD 3.5.1). MOTOROLA CAN MODULE (MCAN) /2. This increases the common mode DD /2 reference supply. At the same DD /2. DD MC68HC05X16 Rev ...

Page 87

... However, when the COMPSEL bit is set each input is compared with V /2 (VDDH – see DD details of the active comparator, the sleep comparator and VDDH, refer to MC68HC05X16 MOTOROLA CAN MODULE (MCAN) Rev setting one of the control DD Figure 5-6) to detect a dominant level. For further ...

Page 88

... THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA 5-26 MOTOROLA CAN MODULE (MCAN) MC68HC05X16 Rev. 1 ...

Page 89

... MHz. The counter is incremented during the low portion of the internal bus clock. Software can read the counter at any time without affecting its value. MC68HC05X16 Rev Figure 6-2, Figure 6-3, PROGRAMMABLE TIMER Figure 6-4 and Figure 6-5. MOTOROLA 6-1 6 ...

Page 90

... Output compare compare circuit 1 circuit ICF1 OCF1 TOF ICF2 Interrupt circuit Input capture interrupt vector $3FF8,9 Figure 6-1 16-bit programmable timer block diagram MOTOROLA 6-2 Internal bus Internal 8-bit processor buffer clock Low High Low byte byte byte byte 4 16-bit Output ...

Page 91

... The PLM results will also be affected while resetting the counter. MC68HC05X16 Rev. 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 7 bit 6 bit 5 bit 4 bit 3 PROGRAMMABLE TIMER State bit 2 bit 1 bit 0 on reset 1111 1111 1111 1100 State bit 2 bit 1 bit 0 on reset 1111 1111 1111 1100 6 Section 10.1.4). MOTOROLA 6-3 ...

Page 92

... Interrupt disabled. TOIE — Timer overflow interrupt enable If this bit is set, a timer interrupt is enabled whenever the TOF status flag (in the timer status register) is set. 1 (set) – Interrupt enabled. 0 (clear) – Interrupt disabled. MOTOROLA 6-4 Address bit 7 bit 6 bit 5 bit 4 $0012 ICIE ...

Page 93

... TCMP1 pin. When clear, it will be a low level which will appear on the TCMP1 pin. 1 (set) – A high output level will appear on the TCMP1 pin. 0 (clear) – A low output level will appear on the TCMP1 pin. MC68HC05X16 Rev. 1 Section Section PROGRAMMABLE TIMER 6.4.3). 6.4.3). 6 MOTOROLA 6-5 ...

Page 94

... The timer status register is read or written when TOF is set, and 2 The LSB of the free-running counter is read, but not for the purpose of servicing the flag. Reading the alternate counter register instead of the counter register will avoid this potential problem. MOTOROLA 6-6 Address bit 7 bit 6 ...

Page 95

... MC68HC05X16 Rev. 1 bit 7 bit 6 bit 5 bit 4 bit 3 PROGRAMMABLE TIMER 6 State bit 2 bit 1 bit 0 on reset Undefined Undefined MOTOROLA 6-7 ...

Page 96

... Reset does not affect the contents of the input capture 2 register, except when exiting STOP mode (see Section 6.6). MOTOROLA 6-8 Address bit 7 bit 6 bit 5 bit 4 ...

Page 97

... Read the timer status register to clear OCF1 (if set); – Write to output compare low 1 to enable the output compare 1 function. MC68HC05X16 Rev. 1 bit 7 bit 6 bit 5 bit 4 bit 3 PROGRAMMABLE TIMER 6 State bit 2 bit 1 bit 0 on reset Undefined Undefined MOTOROLA 6-9 ...

Page 98

... The following procedure is recommended: – Write to output compare high 2 to inhibit further compares; – Read the timer status register to clear OCF2 (if set); – Write to output compare low 2 to enable the output compare 2 function. MOTOROLA 6-10 Address bit 7 bit 6 ...

Page 99

... Pulse length modulation A (PLMA) $000A Address Pulse length modulation B (PLMB) $000B MC68HC05X16 Rev. 1 Section 8). bit 7 bit 6 bit 5 bit 4 bit 3 bit 7 bit 6 bit 5 bit 4 bit 3 PROGRAMMABLE TIMER 6 State bit 2 bit 1 bit 0 on reset 0000 0000 State bit 2 bit 1 bit 0 on reset 0000 0000 MOTOROLA 6-11 ...

Page 100

... The relationships between the internal clock signals, the counter contents and the status of the flag bits are shown in the following figures. It should be noted that the signals labelled ‘internal’ (processor clock, timer clocks and reset) are not available to the user. MOTOROLA 6-12 PROGRAMMABLE TIMER MC68HC05X16 Rev ...

Page 101

... If the input edge occurs in the shaded area from one timer state T10 to the next timer state T10, then the input capture flag will be set during the next T11 state. Figure 6-3 Timer state timing diagram for input capture MC68HC05X16 Rev. 1 $FFFC $FFFD $FFFE $F123 $F124 $F125 $???? $F124 PROGRAMMABLE TIMER $FFFF 6 $F126 MOTOROLA 6-13 ...

Page 102

... The timer overflow flag is set at timer state T11 (transition of counter from $FFFF to $0000 cleared by a read of the timer status register during the internal processor clock high time, followed by a read of the counter low register. Figure 6-5 Timer state timing diagram for timer overflow MOTOROLA 6-14 T00 T01 ...

Page 103

... Software selectable word length (eight or nine bits) • Separate transmitter and receiver enable bits • Capable of being interrupt driven • Transmitter clocks available without altering the regular transmitter or receiver functions • Four separate enable bits for interrupt control MC68HC05X16 SERIAL COMMUNICATIONS INTERFACE Rev MOTOROLA 7-1 ...

Page 104

... Note: The serial communications data register (SCI SCDR) is controlled by the internal R/W signal the transmit data register when written to and the receive data register when read. Figure 7-1 Serial communications interface block diagram MOTOROLA 7-2 Internal bus SCI interrupt + & ...

Page 105

... TC bit will also be set. This will also generate an interrupt if the transmission complete interrupt enable bit (TCIE) is set. If the transmitter is disabled during a transmission, the character being transmitted will be completed before the transmitter gives up control of the TDO pin. MC68HC05X16 SERIAL COMMUNICATIONS INTERFACE Rev. 1 Figure 7-1. Option bits in serial control register1 (SCCR1) 7 MOTOROLA 7-3 ...

Page 106

... There is a fixed rate divide-by-16 before the transmitter to compensate for the inherent divide-by-16 of the receiver (sampling). This means that by loading the same value for both the transmitter and receiver baud rate selector, the same baud rates can be obtained. MOTOROLA 7-4 Internal processor clock SCP0 – ...

Page 107

... Normally RWU is set by software and is cleared automatically in hardware by one of the two methods described below. MC68HC05X16 SERIAL COMMUNICATIONS INTERFACE Rev. 1 Figure 7-3 is used and must meet the following Control bit M selects bit data Start Figure 7-3 Data format 8 0 Stop Start MOTOROLA 7-5 7 ...

Page 108

... If there has been a framing error without detection of a break (10 zeros for 8 bit format or 11 zeros for 9 bit format), the circuit continues to operate as if there actually was a stop bit, and the start MOTOROLA 7-6 and as the receiver clock in ...

Page 109

... Start Start Start edge qualifiers verification samples Start Noise Start Samples 8RT 9RT 10RT 16RT 1RT Figure 7-4) are forced into the sample shift 6RT 7RT 8RT Next bit Figure 7-6); therefore, MOTOROLA 7-7 ...

Page 110

... Data format is as discussed in generates a bit time by using a derivative of the RT clock, thus producing a transmission rate equal to 1/16th that of the receiver sample clock (assuming the same baud rate is selected for both the receiver and transmitter). MOTOROLA 7-8 Figure Expected stop Artifi ...

Page 111

... MC68HC05X16 Output port Figure 7-8 SCI example of synchronous and asynchronous transmission MC68HC05X16 SERIAL COMMUNICATIONS INTERFACE Rev. 1 Figure 7-8, Figure 7-9 and Figure Data out Data in Data in Clock Enable 7-10). Asynchronous (e.g. Modem) Synchronous (e.g. shift register, display driver, etc.) MOTOROLA 7-9 7 ...

Page 112

... Serial communications control register 1 (SCCR1) SCI control 1 (SCCR1) The SCI control register 1 (SCCR1) contains control bits related to the nine data bit character format, the receiver wake-up feature and the options to output the transmitter clocks for synchronous transmissions. MOTOROLA 7-10 Address bit 7 bit 6 ...

Page 113

... Wake-up on address mark; if RWU is set, SCI will wake-up if the 8th (if M=0) or the 9th (if M=1) bit received on the Rx line is set. 0 (clear) – Wake-up on idle line; if RWU is set, SCI will wake-up after 11 (if M= (if M=1) consecutive ‘1’s on the Rx line. MC68HC05X16 SERIAL COMMUNICATIONS INTERFACE Rev. 1 Method of receiver wake-up 7 MOTOROLA 7-11 ...

Page 114

... This bit should not be manipulated while the transmitter is enabled. 7 Idle or preceding transmission clock (CPOL = 0, CPHA = 0) clock (CPOL = 0, CPHA = 1) clock (CPOL = 1, CPHA = 0) clock (CPOL = 1, CPHA = 1) data MOTOROLA 7- data bits) Start Start LSB * LBCL bit controls last data clock Figure 7-9 SCI data clock timing diagram (M=0) ...

Page 115

... This bit should not be manipulated while the transmitter is enabled. Table 7-2 SCI clock on SCLK pin Data format 8 bit 8 bit 9 bit 9 bit MC68HC05X16 SERIAL COMMUNICATIONS INTERFACE Rev data bits MSB * LBCL bit controls last data clock Number of clocks on M-bit LBCL bit SCLK pin Idle or next transmission Stop * * * * 8 Stop 7 MOTOROLA 7-13 ...

Page 116

... After this latest transmission, and provided the TDRE bit is set (no new data to transmit), the line remains idle (driven high while TE = 1); otherwise, normal transmission occurs. This function allows the user to neatly terminate a transmission sequence. MOTOROLA 7-14 Address bit 7 ...

Page 117

... If SBK remains set, the transmitter will continually send whole blocks of zeros (sets 11) until cleared. At the completion of the break code, the transmitter sends at least one high bit to guarantee recognition of a valid start bit. MC68HC05X16 SERIAL COMMUNICATIONS INTERFACE Rev MOTOROLA 7-15 ...

Page 118

... IDLE set) followed by a read of the serial communications data register. Once cleared, IDLE will not be set again until after RDRF has been set, (i.e. until after the line has been active and becomes idle again). MOTOROLA 7-16 Address ...

Page 119

... The FE bit is cleared when the serial communications status register is accessed (with FE set) followed by a read of the serial communications data register. MC68HC05X16 SERIAL COMMUNICATIONS INTERFACE Rev. 1 Section 7.7. 7 MOTOROLA 7-17 ...

Page 120

... SCI receiver, and by the SCT0–SCT2 bits for the transmitter. 7 SCT2, SCT1, SCT0 — SCI rate select bits (transmitter) These three read/write bits select the baud rates for the transmitter. The prescaler output is divided by the factors shown in MOTOROLA 7-18 Address bit 7 bit 6 ...

Page 121

... NT = transmitter baud rate divide ratio NR = receiver baud rate divide ratio baudTx = transmitter baud rate baudRx = receiver baud rate f = CPU clock frequency CLK MC68HC05X16 SERIAL COMMUNICATIONS INTERFACE Rev. 1 Table 7-5. Receiver SCR1 SCR0 division ratio (NR 128 f clk baudTx = ----------------------------------- clk baudRx = ----------------------------------- MOTOROLA 7-19 ...

Page 122

... Table 7-8 SCI baud rate selection with CPU clock frequency = f SCP1 Note: The clock in the ‘Clock divided by’ column refers to the internal processor clock. MOTOROLA 7-20 Table 7-6, Table 7-7 and Table 7-8 Table 7-9 shows how lower transmitter or receiver baud rates may be are representative samples only ...

Page 123

... Table 7-6, Table 7-7, Table 7-8 and Section 2.2.3). 19200 9600 19200 9600 9600 4800 4800 2400 2400 1200 1200 600 600 300 300 150 150 75 Table 7-9 do not apply when MOTOROLA 7-21 7 ...

Page 124

... THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA 7-22 SERIAL COMMUNICATIONS INTERFACE MC68HC05X16 Rev. 1 ...

Page 125

... PLMA PLMB register register ‘A’ register ‘B’ register buffer buffer ‘A’ ‘B’ comparator comparator 8 8 ‘A’ ‘B’ multiplexer multiplexer 16 16 Timer bus 8-1.) R PLMB D/A Latch pin S Zero detector SFB bit From timer MOTOROLA 8-1 8 ...

Page 126

... PLM during the period immediately following an update of the PLM D/A 8 registers). This feature is achieved by double buffering of the PLM D/A registers. Examples of PWM output waveforms are shown in $00 $01 T $80 $ CPU clocks in fast mode and 64 CPU clocks in slow mode MOTOROLA 8-2 Address bit 7 bit 6 bit 5 bit 4 $000A $000B Figure 8-2 ...

Page 127

... The complete register plus an explanation of each bit can be found in MC68HC05X16 PULSE LENGTH D/A CONVERTERS Rev. 1 bit 7 bit 6 bit 5 bit 4 bit 3 POR INTP INTN INTE SFA /2). OSC Section 3.8. State bit 2 bit 1 bit 0 on reset SFB SM WDOG u001 000u MOTOROLA 8-3 8 ...

Page 128

... PLM systems resume regular operation. If STOP mode is exited by 8 power-on or external reset the registers values are forced to $00. 8.4 PLM during WAIT mode The PLM system is not affected by WAIT mode and continues normal operation. MOTOROLA 8-4 Figure Bus SM bit = 0 frequency (f ...

Page 129

... VRL. Selection is done via the CHx bits in the ADSTAT register (see are the only input points for A/D conversion operations; the others are reference points that can be used for test purposes. MC68HC05X16 ANALOG TO DIGITAL CONVERTER Rev Section Figure Section RL 9 9.2.3). 9-1). 9.2.3). AN0–AN7 MOTOROLA 9-1 ...

Page 130

... Warning: Any write to the A/D status/control register will abort the current conversion, reset the conversion complete flag and start a new conversion on the selected channel. At power-on or external reset, both the ADRC and ADON bits are cleared; thus the A/D is disabled. MOTOROLA 9-2 8-bit capacitive DAC ...

Page 131

... Rev. 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 PD7 PD6 PD5 PD4 PD3 PD2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 State bit 1 bit 0 on reset PD1 PD0 Undefined the pins will DD SS State 9 bit 1 bit 0 on reset 0000 0000 MOTOROLA 9-3 ...

Page 132

... When the A/D RC oscillator is turned on, it takes a time t 9 this time A/D conversion results may be inaccurate. Note: If the MCU bus clock falls below 1MHz, the A/D RC oscillator should be switched on. Power-on or external reset clears the ADRC bit. ADRC MOTOROLA 9-4 Address bit 7 bit 6 bit 5 bit 4 $0009 COCO ADRC ADON 0 ADRC ...

Page 133

... ADON CH2 CH1 CH0 Channel selected AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 VRH pin (high (VRH + VRL VRL pin (low VRL pin (low VRL pin (low VRL pin (low VRL pin (low VRL pin (low) 9 MOTOROLA 9-5 ...

Page 134

... It should be noted that these are typical values measured at room temperature. Analog 9 input pin Note: MOTOROLA 9-6 Figure 9-2. Sampling time is limited to 12 bus clock cycles. After sampling, Input protection device + ~20V - ~0.7V < 2pF The analog switch is closed during the 12 cycle sample time only ...

Page 135

... Figure 10-1 Reset timing diagram MC68HC05X16 Rev CYC t ( DOGL New 3FFE 3FFF PC New New Op PCH PCL code Program execution begins RESETS AND INTERRUPTS (External hardware reset) ) New 3DFE 3FFE 3FFF PC Reset sequence New New Op Mask options PCH PCL code Program execution begins MOTOROLA 10-1 10 ...

Page 136

... A power-on reset has occurred. 0 (clear) – No power-on reset has occurred. Note: The bits shown shaded in the above representation are explained individually in the relevant sections of this manual. The complete register plus an explanation of each bit can be found in MOTOROLA 10-2 Section 10.1.2). Address bit 7 bit 6 bit 5 ...

Page 137

... The input to the watchdog system is derived from the carry output of bit 7 of the free running timer counter. Therefore, a reset of the timer may affect the period of the watchdog timeout. MC68HC05X16 Rev. 1 CYC VDD pin MC68HC05X16 RESET pin RESETS AND INTERRUPTS ). An internal Schmitt Trigger 10 Figure 10-3. The divide-by-7 MOTOROLA 10-3 ...

Page 138

... The watchdog counter, therefore, has to be cleared periodically, by software, with a period less than t DOG The reset generated by the watchdog system is apparent at the RESET pin (see RESET pin level is re-entered in the control logic, and when it has been maintained at level ‘zero’ for a minimum of t DOGL MOTOROLA 10 256 7 watchdog (Bit 7 of free ...

Page 139

... Note: Reset action on individual MCAN registers is described in summarised in Table 3-2. MC68HC05X16 Rev. 1 cycles start-up delay. On start-up, the watchdog will be PORL RESETS AND INTERRUPTS Section 1.2) to Section 5 and is also 10 MOTOROLA 10-5 ...

Page 140

... SCI status bits TDRE and TC set Oscillator disabled for 4064 cycles Timer clock cleared SCI clock cleared A/D disabled SM bit in the miscellaneous register cleared Watchdog counter reset 10 WDOG bit in the miscellaneous register reset EEPROM control bits set or cleared (as per Section MOTOROLA 10-6 Function/effect RESET – x – ...

Page 141

... Note: Power-on and external reset clear all interrupt enable bits to prevent interrupts during the reset sequence, but set the INTE bit (see MC68HC05X16 Rev. 1 Section 3.8). RESETS AND INTERRUPTS 10 MOTOROLA 10-7 ...

Page 142

... Is I-bit set? IRQ or WOI external interrupt? internal interrupt? internal interrupt? MCAN interrupt? 10 Fetch next instruction Execute instruction MOTOROLA 10-8 Reset NO YES Clear IRQ request latch NO Timer YES NO YES SCI NO YES CIRQ NO Figure 10-4 Interrupt flow chart RESETS AND INTERRUPTS Stack PC Set I-bit ...

Page 143

... TSR ICF1, ICF2 $3FF8, $3FF9 TSR OCF1, OCF2 $3FF6, $3FF7 TSR TOF $3FF4, $3FF5 TDRE, TC, SCSR OR, RDRF, $3FF2, $3FF3 IDLE WIF,OIF,EIF, CINT $3FF0, $3FF1 TIF, RIF RESETS AND INTERRUPTS Figure 10-4 shows the highest lowest 10 MOTOROLA 10-9 ...

Page 144

... I-bit is set. Any attempt to change the external interrupt option while the I-bit is clear will be unsuccessful external interrupt is pending, it will automatically be cleared when selecting a different interrupt option. MOTOROLA 10-10 Address bit 7 bit 6 ...

Page 145

... MCAN control register at $0020. The CIRQ sources are (also see Receive IRQ: this signals successful reception of a complete message. Transmit IRQ: this signals successful transmission of a complete message. MC68HC05X16 Rev. 1 Section 5.3.4): RESETS AND INTERRUPTS Section 1.2). If wired-OR Section 2.3.19 and 10 MOTOROLA 10-11 ...

Page 146

... SCSR (address $0010). The general sequence for clearing an interrupt is a software sequence of accessing the serial communications status register while the flag is set followed by a read or write of an associated register. Refer to Section 7 MOTOROLA 10-12 Section 5.3.3). and Section 6.2.2 for further information ...

Page 147

... The WAIT instruction causes all processor clocks to stop, but leaves the timer clocks running. This ‘rest’ state of the processor can be cleared by reset, an external or WOI interrupt, a timer interrupt or an SCI interrupt. There are no special WAIT vectors for these individual interrupts. MC68HC05X16 Rev. 1 RESETS AND INTERRUPTS Figure 2-4. 10 MOTOROLA 10-13 ...

Page 148

... THIS PAGE LEFT BLANK INTENTIONALLY 10 MOTOROLA 10-14 RESETS AND INTERRUPTS MC68HC05X16 Rev. 1 ...

Page 149

... The accumulator is a general purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations. MC68HC05X16 CPU CORE AND INSTRUCTION SET Rev Accumulator 7 0 Index register 7 0 Program counter 7 0 Stack pointer Condition code register Carry / borrow Zero Negative Interrupt mask Half carry 11 MOTOROLA 11-1 ...

Page 150

... The CCR is a 5-bit register in which four bits are used to indicate the results of the instruction just executed, and the fifth bit indicates whether interrupts are masked. These bits can be individually tested by a program, and specific actions can be taken as a result of their state. Each bit is explained in the following paragraphs. MOTOROLA 11-2 7 Condition code register ...

Page 151

... This instruction allows unsigned multiplication of the contents of the accumulator (A) and the index register (X). The high-order product is then stored in the index register and the low-order product is stored in the accumulator. A detailed definition of the MUL instruction is shown in Table 11-1. MC68HC05X16 CPU CORE AND INSTRUCTION SET Rev MOTOROLA 11-3 ...

Page 152

... Refer to 11.2.6 Tables Tables for all the instruction types listed above follow. In addition there is a complete alphabetical listing of all the instructions (see M68HC05 MCU family (see MOTOROLA 11-4 11-4. Table 11-6 for a complete list of control instructions. Table 11-7), and an opcode map for the instruction set of the Table 11-8) ...

Page 153

... H : Cleared I : Not affected N : Not affected Z : Not affected C : Cleared MUL Addressing mode Cycles Bytes Inherent 11 1 Addressing modes Indexed Direct Extended Opcode $42 Indexed Indexed (no (8-bit (16-bit offset) offset) offset MOTOROLA 11-5 11 ...

Page 154

... Branch if interrupt mask bit is set Branch if interrupt line is low Branch if interrupt line is high Branch to subroutine Function Branch if bit n is set Branch if bit n is clear 11 Set bit n Clear bit n MOTOROLA 11-6 Table 11-3 Branch instructions Function Mnemonic BRA BRN BHI BLS BCC ...

Page 155

... Inherent addressing mode Mnemonic Opcode # Bytes # Cycles TAX 97 1 TXA 9F 1 SEC 99 1 CLC 98 1 SEI 9B 1 CLI 9A 1 SWI 83 1 RTS 81 1 RTI 80 1 RSP 9C 1 NOP 9D 1 STOP 8E 1 WAIT 8F 1 Indexed Indexed (no (8-bit offset) offset MOTOROLA 11-7 ...

Page 156

... BSET 11 BSR CLC CLI CLR CMP Address mode abbreviations BS Bit set/clear C BTB Bit test & branch DIR Direct EXT Extended MOTOROLA 11-8 Table 11-7 Instruction set Addressing modes IMM DIR EXT REL IX IX1 H Half carry (from bit 3) IMM Immediate I Interrupt mask ...

Page 157

... Tested and set if true, cleared otherwise • Not affected ? Load CCR from stack 0 Cleared 1 Set MOTOROLA 11-9 ...

Page 158

... MOTOROLA 11-10 Table 11-8 M68HC05 opcode map CPU CORE AND INSTRUCTION SET MC68HC05X16 Rev. 1 ...

Page 159

... In the direct addressing mode, the effective address of the argument is contained in a single byte following the opcode byte. Direct addressing allows the user to directly address the lowest 256 bytes in memory with a single two-byte instruction. Address bus high MC68HC05X16 CPU CORE AND INSTRUCTION SET Rev PC+ (PC+1); PC PC+2 0; Address bus low (PC+1) 11 MOTOROLA 11-11 ...

Page 160

... This address mode can be used in a manner similar to indexed, 8-bit offset except that this three-byte instruction allows tables to be anywhere in memory. As with direct and extended addressing, the Motorola assembler determines the shortest form of indexed addressing. ...

Page 161

... Otherwise, control proceeds to the next instruction. The span of relative addressing is from –126 to +129 from the opcode address. The programmer need not calculate the offset when using the Motorola assembler, since it calculates the proper offset and checks to see that it is within the span of the branch. ...

Page 162

... THIS PAGE LEFT BLANK INTENTIONALLY 11 MOTOROLA 11-14 CPU CORE AND INSTRUCTION SET MC68HC05X16 Rev. 1 ...

Page 163

... For maximum reliability all unused inputs should be tied to either V MC68HC05X16 ELECTRICAL SPECIFICATIONS Rev Symbol Value V – 0 – 0 – 0 –40 to +125 T – +150 STG OSC . Unit MHz 12 MOTOROLA 12-1 ...

Page 164

... WAIT (SM = 0): CAN active WAIT (SM =1): CAN active WAIT (SM = 0): CAN asleep WAIT (SM = 1): CAN asleep STOP: CAN active STOP: CAN asleep High-Z leakage current PA0–7, PB0–7, PC0–7, TDO, RESET, SCLK MOTOROLA 12-2 Table 12-2 DC electrical characteristics = 0 Vdc – +125 (1) ...

Page 165

... OUT C — — — — INJ |I | — INJ = 0.2 V and – 0.2 V: STOP 2.2 MHz CAN = 11 MHz + I DD DD1 (2) Typ Max Unit — — A — +10 0 — — — — pF — — Figure 2-6(c); all inputs 0.2 V measured with DD ) MOTOROLA 12-3 12 ...

Page 166

... Source impedances greater than 10k will adversely affect internal charging time during input sampling. (3) The external system error caused by input leakage current is approximately equal to the product of R source and input current. Input current to A/D channel will be dependent on external source impedance (see 12 MOTOROLA 12-4 Table 12-3 A/D characteristics = 0 Vdc – ...

Page 167

... TLTL TH Max Unit 22 MHz 11 MHz 2.2 MHz — ns 100 ms 100 ms 500 s — t CYC — t CYC — t CYC — t CYC 7168 t CYC — t CYC — ns — t CYC — ns — t CYC — ns cycles 10 years ), this is the limiting t TL MOTOROLA 12-5 12 ...

Page 168

... A < I (1) Maximum DC current should comply with maximum ratings. 12.6 MCAN bus interface control timing characteristics Table 12-6 MCAN bus interface control timing characteristics (4. MCAN bus output driver Rise and fall time (C 12 MOTOROLA 12 Vdc – +125 Characteristic Symbol V IN ...

Page 169

... PD6/AN6 14 PD5/AN5 Device MC68HC05X16, MC68HC05X32 MC68HC705X32 Note: Unless otherwise stated, a pin labelled as ‘NU’ should be tied to V environment. Pins labelled ‘NC’ can be left floating, since they are not bonded to any part of the device. Figure 13-1 64-pin QFP pinout MC68HC05X16 Rev. 1 ...

Page 170

... E 2.00 2.40 F 0.30 — G 0.80 BSC H 0.067 0.250 J 0.130 0.230 K 0.50 0. 12.00 REF MOTOROLA 13 Detail “A” Detail “C” M Datum -H- Plane M Notes 1. Datum Plane –H– is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 2. Datums A– ...

Page 171

... Package Type MC68HC05X16 64-pin QFP MC68HC05X32 64-pin QFP MC68HC705X32 64-pin QFP Note: The high speed version of the MC68HC05X32 has the same device title as the standard version. High speed operation is selected via a check box on the order form and will be confirmed on the listing verification form. See MC68HC05X16 Rev ...

Page 172

... ROM code will be generated and returned with a listing verification form. The listing should be thoroughly checked and the verification form completed, signed and returned to Motorola. The signed verification form constitutes the contractual agreement for creation of the custom mask. If desired, Motorola will program blank EPROMs (supplied by the customer) from the data fi ...

Page 173

... ROM plus 16 bytes of user vectors • 528 bytes of RAM • 654 bytes of bootstrap ROM • Available in 64-pin QFP package • High speed operation (4 MHz bus speed) available. See characteristics. • – +125 C temperature range MC68HC05X16 Rev Appendix C for tables of electrical MC68HC05X32 15 MOTOROLA A-1 ...

Page 174

... RX0 RX1 NWOI MDS VDD VSS PD0/AN0 PD1/AN1 PD2/AN2 PD3/AN3 PD4/AN4 PD5/AN5 PD6/AN6 PD7/AN7 VRH VRL 15 MOTOROLA A-2 Section A.3.1 to Section A.3.4 256 bytes EEPROM 31248 bytes user ROM Charge pump (including 16 bytes user vectors) COP watchdog Oscillator 654 bytes bootstrap ...

Page 175

... A/D converter 2 bytes $000A PLM system 2 bytes $000C Miscellaneous 1 byte $000D SCI 5 bytes $0012 Timer 14 bytes $0020 MCAN control registers 10 bytes $002A MCAN transmit buffer 10 bytes $0034 MCAN receive buffer 10 bytes $003E $0047 $0100 Options register 15 MOTOROLA A-3 ...

Page 176

... MCAN receive buffer 10 bytes $003E $0047 Options register $0100 Figure A-2 Memory map of the MC68HC05X32 (Continued) 15 MOTOROLA A-4 Registe Port A data register Port B data register Port C data register Port D input data register Port A data direction register Port B data direction register Port C data direction register ...

Page 177

... OLV2 IEDG1 OLVL1 0000 00u0 Undefined Undefined Undefined Undefined Undefined 1111 1111 1111 1100 1111 1111 1111 1100 Undefined Undefined Undefined Undefined EE1P SEC Not affected MOTOROLA A-5 15 ...

Page 178

... However recommended that normal precautions be taken to avoid the application of any voltages higher than those given in the maximum ratings table to this high impedance circuit. For maximum reliability all unused inputs should be tied to either V 15 MOTOROLA A-6 Table A-2 Maximum ratings Rating Symbol ...

Page 179

... DD 0.1 0.4 V 0.2 0.6 0.2 0.4 — — 0. 360 900 A 360 900 A 32 100 3 1.6 3 1.5 3.7 mA 0.8 1.4 mA 0.4 1.1 mA 0.5 1 300 4.6 8 1.2 1.8 mA 0.8 1.4 mA 0.5 1 300 A 0 MOTOROLA A-7 15 ...

Page 180

... The maximum specified current for each port is the sum of the magnitudes of the currents on each side of the individual port pins. Some disturbance of the A/D accuracy is possible during an injection event and is dependent on board layout, power supply decoupling and reference voltage decoupling configurations. 15 MOTOROLA A-8 Table A-3 DC electrical characteristics = 0 Vdc – +125 C) ...

Page 181

... Rev. 1 Table A-4 A/D characteristics Parameter = 0V) RL and (2) MC68HC05X32 Min Max Unit 8 — Bit — 0.5 LSB — 0.5 LSB — 1 LSB 0 – 0 — V — CYC — GUARANTEED 00 — Hex — FF Hex — CYC — — — Figure 9-2). MOTOROLA A-9 15 ...

Page 182

... The minimum period t the capture interrupt service routine plus 24 t (4) The minimum period t the interrupt service routine plus temperature (6) Refer to Reliability Monitor Report (currrent quarterly issue) for current failure rate information. 15 MOTOROLA A-10 Table A-5 Control timing = 0 Vdc – +125 ...

Page 183

... OUT I –100 OUT (1) I –100 –1.0V) I –10 OUT 1.0V OUT OL (1) I –100 Vdc – +125 C) A Symbol Min 2 for DD DV –180 OUT MC68HC05X32 t TL Max Unit V +0 –1 +100 mA + +200 mV +100 mA +100 mA — mA — mA +100 mA Max Unit +180 mV MOTOROLA A-11 15 ...

Page 184

... A.3.6 MCAN bus interface control timing characteristics Table 1-7 MCAN bus interface control timing characteristics (4. MCAN bus output driver Rise and fall time (C 15 MOTOROLA A-12 5.5V Vdc – +125 Characteristic Symbol = 100pF) T LOAD RF MC68HC05X32 Min Max Unit — MC68HC05X16 Rev. 1 ...

Page 185

... B-10) is 1.5 t – Maximum bus speed 2.2 MHz The MC68HC705X32 is a device similar to the MC68HC05X16, but with 32K bytes of EPROM instead of 16K bytes of ROM. In addition, the bootstrap routines available in the MC68HC05X16 are replaced by bootstrap routines specific to the MC68HC705X32. The entire MC68HC05X16 data sheet applies to the MC68HC705X32, with the exceptions outlined in this appendix ...

Page 186

... Note: Although this pin can be left floating to disconnect the MCAN module advisable to connect it to VSS when the module is not in use. 15 MOTOROLA B-2 Section B.9.2 and Section B.9.5 MC68HC705X32 contain data specific to this device. MC68HC05X16 Rev. 1 ...

Page 187

... MDS VDD VSS PD0/AN0 PD1/AN1 PD2/AN2 PD3/AN3 8-bit PD4/AN4 A/D converter PD5/AN5 PD6/AN6 PD7/AN7 VRH VRL Figure B-1 MC68HC705X32 block diagram MC68HC05X16 Rev. 1 31248 bytes EPROM (including 16 bytes user vectors) 32 654 bytes bootstrap ROM MCAN 528 bytes RAM M68HC05 CPU 16-bit ...

Page 188

... WOI DIV2 DIV8 RTIM MC68HC705X32 State on bit 3 bit 2 bit 1 bit 0 Undefined Undefined PC2/ECLK Undefined PD3 PD2 PD1 PD0 Undefined 0000 0000 0000 0000 0000 0000 ...

Page 189

... Timer output compare 1& 2 $7FF8–9 Timer input capture 1& 2 $7FFA–B WOI, External IRQ $7FFC–D SWI $7FFE–F Reset/power-on reset Figure B-2 Memory map of the MC68HC705X32 MC68HC05X16 Rev. 1 EPROM User Vectors MC68HC705X32 Register groups $0000 Ports 7 bytes ...

Page 190

... MCAN receive buffer 10 bytes $003E $0047 $0100 Options register $7FDE Mask options register Figure B-2 Memory map of the MC68HC705X32 (Continued) 15 MOTOROLA B-6 Registers Port A data register Port B data register Port C data register Port D input data register Port A data direction register ...

Page 191

... B.5 EPROM The MC68HC705X32 memory map is given in of EPROM. 16 bytes are used for the reset and interrupt vectors from address $7FF0 to $7FFF. The main EPROM block of 31232 bytes is located from $0400 to $7DFF. One byte of EPROM is used as an option register and is located at address $7FDE. ...

Page 192

... WOIE CAF E6LAT E6PGM ECLK E1ERA E1LAT E1PGM 0000 0000 Section Section 5.5). The bit is cleared when the MCAN wakes up. MC68HC705X32 switching must PP6 State bit 3 bit 2 bit 1 bit 0 on reset B.7). If WOI is not set then MC68HC05X16 ...

Page 193

... A programming operation will take place. Once the program/erase EEPROM address has been selected, E1ERA cannot be changed. MC68HC05X16 Rev. 1 programming time, the E6LAT bit has to be reset PROG1 Description 0 Read/execute in EPROM 0 Ready to write address/data to EPROM 1 programming in progress MC68HC705X32 15 MOTOROLA B-9 ...

Page 194

... E1LAT bit has to be reset PROG1 Table B-3 EEPROM1 control bits description E1LAT E1PGM Description 0 0 Read condition 1 0 Ready to load address/data for program/erase 1 1 Byte programming in progress 1 0 Ready for byte erase (load address Byte erase in progress MC68HC705X32 MC68HC05X16 Rev. 1 ...

Page 195

... EPROM erase verification mode with PD1 set. When the SEC bit is changed, its new value will have no effect until the next power-on or external reset. 1 (set) – EEPROM/EPROM not protected. 0 (clear) – EEPROM/EPROM protected. MC68HC05X16 Rev. 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 MC68HC705X32 State bit 1 bit 0 on reset EE1P SEC Not affected 15 MOTOROLA B-11 ...

Page 196

... DIV2 DIV8 Clock divide ratio where the RESET pin is kept low after a power-on reset. PORL = 16 cycles. PORL = 4064 cycles. PORL MC68HC705X32 bit 4 bit 3 bit 2 bit 1 bit 0 RTIM RWAT WWAT PBPD PCPD Not affected Table B-4). Note that MC68HC05X16 State on reset Rev. 1 ...

Page 197

... PD 1 (set) – Pull-down resistors are connected to all 8 pins of port C; the pull-down (clear) – No pull-down resistors are connected. MC68HC05X16 Rev active only while the pin is an input active only while the pin is an input. PD MC68HC705X32 15 MOTOROLA B-13 ...

Page 198

... The hold time on the IRQ, MDS, TCAP1 and TCAP2 pins is two clock cycles after the external RESET pin is brought high. When the MC68HC705X32 is placed in the bootstrap mode, the bootstrap reset vector will be fetched and the bootstrap firmware will start to execute. to enter each level of bootstrap mode on the rising edge of RESET . ...

Page 199

... Figure B-3 Modes of operation flow chart MC68HC05X16 Rev. 1 Parallel E/EEPROM bootstrap Erased EPROM verification Y Y SEC bit active? Red LED PD4 set Jump to RAM PD2 set? N Reserved for Motorola use Y SEC bit active? Red LED PD4 set MC68HC705X32 Serial RAM load/execute ($0051) 15 MOTOROLA B-15 ...

Page 200

... Figure B-3 Modes of operation flow chart (Continued) 15 MOTOROLA B- PD2 set? Base address = $400 Base address = $100 (EPROM only) (EPROM and EEPROM) A PD2 set Base address = $100 (EPROM and EEPROM) N Data verified? Y Green LED on MC68HC705X32 Y Base address = $400 (EPROM only) Red LED on MC68HC05X16 Rev. 1 ...

Related keywords