CY7C0241-35AC Cypress Semiconductor Corporation., CY7C0241-35AC Datasheet
CY7C0241-35AC
Specifications of CY7C0241-35AC
Related parts for CY7C0241-35AC
CY7C0241-35AC Summary of contents
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... Features • True Dual-Ported memory cells which allow simulta- neous reads of the same memory location • organization (CY7C024) • organization (CY7C0241) • organization (CY7C025) • organization (CY7C0251) • 0.65-micron CMOS for optimum speed/power • High-speed access • Low operating power 150 mA (typ.) CC • ...
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... Notes: 1. BUSY is an output in master mode and an input in slave mode. 2. I/O –I/O on the CY7C0241/0251 I/O –I/O on the CY7C0241/0251 the CY7C025/0251. 12L the CY7C025/0251. 12R Document #: 38-06035 Rev. *C I/O I/O CONTROL CONTROL MEMORY ADDRESS ADDRESS ARRAY DECODER DECODER INTERRUPT CE CE ...
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... I/O 13L 7 I/O 14L 8 GND 9 I/O 10 15L I/O 11 16L GND I/O 23 17R Document #: 38-06035 Rev. *C 100-Pin TQFP Top View CY7C024 100-Pin TQFP Top View CY7C0241/0251 CY7C024/0241 CY7C025/0251 INT 65 L BUSY 64 L GND 63 M/S 62 BUSY 61 R INT ...
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Pin Definitions Left Port Right Port R/W R –A A –A 0L 11/12L 0R 11/12R I/O –I/O I/O –I/O 0L 15/17L 0R 15/17R SEM SEM ...
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Busy The CY7C024/0241 and CY7C025/0251 provide on-chip arbitration to resolve simultaneous memory location access (contention). If both ports’ CEs are asserted and an address match occurs within t of each other, the busy logic will PS determine which port has ...
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Table 2. Interrupt Operation Example (Assumes BUSY Function Set Right INT Flag R Reset Right INT Flag R Set Left INT Flag L Reset Left INT Flag L Table 3. Semaphore Operation Example I/O 0 Function No action Left port ...
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Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential ............... –0.3V to +7.0V ...
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Electrical Characteristics Over the Operating Range (continued) Parameter Description I Operating Current CC I Standby Current SB1 (Both Ports TTL Levels) I Standby Current SB2 (One Port TTL Level) I Standby Current SB3 (Both Ports CMOS Levels) I Standby Current ...
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Switching Characteristics Over the Operating Range Parameter Description Read Cycle t Read Cycle Time RC t Address to Data Valid AA t Output Hold From Address OHA Change [14 LOW to Data Valid ACE t OE LOW to ...
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Switching Characteristics Over the Operating Range (continued) Parameter Description [19] Busy Timing t BUSY LOW from Address BLA Match t BUSY HIGH from Address BHA Mismatch t BUSY LOW from CE LOW BLC t BUSY HIGH from CE HIGH BHC ...
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Switching Waveforms Read Cycle No. 1 (Either Port Address Access) ADDRESS OHA DATA OUT PREVIOUS DATA VALID Read Cycle No. 2 (Either Port CE/OE Access) CE and DATA OUT CURRENT ...
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Switching Waveforms (continued) Write Cycle No. 1: R/W Controlled Timing ADDRESS OE [31,32 R/W NOTE 34 DATA OUT DATA IN Write Cycle No Controlled Timing ADDRESS [31,32 R/W DATA IN Notes: 27. ...
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Switching Waveforms (continued) Semaphore Read After Write Timing, Either Side A –A VALID ADRESS SEM I R/W OE Timing Diagram of Semaphore Contention A – R/W L SEM L A –A ...
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Switching Waveforms (continued) Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Write Timing with Busy Input (M/S=LOW) R/W BUSY Note: 40 LOW. ...
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Switching Waveforms (continued) Busy Timing Diagram No.1 (CE Arbitration) CE Valid First: L ADDRESS L BUSY R CE Valid First: R ADDRESS L BUSY L Busy Timing Diagram No.2 (Address Arbitration) Left ...
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Switching Waveforms (continued) Interrupt Timing Diagrams Left Side Sets INT : R ADDRESS WRITE FFF (1FFF CY7C025 R/W L INT R [43] t INS Right Side Clears INT : R ADDRESS R ...
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Ordering Information 4K x16 Dual-Port SRAM) ( Speed (ns) Ordering Code 15 CY7C024–15AC CY7C024-15AXC CY7C024–15JC CY7C024-15JXC 25 CY7C024–25AC CY7C024-25AXC CY7C024–25JC CY7C024-25JXC CY7C024–25AI CY7C024-25AXI CY7C024–25JI CY7C024-25JXI 35 CY7C024–35AC CY7C024-35AXC CY7C024–35JC CY7C024-35JXC CY7C024–35AI CY7C024-35AXI CY7C024–35JI CY7C024-35JXI 55 CY7C024–55AC CY7C024-55AXC CY7C024–55JC CY7C024-55JXC CY7C024–55AI ...
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... CY7C0241–15AC CY7C0241-15AXC CY7C0241–15AI CY7C0241-15AXI 25 CY7C0241–25AC CY7C0241-25AXC CY7C0241–25AI CY7C0241-25AXI 35 CY7C0241–35AC CY7C0241-35AXC CY7C0241–35AI CY7C0241-35AXI 55 CY7C0241–55AC CY7C0241-55AXC CY7C0241–55AI CY7C0241-55AXI Document #: 38-06035 Rev. *C (continued) Package Name Package Type A100 100-Pin Thin Quad Flat Pack A100 100-Pin Lead Free Thin Quad Flat Pack ...
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Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C0251–15AC CY7C0251–15AXC 25 CY7C0251–25AC CY7C0251-25AXC CY7C0251–25AI CY7C0251–25AXI 35 CY7C0251–35AC CY7C0251–35AXC CY7C0251–35AI CY7C0251–35AXI 55 CY7C0251–55AC CY7C0251–55AXC CY7C0251–55AI CY7C0251–55AXI Document #: 38-06035 Rev. *C Package Name Package Type A100 100-Pin Thin Quad ...
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Package Diagrams 100-Pin Lead (Pb)-Free Thin Plastic Quad Flat Pack (TQFP) A100 84-Lead Lead Free Plastic Leaded Chip Carrier J83 All product and company names mentioned in this document are trademarks of their respective holders. Document #: 38-06035 Rev. *C ...
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Document History Page Document Title: CY7C024/0241, CY7C025/0251 4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int, Busy Document Number: 38-06035 REV. ECN NO. Issue Date Change ** 110177 09/29/01 *A 122286 12/27/02 *B 236754 See ECN ...