AD974 Analog Devices, AD974 Datasheet
AD974
Specifications of AD974
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AD974 Summary of contents
Page 1
... ADC and a +2.5 V reference on a single chip. 2. The part operates from a single +5 V supply and also has a power-down feature. 3. Interfacing to the AD974 is simple with a low number of interconnect signals. 4. The AD974 is comprehensively specified for ac parameters such as SNR and THD, as well as dc parameters such as linearity and offset and gain errors ...
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... AD974–SPECIFICATIONS Parameter RESOLUTION ANALOG INPUT Voltage Range Impedance Sampling Capacitance THROUGHPUT SPEED Complete Cycle (Acquire and Convert) Throughput Rate DC ACCURACY Integral Linearity Error Differential Linearity Error No Missing Codes 2 Transition Noise 3 Full-Scale Error Full-Scale Error Drift Full-Scale Error Full-Scale Error Drift ...
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... Serial 16 Bits Straight Binary +0.4 +0 +5.25 +4.75 +5 +5.25 +5.25 +4.75 +5 +5.25 4.5 14 120 120 50 +85 –40 +85 Typ Max 100 4 3.8 4.0 5 220 220 1.7 AD974 Units Units ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD974 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... DATA The serial data output is synchronized to DATACLK. Conversion results are stored in an on- chip register. The AD974 provides the conversion result, MSB first, from its internal shift regis- ter. When using the internal data clock (EXT/INT = Logic LOW), DATA is valid on both the rising and falling edges of DATACLK ...
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... R/C input to when the input signal is held for a conversion. TRANSIENT RESPONSE The time required for the AD974 to achieve its rated accuracy after a full-scale step function is applied to its input. OVERVOLTAGE RECOVERY The time required for the ADC to recover to full accuracy after an analog input signal 150% of full-scale is reduced to 50% of the full-scale value ...
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... AD974 will again resume tracking the input signal. Under certain conditions the CS pin can be tied Low and R/C will be used to determine whether you are initiating a conver- sion or reading data. On the first conversion, after the AD974 is powered up, the DATA output will be indeterminate. Conversion results can be clocked serially, using either an internal clock generated by the AD974 or an external clock ...
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... The external clock can be either a continuous or discontinuous clock. A discontinu- ous clock can be either normally low or normally high when inactive. In the case of the discontinuous clock, the AD974 can be configured to either generate or not generate a SYNC output (with a continuous clock a SYNC output will always be produced). ...
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... BIT 15 BIT 14 (MSB BIT 15 BIT 14 (MSB) –9– AD974 BIT 0 (LSB BIT 0 (LSB) ...
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... AD974 EXTERNAL DISCONTINUOUS CLOCK DATA READ DURING CONVERSION WITH SYNC OUTPUT GENERATED Figure 7 illustrates the method by which data from conversion “n-1” can be read during conversion “n” while using a discon- tinuous external clock, with the generation of a SYNC output. What permits the generation of a SYNC output is a transition of DATACLK while either CS is High or while both CS and R/C are low ...
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... With a continuous clock the CS pin cannot be tied low as it could be with a discontinuous clock. Use of a continuous clock, while a conversion is occurring, can increase the DNL and Transition Noise of the AD974. After a conversion is complete, indicated by BUSY returning high, the result of that conversion can be read while CS is low ...
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... AD974 EXTERNAL CONTINUOUS CLOCK DATA READ DURING CONVERSION WITH SYNC OUTPUT GENERATED Figure 9 illustrates the method by which data from conversion “n-1” can be read during conversion “n” while using a continu- ous external clock with the generation of a SYNC output. What ...
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... The analog input section has overvoltage protection on VxA and VxB. Since the AD974 has two analog grounds it is important to ensure that the analog input is referenced to the AGND1 pin, the low current ground. This will minimize any problems associated with a resistive ground drop ...
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... AD974 INPUT RANGE BASIC CONNECTIONS FOR AD974 BIP VxA V VxB IN AGND1 10V CAP + 2.2 F AD974 REF + 2.2 F AGND2 BIP V VxA IN VxB AGND1 0V TO +5V CAP + 2.2 F AD974 REF + 2.2 F AGND2 BIP V VxA IN VxB AGND1 0V TO +4V CAP + 2.2 F AD974 REF + 2.2 F AGND2 Figure 11. Analog Input Configurations –14– REV. A ...
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... There are no internal provisions to allow for any further adjustment of offset error through external circuitry. The reference of the AD974 can be adjusted as shown in Figure 12. This will allow the full-scale error of any one channel to be adjusted to zero or will allow the average full-scale error of the four channels to be minimized ...
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... The mismatch in capacitor values is adjusted (using the calibra- tion coefficients) during a conversion, resulting in excellent dc linearity performance. Figures 17 and 18, respectively, show typical INL and DNL plots for the AD974 at + histogram test is a statistical method for deriving an A/D converter’s differential nonlinearity. A ramp input is sampled by the ADC and a large number of conversions are taken at each voltage level, averaged and then stored ...
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... ADC, a range of output codes may occur for a given input voltage. Thus, when a dc signal is applied to the AD974 input, and 10,000 conversions are recorded, the result will be a distribution of codes as shown in Figure 21. This histogram shows a bell shaped curve consistent with the Gaussian nature of thermal noise ...
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... Force RFS0 low through PF0. The Receive Frame Sync signal has been programmed active high. • Enable AD974 by forcing through PF1. • Enable SPORT0 Receive Interrupt through the IMASK register. • Wait for at least one full conversion cycle of the AD974 and throw away the received data. • ...
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... V pins of the AD974 and the system supply to the remaining digital circuitry. With this configuration, AGND1, AGND2 and DGND should be connected back at the ADC. When there is significant bus activity on the digital output pins, the digital and analog supply pins on the ADC should be separated ...
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... AD974 PIN 1 0.210 (5.33) MAX SEATING PLANE 28 1 0.0118 (0.30) 0.0040 (0.10) 0.078 (1.98) 0.068 (1.73) 0.008 (0.203) 0.002 (0.050) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead 300 Mil Plastic DIP (N-28B) 1.425 (38.195) 1.385 (35.179 0.280 (7.11) 0.240 (6.10 0.015 (0.381) MIN 0.150 (3.81) 0.115 (2.92) 0.022 (0.558) ...