ADSP-21MOD980N-000 Analog Devices, ADSP-21MOD980N-000 Datasheet
ADSP-21MOD980N-000
Specifications of ADSP-21MOD980N-000
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ADSP-21MOD980N-000 Summary of contents
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... Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. INTEGRATION FEATURES ADSP-2100 Family Code-Compatible, with Instruction Set Extensions 16 Mbits of On-Chip SRAM, Configured as 9 Mbits of Program Memory and 7 Mbits of Data Memory Dual-Purpose Program Memory, for Both Instruction ...
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... DEVELOPMENT SYSTEM Analog Devices' wide range of software and hardware devel- opment tools supports the ADSP-218x N Series. The DSP tools include an integrated development environment (IDE), an evaluation kit, and a serial port emulator. VisualDSP® integrated development environment, allowing for fast and easy development, debug and deploy- ment ...
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... ADSP-2188N data sheet. For additional information on the architecture and instruction set of the modem processors, refer to the ADSP-2100 Family User’s Manual (3rd edition). For more information about the development tools, refer to the ADSP-2100 Family Development Tools Data Sheet. ...
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... RAM • Two serial ports • An IDMA host. The signals of each modem processor are accessed through the external pins of the ADSP-21mod980N. Some signals are bussed with the signals of the other processors and are 4 2188N 2188N 2188N 2188N DSP 3 ...
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... The following is a brief list of ADSP-21mod980N SPORT features. For additional information on the internal Serial Ports, refer to the ADSP-2100 Family User’s Manual. Each SPORT: • is bidirectional and has a separate, double-buffered transmit and receive section. • ...
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... EZ-Port 16 1 Interrupt/Flag Pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, then the ADSP-21mod980N will vector to the appropriate interrupt vector address when the pin is asserted, either by external devices, or set as a programmable flag. 2 SPORT configuration determined by the ADSP-21mod980N System Control Register. Software configurable. ...
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... The CLKOUT pin may also be disabled to reduce external power dissipation. POWER DOWN The ADSP-21mod980N modem pool has a low power fea- ture that lets the modem pool enter a very low power dormant state through software control. Here is a brief list 7. When the ...
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... The one-cycle response time of the standard idle state is increased by n, the clock divisor. When an enabled interrupt is received, the ADSP-21mod980N will remain in the idle state for maximum of n modem pool cycles (n = 16, 32, 64, or 128) before resuming normal operation. ...
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... The CLKIN input cannot be halted, changed during oper- ation, or operated below the specified frequency during normal operation. The only exception is while the processor is in the power down state. For additional information, refer to Chapter 9, ADSP-2100 Family User’s Manual for a detailed explanation of this power down feature. ADSP-21mod980N T1/E1 ...
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... Control Register. RESET The RESET signals initiate a reset of each modem proces- sor in the ADSP-21mod980N. The RESET signals must be asserted during the power-up sequence to assure proper ini- tialization. RESET during initial power-up must be held long enough to let the internal clocks stabilize. If RESETs are activated any time after power up, the clocks continue to run and do not require stabilization time ...
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... MEMORY MAPPED REGISTERS (NEW TO THE ADSP-21MOD980N) The ADSP-21mod980N has three memory mapped regis- ters that differ from other ADSP-21xx Family DSPs. See “Waitstate Control Register” on page 11. See 0x0000 - 0x1F F F “Programmable Flag & Composite Select Control Regis- ter” ...
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... BMWAIT Figure 7. Programmable Flag 1 Since they are multiplexed within the ADSP-21mod980N, PF[2:0] should be configured as an output for only one processor at a time. Bit [ (0x3FE6) must also ensure that PF[3] is never an output ...
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... DMA operation. Asserting the IDMA port select (IS) and address latch enable (IAL) directs the ADSP-21mod980N to write the address onto the IAD [14:0] bus into the IDMA Control Register. If IAD [15] is set to 0, IDMA latches the address. ...
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... PRELIMINARY TECHNICAL DATA ADSP-21mod980N For current information contact Analog Devices at (800) ANALOGD 0x0000 - 0x20 0x2000 - 0x2000 - ...
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... IDMA PORT BOOTING The ADSP-21mod980N boots programs through its Inter- nal DMA port.When Mode Mode and Mode the ADSP-21mod980N boots from the IDMA port. IDMA feature can load as much on-chip memory as desired. Program execution is held off until on-chip pro- gram memory location 0 is written to ...
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... Figure 11. Selecting a Modem Processor in the ADSP-21mod980N Issuing the “chip reset” command during emulation causes the modem processor to perform a full chip reset, including a reset of its memory mode. Therefore vital that the 16 The EZ-ICE can emulate only one modem processor at a time ...
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... PRELIMINARY TECHNICAL DATA For current information contact Analog Devices at (800) ANALOGD ADSP-21mod980N, it may be necessary to reset the target hardware separately to insure the proper mode selection state on emulator chip reset. See the ADSP-2100 Family EZ-Tools data sheet for complete information on ICE products. The ICE-Port interface consists of the following ...
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... PRELIMINARY TECHNICAL DATA ADSP-21mod980N For current information contact Analog Devices at (800) ANALOGD ELECTRICAL SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Parameter Description V External supply DDEXT V Internal supply DDINT V Input Voltage INPUT T Ambient temperature AMB ELECTRICAL CHARACTERISTICS Parameter Hi-Level Input Voltage Hi-Level CLKIN Voltage ...
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... Input only pins: CLKIN, RESET, BR, DR0, DR1. 4 Output pins: BG, A0, DT0, DT1, CLKOUT, IACK. 5 Although specified for TTL outputs, all ADSP-21mod980N outputs are CMOS-compatible and will drive to V loads. 6 Guaranteed but not tested. 7 Three-statable pins: DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RSF1, IAD[15:0]. ...
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... PRELIMINARY TECHNICAL DATA ADSP-21mod980N For current information contact Analog Devices at (800) ANALOGD ABSOLUTE MAXIMUM RATINGS Parameter Description V Internal Supply Voltage DDINT V External Supply Voltage DDEXT 1 Input Voltage Output Voltage Swing Storage Temperature Range 1 Applies to bidirectional pins (D0:D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1:A13, PF0:PF7) and input only pins (CLKIN, RESET, BR, DR0, DR1) ...
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... Total Power Dissipation = internal power dissipation from INT calculated for each output the DDEXT example in Table 7. 2 × C (pF) × V (V) DDEXT 3.3 ADSP-21mod980N = 3.3 V and ns. DDEXT INT DDEXT Figure 15 × f (MHz) PD (mW) 18.8 104.8 18.8 117.9 222.7 21 ...
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... PRELIMINARY TECHNICAL DATA ADSP-21mod980N For current information contact Analog Devices at (800) ANALOGD ...
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... 2.0V 1. ING ADSP-21mod980N ) is the difference of t DIS MEASURED Figure 16. The time is the interval from , is dependent on the capacitive load, DECAY , on the output pin. It can – ...
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... CKH CK ns Output Drive Currents Figure 14 shows typical I-V characteristics for the output drivers on the ADSP-21mod980N. The curves represent the current drive capability of the output drivers as a func- tion of output voltage Capacitive Loading Figure 16 and Figure 17 show the capacitive loading char- acteristics of the ADSP-21mod980N ...
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... not needed by the application, CLKOUT should be disabled to reduce noise (DM(0x3FF3) bit 14). 3 Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal oscillator start-up time). REV. PrB 6/2001 2 : ADSP-21mod980N Min. Max Unit 25.0 40.0 ns ...
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... PRELIMINARY TECHNICAL DATA ADSP-21mod980N For current information contact Analog Devices at (800) ANALOGD * Figure 19 ...
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... IFS IFH recognized on the following cycle. (Refer to Interrupt Controller Operation in the Program Control chapter of the ADSP-2100 Family User’s Manual for further information on interrupt servicing.) 2 Edge-sensitive interrupts require pulse widths greater than 10 ns; level-sensitive interrupts must be held low until serviced. ...
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... PRELIMINARY TECHNICAL DATA ADSP-21mod980N For current information contact Analog Devices at (800) ANALOGD Serial Ports Table 11. Serial Ports Parameter Description Timing Requirements: t SCLK Period SCK t DR/TFS/RFS Setup before SCLK Low SCS t DR/TFS/RFS Hold after SCLK Low SCH t SCLKIN Width SCP Switching Characteristics: ...
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... Figure 21. Serial Ports ADSP-21mod980N ...
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... Address Latch Start after Address Latch End IALD 1 Start of Address Latch = IS Low and IAL High. 2 End of Address Latch = IS High or IAL Low. 3 For IDMA, please refer to the ADSP-2100 Family User’s Manual. 4 Start of Write or Read = IS Low and IWR Low or IRD Low ...
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... Start of Write to IACK High IKHW 1 Start of Write = IS Low and IWR Low. 2 For IDMA, please refer to the ADSP-2100 Family User’s Manual. 3 End of Write = IS High or IWR High Write Pulse ends before IACK Low, use specifications Write Pulse ends after IACK Low, use specifications t ...
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... If Write Pulse ends before IACK Low, use specifications Write Pulse ends after IACK Low, use specifications t 4 This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User’s Manual ...
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... IAD[15:0] Previous Data Hold after Start of Read (PM2) IRDH 1 Start of Read = IS Low and IRD Low. 2 For IDMA, please refer to the ADSP-2100 Family User’s Manual. 3 End of Read = IS High or IRD High read or first half of PM read. 5 Second half of PM read. ...
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... IAD[15:0] Previous Data Hold after Start of Read (PM2) IRDH 1 Timing applies to ADSP-21mod980N when Short Read Only mode is disabled. See 2 Start of Read = IS Low and IRD Low. 3 For IDMA, please refer to the ADSP-2100 Family User’s Manual. 4 End of Read = IS High or IRD High. ...
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... Disabled by default. 2 Start of Read = IS Low and IRD Low. Previous data remains until end of read. 3 End of Read = IS High or IRD High. 4 For IDMA, please refer to the ADSP-2100 Family User’s Manual. IACK IAD[15:0] Figure 27. IDMA Read, Short Read Only Mode REV ...
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... PRELIMINARY TECHNICAL DATA ADSP-21mod980N For current information contact Analog Devices at (800) ANALOGD 352-BALL PBGA Table 18. Pinout by Signal Name (Continued) PACKAGE PINOUT Signal Name CLKOUT_3 A physical layout of all sig- nals is shown in the CLKOUT_4 following tables. Figure on page 40 shows the signals CLKOUT_5 on the left side of the device CLKOUT_6 when viewed from the top ...
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... IAD13_A E2 A1 IAD13_B AD26 A5 IAD14_A D1 A11 IAD14_B AC24 A16 IAD15_A E4 A19 IAD15_B AC25 A20 IAD2_A C2 A21 IAD2_B V24 ADSP-21mod980N Table 18. Pinout by Signal Name (Continued) Signal Name Pin IAD3_A D3 IAD3_B W24 IAD4_A C1 IAD4_B W25 IAD5_A D2 IAD5_B W26 IAD6_A V4 IAD6_B M26 IAD7_A Y4 IAD7_B ...
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... PRELIMINARY TECHNICAL DATA ADSP-21mod980N For current information contact Analog Devices at (800) ANALOGD Table 18. Pinout by Table 18. Pinout by Signal Name (Continued) Signal Name (Continued) Signal Name Pin Signal Name PF2 C6 PF7_6 PF4_1 M1 PF7_7 PF4_2 C10 PF7_8 PF4_3 D18 RESET_1 PF4_4 AC2 RESET_2 PF4_5 ...
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... PRELIMINARY TECHNICAL DATA For current information contact Analog Devices at (800) ANALOGD Table 18. Pinout by Signal Name (Continued) Signal Name Pin VDDINT R1 VDDINT R2 VDDINT R3 REV. PrB 6/2001 ADSP-21mod980N 39 ...
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... PRELIMINARY TECHNICAL DATA ADSP-21mod980N For current information contact Analog Devices at (800) ANALOGD Signals by Pin Location—Top View, Left to Right GND A0 VDDINT VDDINT B IAD1_A GND VDDINT IAD0_A C IAD4_A IAD2_A GND IRD_A D IAD14_A IAD6_A IAD3_A GND E DR0A IAD13_A CLKIN IAD15_A F GND ...
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... VDDEXT TFS0_8 GND RESET_8 GND VDDEXT RFS0B GND GND GND VDDEXT DT1_8 GND EE_8 GND VDDEXT DT0B GND DR0B GND ADSP-21mod980N D21 D18 GND A D17 GND D16 B GND D15 D14 C D13 D12 D11 D D10 D09 ERESET E IS_3 BG_3 ...
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... INA Figure 28. 352-Lead metric Plastic Ball Grid Array (PBGA) (B-352) A complete modem requires the device listed in plus a software solution as described in on page 2. Table 19. Ordering Guide Ambient Temperature Part Number Range ADSP-21mod980N-000 0ºC to +70º ...