CS1301

Manufacturer Part NumberCS1301
DescriptionNational Semiconductor [Media Coprocessor]
ManufacturerNational Semiconductor
CS1301 datasheet
 
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Page 22/25:

REFERENCE VOLTAGES

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Signal Definitions
(Continued)
2.3

REFERENCE VOLTAGES

Outputs always drive to a level determined by the 3.3V I/O
voltage, with the exception of Open Drain mode outputs.
VREF_PCI
Determined Mode
PCI_AD00
PCI_AD27
PCI_AD01
PCI_AD28
PCI_AD02
PCI_AD29
PCI_AD03
PCI_AD30
PCI_AD04
PCI_AD31
PCI_AD05
PCI_CLK
PCI_AD06
PCI_C/BE#0
PCI_AD07
PCI_C/BE#1
PCI_AD08
PCI_C/BE#2
PCI_AD09
PCI_C/BE#3
PCI_AD10
PCI_PAR
PCI_AD11
PCI_FRAME#
PCI_AD12
PCI_IRDY#
PCI_AD13
PCI_TRDY#
PCI_AD14
PCI_STOP#
PCI_AD15
PCI_IDSEL
PCI_AD16
PCI_DEVSEL#
PCI_AD17
PCI_REQ#
PCI_AD18
PCI_GNT#
PCI_AD19
PCI_PERR#
PCI_AD20
PCI_SERR#
PCI_AD21
PCI_INTA#
PCI_AD22
PCI_INTB#
PCI_AD23
PCI_INTC#
PCI_AD24
PCI_INTD#
PCI_AD25
TRI_RESET#
PCI_AD26
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VREF_PERIPH and VREF_PCI determine input voltage
clamping, not input signal thresholds or output levels.
VREF_PERIPH
SDRAM Interface
Determined Mode
(3.3V Mode)
TRI_USERIRQ
MM_CLK0
MM_DQM2
TRI_TIMER_CLK
MM_CLK1
MM_DQM3
JTAG_TDI
MM_A00
MM_DQ13
JTAG_TDO
MM_A01
MM_DQ14
JTAG_TCK
MM_A02
MM_DQ15
JTAG_TMS
MM_A03
MM_DQ16
VI_CKL
MM_A04
MM_DQ17
VI_DVALID
MM_A05
MM_DQ18
VI_DATA0
MM_A06
MM_DQ19
VI_DATA1
MM_A07
MM_DQ20
VI_DATA2
MM_A08
MM_DQ21
VI_DATA3
MM_A09
MM_DQ22
VI_DATA4
MM_A10
MM_DQ23
VI_DATA5
MM_A11
MM_DQ24
VI_DATA6
MM_A12
MM_DQ25
VI_DATA7
MM_A13
MM_DQ26
VI_DATA8
MM_DQ00
MM_DQ27
VI_DATA9
MM_DQ01
MM_DQ28
IIC_SDA
MM_DQ02
MM_DQ29
IIC_SCL
MM_DQ03
MM_DQ30
VO_IO1
MM_DQ04
MM_DQ31
VO_IO2
MM_DQ05
MM_CKE0
VO_CLK
MM_DQ06
MM_CKE1
AI_SCK
MM_DQ07
MM_CS0#
AI_SD
MM_DQ08
MM_CS1#
AI_WS
MM_DQ09
MM_CS2#
AO_SCK
MM_DQ10
MM_CS3#
AO_WS
MM_DQ11
MM_RAS#
MM_DQ12
MM_CAS#
MM_DQM0
MM_WE#
MM_DQM1
22
Inputs
Output Only
(3.3V Mode)
Pins
TRI_CLKIN
VO_DATA0
BOOT_CLK
VO_DATA1
TESTMODE
VO_DATA2
SCANCPU
VO_DATA3
VO_DATA4
VO_DATA5
VO_DATA6
VO_DATA7
AO_OSCLK
AO_SCK
AO_SD1
AO_SD2
AO_SD3
AO_SD4
SPDO
Revision 2.2