HD6473217P16 Renesas Electronics Corporation., HD6473217P16 Datasheet
HD6473217P16
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HD6473217P16 Summary of contents
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To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April ...
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Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may ...
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Hitachi Single-Chip Microcomputer 27/2/03 H8/3217 Series H8/3217, H8/3216 H8/3214, H8/3212 H8/3202 Hardware Manual ...
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When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole ...
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The H8/3217 Series is a family of high-performance single-chip microcomputers ideally suited for embedded control of industrial equipment. The chips are built around an H8/300 CPU core: a high-speed processor. On-chip supporting modules provide ROM, RAM, four types of timers, ...
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Section 1 Overview ............................................................................................................ 1.1 Overview .......................................................................................................................... 1.2 Block Diagram.................................................................................................................. 1.3 Pin Assignments and Functions........................................................................................ 1.3.1 Pin Arrangement ................................................................................................. 1.3.2 Pin Functions....................................................................................................... Section 2 CPU ...................................................................................................................... 25 2.1 Overview .......................................................................................................................... 25 2.1.1 Features ............................................................................................................... 2.1.2 Address Space ..................................................................................................... 2.1.3 Register ...
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Section 3 MCU Operating Modes and Address Space 3.1 Overview .......................................................................................................................... 63 3.1.1 Operating Modes ................................................................................................. 3.1.2 Mode and System Control Registers................................................................... 3.2 System Control Register (SYSCR) .................................................................................. 64 3.3 Mode Control Register (MDCR)...................................................................................... 66 3.4 Mode Descriptions............................................................................................................ 66 3.5 ...
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Section 7 I/O Ports .............................................................................................................. 109 7.1 Overview .......................................................................................................................... 109 7.2 Port 1 ................................................................................................................................ 116 7.2.1 Overview ............................................................................................................. 116 7.2.2 Register Configuration and Descriptions ............................................................ 117 7.2.3 Pin Functions in Each Mode ............................................................................... 119 7.2.4 MOS Input Pull-Ups............................................................................................ 122 7.3 ...
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PWM Output Enable Registers A and B (PWOERA and PWOERB)................ 162 8.2.4 Port 1 Data Direction Register (P1DDR)............................................................ 163 8.2.5 Port 2 Data Direction Register (P2DDR)............................................................ 163 8.2.6 Port 1 Data Register (P1DR) ............................................................................... 163 8.2.7 Port 2 Data ...
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Register Descriptions........................................................................................................ 197 10.2.1 Timer Counter (TCNT)—H'FFCC (TMR0), H'FFD4 (TMR1), H'FF9E (TMRX) ................................................................................................. 197 10.2.2 Time Constant Registers A and B (TCORA and TCORB)—H'FFCA and H'FFCB (TMR0), H'FFD2 and H'FFD3 (TMR1), H'FF9C and H'FF9D (TMRX)................................................................................................. 197 10.2.3 Timer Control ...
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Block Diagram .................................................................................................... 232 12.1.3 Register Configuration ........................................................................................ 232 12.2 Register Descriptions........................................................................................................ 233 12.2.1 Timer Counter (TCNT) ....................................................................................... 233 12.2.2 Timer Control/Status Register (TCSR) ............................................................... 233 12.2.3 Register Access ................................................................................................... 235 12.3 Operation .......................................................................................................................... 236 12.3.1 Watchdog Timer Mode ...
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Register Configuration ........................................................................................ 290 14.2 Register Descriptions........................................................................................................ 291 2 14.2 Bus Data Register (ICDR) ............................................................................ 291 14.2.2 Slave Address Register (SAR) ............................................................................ 291 2 14.2 Bus Mode Register (ICMR).......................................................................... 292 2 14.2 Bus ...
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Section 16 RAM .................................................................................................................. 335 16.1 Overview .......................................................................................................................... 335 16.2 Block Diagram.................................................................................................................. 335 16.3 RAM Enable Bit (RAME)................................................................................................ 336 16.4 Operation .......................................................................................................................... 337 16.4.1 Expanded Modes (Modes 1 and 2)...................................................................... 337 16.4.2 Single-Chip Mode (Mode 3) ............................................................................... 337 Section 17 ...
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AC Characteristics .............................................................................................. 372 19.3 MCU Operational Timing ................................................................................................ 378 19.3.1 Bus Timing.......................................................................................................... 379 19.3.2 Control Signal Timing ........................................................................................ 381 19.3.3 16-Bit Free-Running Timer Timing.................................................................... 383 19.3.4 8-Bit Timer Timing ............................................................................................. 384 19.3.5 Pulse Width Modulation Timer Output Timing.................................................. ...
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Overview The H8/3217 Series is a series of single-chip microcomputers integrating a CPU core together with a variety of peripheral functions needed in control systems. The H8/300 CPU is a high-speed processor featuring powerful bit-manipulation instructions, ideally suited for ...
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Table 1-1 Features Feature Description CPU General register architecture • Eight 16-bit general registers, or • Sixteen 8-bit general registers High speed • Maximum clock rate: 16 MHz MHz MHz/3 V (ø clock) • Add/subtract: 125 ...
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... HIRQ 1 gate output 20 to IRQ 0 to KEYIN 0 Type Code 5 V Series (16 MHz Series 3 V Series (12 MHz) (10 MHz) HD6473217C16 HD6473217C16 HD6473217P16 HD6473217P16 HD6473217F16 HD6473217F16 HD6473217TF16 HD6473217TF16 , HIRQ ) Package ROM 64-pin windowed PROM shrink DIP (DC-64S) 64-pin shrink DIP (DP-64S) ...
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Table 1-1 Features (cont) Feature Description Product lineup Product Name H8/3217* H8/3216* H8/3214 ZTAT H8/3214* H8/3212* H8/3202* 4 Type Code 5 V Series (16 MHz Series 3 V Series (12 MHz) (10 MHz) HD6433217P16 HD6433217VP10 HD6433217P12 HD6433217F16 HD6433217VF10 ...
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Table 1-1 Features (cont) Feature Description On-chip peripheral functions Product Name Except H8/3212 and H8/3202 H8/3212 H8/3202 2 Notes: The I C bus interface is available as an option. Observe the following notes when using this option. 1. Please inform ...
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Block Diagram Figure 1-1 shows a block diagram of the H8/3217 Series. Note that the H8/3212 and H8/3202 have a subset specification that does not include certain of the on-chip supporting modules. See tables 1-2 to 1-4, Pin Assignments ...
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Pin Assignments and Functions 1.3.1 Pin Arrangement Figure 1-2 shows the pin arrangement of the H8/3217 Series in the DC-64S and DP-64S packages. Figure 1-3 shows the pin arrangement in the FP-64A package. Figure 1-4 shows the pin arrangement ...
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XTAL 1 EXTAL NMI STBY /TMCI /TMO /TMRI HIRQ / HSYNCI/P4 /TMCI 12 ...
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XTAL 1 EXTAL NMI STBY /TMCI /TMO ...
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Pin Functions (1) Pin Assignments in Each Operating Mode: Table 1-2 to table 1-4 list the assignments of the pins of the DC-64S, DP-64S, FP-64A, and TFP-80C packages in each operating mode. Table 1-2 Pin Assignments in Each Operating ...
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Table 1-2 Pin Assignments in Each Operating Mode (Except H8/3212 and H8/3202) (cont) Pin No. DC-64S DP-64S FP-64A TFP-80C Mode HSYNCI HSYNCO CSYNCI ø ...
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Table 1-2 Pin Assignments in Each Operating Mode (Except H8/3212 and H8/3202) (cont) Pin No. DC-64S DP-64S FP-64A TFP-80C — — — — 49 ...
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Table 1-3 Pin Assignments in Each Operating Mode (H8/3212) Pin No. DP-64S FP-64A TFP-80C — — — — ...
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Table 1-3 Pin Assignments in Each Operating Mode (H8/3212) (cont) Pin No. DP-64S FP-64A TFP-80C — — — — ...
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Table 1-3 Pin Assignments in Each Operating Mode (H8/3212) (cont) Pin No. DP-64S FP-64A TFP-80C — — ...
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Table 1-4 Pin Assignments in Each Operating Mode (H8/3202) Pin No. DP-64S FP-64A TFP-80C — — — — ...
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Table 1-4 Pin Assignments in Each Operating Mode (H8/3202) (cont) Pin No. DP-64S FP-64A TFP-80C — — — — ...
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Table 1-4 Pin Assignments in Each Operating Mode (H8/3202) (cont) Pin No. DP-64S FP-64A TFP-80C — — ...
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Pin Functions: Table 1-5 gives a concise description of the function of each pin. Table 1-5 Pin Functions DC-64S Type Symbol DP-64S Power Clock XTAL 9 EXTAL 10 ø 23 RES ...
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Table 1-5 Pin Functions (cont) DC-64S Type Symbol DP-64S Data bus WAIT Bus 38 control NMI Interrupt 13 signals IRQ IRQ ...
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Table 1-5 Pin Functions (cont) DC-64S Type Symbol DP-64S 16-bit FTCI 1 free- running timer FTOA 2 FTOB 3 FTI 4 8-bit timer TMO , 18 0 (channel TMO , except TMO 24 x H8/3202) TMCI , ...
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Table 1-5 Pin Functions (cont) DC-64S Type Symbol DP-64S General purpose ...
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Table 1-5 Pin Functions (cont) DC-64S Type Symbol DP-64S Timer VSYNCI 4 connec- HSYNCI 20 tion CSYNCI 22 (except FBACKI 23 H8/3202) VSYNCO 3 HSYNCO 21 CLAMPO bus SCL 31 0 interface SCL 33 1 (option) ...
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Overview The H8/3217 Series has the generic H8/300 CPU: an 8-bit central processing unit with a speed- oriented architecture featuring sixteen general registers. This section describes the CPU features and functions, including a concise description of the addressing modes ...
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Power-down mode — SLEEP instruction 2.1.2 Address Space The H8/300 CPU supports an address space kbytes for storing program code and data. The memory map is different for each mode (modes 1, 2, and 3). ...
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Register Descriptions 2.2.1 General Registers All the general registers can be used as both data registers and address registers. When used as address registers, the general registers are accessed as 16-bit registers (R0 to R7). When used as data ...
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Bit 6—User Bit (U): This bit can be written and read by software for its own purposes (using the LDC, STC, ANDC, ORC, and XORC instructions). Bit 5—Half-Carry (H): This bit is set to 1 when the ADD.B, ADDX.B, SUB.B, ...
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Data Formats The H8/300 CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word) data. • Bit manipulation instructions operate on 1-bit data specified as bit ..., 7) in ...
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Data Formats in General Registers Data of all the sizes above can be stored in general registers as shown in figure 2-3. Data Type Register No 1-bit data RnH 1-bit data RnL 7 Byte data RnH MSB ...
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Memory Data Formats Figure 2-4 indicates the data formats in memory. Word data stored in memory must always begin at an even address. In word access the least significant bit of the address is regarded ...
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Addressing Modes 2.4.1 Addressing Modes The H8/300 CPU supports eight addressing modes. Each instruction uses a subset of these addressing modes. (1) Register Direct—Rn: The register field of the instruction specifies 16-bit general register containing the ...
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The ADDS and SUBS instructions implicitly contain the value immediate data. Some bit manipulation instructions contain 3-bit immediate data (#xx:3) in the second or fourth byte of the instruction, specifying a bit number. (7) ...
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Instruction Set Table 2-1 lists the H8/300 CPU instruction set. Table 2-1 Instruction Classification Function Instructions Data transfer MOV, MOVTPE Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, DIVXU, CMP, NEG Logic operations AND, ...
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Operation Notation Rd General register (destination) Rs General register (source) Rn, Rm General register General register field n m <EAs> Effective address: general register or memory location (EAd) Destination operand (EAs) Source operand SP Stack pointer PC ...
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Data Transfer Instructions Table 2-2 describes the data transfer instructions. Figure 2-5 shows their object code formats. Table 2-2 Data Transfer Instructions Instruction Size* Function MOV B/W (EAs) Moves data between two general registers or between a general register ...
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Legend op: Operation field di: Direction field (0-load from; 1-store to Register field m n ...
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Arithmetic Operations Table 2-3 describes the arithmetic instructions. See figure 2-6 in section 2.5.4, Shift Operations for their object codes. Table 2-3 Arithmetic Instructions Instruction Size* Function ADD B/W Rd SUB Performs addition or subtraction on data in two ...
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Logic Operations Table 2-4 describes the four instructions that perform logic operations. See figure 2-6 in section 2.5.4, Shift Operations for their object codes. Table 2-4 Logic Operation Instructions Instruction Size* Function AND B Rd Performs a logical AND ...
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Legend op: Operation field Register field m n #imm: Immediate data ...
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Bit Manipulations Table 2-6 describes the bit-manipulation instructions. Figure 2-7 shows their object code formats. Table 2-6 Bit-Manipulation Instructions Instruction Size* Function BSET B 1 Sets a specified bit in a general register or memory to 1. The bit ...
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Table 2-6 Bit-Manipulation Instructions (cont) Instruction Size* Function BLD B (<bit-No.> of <EAd>) Copies a specified bit in a general register or memory to the C flag. BILD ¬ (<bit-No.> of <EAd>) Copies the inverse of a specified bit in ...
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Before Execution of BCLR Instruction Input/output Input Input Pin state Low High DDR Execution of BCLR Instruction BCLR.B #0, @P4DDR After Execution of BCLR Instruction Input/output Output Output Pin ...
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Legend op: Operation field ...
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Legend op: Operation field Register field m n abs: Absolute address #imm: Immediate data Figure 2-7 Bit Manipulation Instruction Codes (cont #imm ...
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Branching Instructions Table 2-7 describes the branching instructions. Figure 2-8 shows their object code formats. Table 2-7 Branching Instructions Instruction Size Function Bcc — Branches if condition cc is true. Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) ...
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Legend op: Operation field cc: Condition field r : Register field m disp: Displacement abs: Absolute address Figure 2-8 Branching Instruction Codes ...
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System Control Instructions Table 2-8 describes the system control instructions. Figure 2-9 shows their object code formats. Table 2-8 System Control Instructions Instruction Size* Function RTE — Returns from an exception-handling routine. SLEEP — Causes a transition to the ...
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Legend op: Operation field r : Register field n #imm: Immediate data Figure 2-9 System Control Instruction Codes 2.5.8 Block Data Transfer Instruction Table 2-9 describes the EEPMOV instruction. Figure 2-10 shows its object code ...
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Legend op: Operation field Figure 2-10 Block Data Transfer Instruction Notes on EEPMOV Instruction • The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes specified by R4L from the address specified by R5 ...
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CPU States The CPU has three states: the program execution state, exception-handling state, and power-down state. The power-down state is further divided into three modes: the sleep mode, software standby mode, and hardware standby mode. Figure 2-11 summarizes these ...
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Interrupt request Exception- handling state RES = 1 Reset state Notes transition to the reset state occurs when RES goes low, except when the chip is in the hardware standby mode transition from any state to ...
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Branches to that address, returning to the program execution state. See section 4, Exception Handling, for further information on the exception-handling state. 2.6.3 Power-Down State The power-down state includes three modes: the sleep mode, the software standby mode, and ...
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Internal address bus Internal read signal Internal data bus (read) Internal write signal Internal data bus (write) Figure 2-13 On-Chip Memory Access Cycle Bus cycle T state T state 2 1 Address Read data Write data 57 ...
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Address bus AS: High RD: High WR: High Data bus: High impedance state Figure 2-14 Pin States during On-Chip Memory Access Cycle 58 Bus cycle T state T state 1 2 Address ...
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Access to On-Chip Register Field and External Devices The on-chip register field (I/O ports, dual-port RAM, on-chip supporting module registers, etc.) and external devices are accessed in a cycle consisting of three states: T byte of data can be ...
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Address bus AS: High RD: High WR: High Data bus: high impedance state Figure 2-16 Pin States during On-Chip Supporting Module Access 60 Bus cycle T state T state 2 1 Address T state 3 ...
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T 1 ø Address bus AS RD WR: High Data bus Figure 2-17 (a) External Device Access Timing (Read) Read cycle state T state 2 Address Read data T state 3 61 ...
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Address bus AS RD: High WR Data bus Figure 2-17 (b) External Device Access Timing (Write) 62 Write cycle T state T state 2 1 Address Write data T state 3 ...
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Section 3 MCU Operating Modes and Address Space 3.1 Overview 3.1.1 Operating Modes The H8/3217 Series operates in three modes numbered 1, 2, and 3. An additional non-operating mode (mode 0) is used for PROM version programming. The mode is ...
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System Control Register (SYSCR) Bit 7 6 SSBY STS2 Initial value 0 0 Read/Write R/W R/W The system control register (SYSCR 8-bit register that controls the operation of the chip. Bit 7—Software Standby (SSBY): Enables transition to ...
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Bit 3—External Reset (XRST): Indicates the source of a reset. A reset can be generated by input of an external reset signal watchdog timer overflow when the watchdog timer is used. XRST is a read-only bit. It ...
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Mode Control Register (MDCR) Bit 7 6 — — Initial value 1 1 Read/Write — — Note: * Initialized according to MD The mode control register (MDCR 8-bit register that indicates the operating mode of the chip. ...
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Note: In mode 2, ports 1 and 2 are initially general-purpose input ports. Software must change the desired pins to output before using them for the address bus. See section 7, I/O Ports for details. Mode 3 (Single-Chip Mode): In ...
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Mode 1 Expanded mode without on-chip ROM H'0000 Vector table H'0063 H'0064 External address space H'F77F H'F780 On-chip RAM * , 2048 bytes H'FF7F H'FF80 External address space H'FF8F H'FF90 On-chip I/O register field H'FFFF Note: * External memory can ...
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Mode 1 Expanded mode without on-chip ROM H'0000 Vector table H'0063 H'0064 External address space H'F77F H'F780 *1 On-chip RAM , 2048 bytes H'FF7F H'FF80 External address space H'FF8F H'FF90 On-chip I/O register field H'FFFF Notes: *1. External memory can ...
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Mode 1 Expanded mode without on-chip ROM H'0000 Vector table H'0063 H'0064 External address space H'FB7F H'FB80 On-chip RAM * , 1024 byte H'FF7F H'FF80 External address space H'FF8F H'FF90 On-chip I/O register field H'FFFF Note: * External memory can ...
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Mode 1 Expanded mode without on-chip ROM H'0000 Vector table H'0063 H'0064 External address space H'B77F H'B780 *1, *2 Reserved H'FD7F H'FD80 *1 On-chip RAM , 512 bytes H'FF7F H'FF80 External address space H'FF8F H'FF90 On-chip I/O register field H'FFFF ...
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Section 4 Exception Handling [Key-sense interrupt function incorporated in all models except the H8/3212] Note that the H8/3212 does not have an IRQ KEYIN input signals and the KMIMR register. 7 4.1 Overview The H8/3217 Series recognizes only two kinds ...
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Reset Sequence The reset state begins when RES goes low or a watchdog reset occurs. To ensure correct resetting, at power-on the RES pin should be held low for at least 20 ms reset during operation, the ...
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RES/watchdog reset (internal) ø Internal address bus Internal read signal Internal write signal Internal data bus (16 bits) (1) Reset exception handling vector address (H'0000) (2) Program start address (3) First instruction of program Figure 4-1 Reset Sequence (Mode 2 ...
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Figure 4-2 Reset Sequence (Mode 1) 76 ...
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Disabling of Interrupts after Reset All interrupts, including NMI, are disabled immediately after a reset. The first program instruction, located at the address specified at the top of the vector table, is therefore always executed. To prevent program crashes, ...
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Table 4-2 Interrupts Interrupt Source NMI IRQ 0 IRQ 1 IRQ 2 Reserved IRQ (KEYIN 6 0 Reserved Host interface IBF1 (IDR1 reception complete) (except H8/3212) IBF2 (IDR2 reception complete) 16-bit ICI (Input capture) free-running OCIA (Output compare A) timer ...
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Notes: 1. H'0000 and H'0001 contain the reset vector. 2. H'0002 to H'0005 are reserved in the H8/3217 Series and are not available to the user The I C bus interface is an option. 4.3.2 Interrupt-Related Registers The ...
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IRQ Sense Control Register (ISCR)—H'FFC6 Bit 7 — IRQ6SC Initial value 1 Read/Write — Bits and 6—IRQ to IRQ 0 bits select how the input at pins IRQ Bit ...
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If execution of interrupt-handling routines under these conditions is not desired, it can be avoided by using the following procedure to disable and clear interrupt requests. 1. Set the I bit the CCR, masking interrupts. Note that ...
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KMIMR0 (1) P6 /KEYIN 0 0 KMIMR1 (1) P6 /KEYIN KMIMR6 (1) P7 /KEYIN ...
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The IRQ input signal is generated as the logical OR of the key-sense inputs. When pins KEYIN 6 to KEYIN ( and bits should be cleared enable the corresponding key-sense interrupts. ...
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NMI interrupt * IRQ flag 0 IRQ0E IRQ 0 interrupt OVF OVIE OVI interrupt Note: * For edge-sensed interrupts, these AND gates change to the circuit shown below. IRQ edge 0 IRQ0E Figure 4-4 Block Diagram of Interrupt Controller The ...
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Figure 4 flowchart of the interrupt (and reset) operations. Figure 4-7 shows the interrupt timing sequence for the case in which the software interrupt-handling routine is in on-chip ROM and the stack is in on-chip RAM. (1) An ...
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Reset Figure 4-5 Hardware Interrupt-Handling Sequence 86 Program execution No Interrupt requested? Yes Yes NMI Yes No IRQ ? 0 Yes No IRQ ? 1 Yes Latch vector no. Save PC Save CCR I 1 ...
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SP – – – – (R7) Stack area Before interrupt is accepted PC: Program counter CCR: Condition code register SP: Stack pointer Notes: 1. The PC contains the address of the first ...
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Interrupt accepted Interrupt priority decision. Wait for end of instruction Interrupt request signal ø Internal address (1) bus Internal read signal Internal write signal Internal 16-bit (2) data bus (1) Instruction prefetch address (Instruction is not executed. Address is saved ...
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Interrupt Response Time Table 4-4 indicates the time that elapses from an interrupt request signal until the first instruction of the software interrupt-handling routine is executed. Since the H8/3217 Series accesses its on- chip memory 16 bits at a ...
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Internal address bus Internal write signal OCIAE OCFA OCIA interrupt signal Figure 4-8 Contention between Interrupt and Disabling Instruction The above contention does not occur if the enable bit or flag is cleared to 0 while the interrupt mask ...
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SP BSR instruction H'FEFF set Upper byte of program counter Lower byte of program counter L R1L: General register R1L SP: Stack pointer Figure 4-9 Example of Damage Caused by Setting an Odd ...
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There are four host interface output pins—GA which are set to the port function (input state) initially. There are eight host interface I/O pins, HDB to HDB ; in single-chip mode, these are outputs when the ...
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Section 5 Wait-State Controller 5.1 Overview The H8/3217 Series has an on-chip wait-state controller that enables insertion of wait states into bus cycles for interfacing to low-speed external devices. 5.1.1 Features Features of the wait-state controller are listed below. • ...
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Input/Output Pins Table 5-1 summarizes the wait-state controller’s input pin. Table 5-1 Wait-State Controller Pins Name Abbreviation WAIT Wait 5.1.4 Register Configuration Table 5-2 summarizes the wait-state controller’s register. Table 5-2 Register Configuration Name Wait-state control register 5.2 Register ...
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Bits 7 and 6—Reserved: These bits cannot be modified and are always read as 1. Bit 5—Clock Double (CKDBL): Controls frequency division of clock signals supplied to supporting modules. For details, see section 6, Clock Pulse Generator. Bit 4—Reserved: This ...
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Wait Modes Programmable Wait Mode: The number of wait states (T inserted in all accesses to external addresses. Figure 5-2 shows the timing when the wait count is 1 (WC1 = 0, WC0 = 1). ø Address bus AS ...
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Pin Wait Mode: In all accesses to external addresses, the number of wait states (T bits WC1 and WC0 are inserted. If the WAIT pin is low at the fall of the system clock (ø) in the last of these ...
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Pin Auto-Wait Mode: If the WAIT pin is low, the number of wait states (T WC1 and WC0 are inserted. In pin auto-wait mode, if the WAIT pin is low at the fall of the system clock (ø) in the ...
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Section 6 Clock Pulse Generator 6.1 Overview The H8/3217 Series has a built-in clock pulse generator (CPG) consisting of an oscillator circuit, a duty adjustment circuit, and a prescaler that generates clock signals for the on-chip supporting modules. 6.1.1 Block ...
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Wait-State Control Register (WSCR) WSCR is an 8-bit readable/writable register that controls frequency division of the clock signals supplied to the supporting modules. It also controls wait-state insertion. WSCR is initialized to H' reset and in hardware ...
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Oscillator Circuit If an external crystal is connected across the EXTAL and XTAL pins, the on-chip oscillator circuit generates a system clock signal. Alternatively, an external clock signal can be applied to the EXTAL pin. (1) Connecting an External ...
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Crystal Oscillator: Figure 6-3 shows an equivalent circuit of the crystal resonator. The crystal resonator should have the characteristics listed in table 6-2. L XTAL Figure 6-3 Equivalent Circuit of External Crystal Table 6-2 External Crystal Parameters Frequency (MHz) 2 ...
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Note on Board Design: When an external crystal is connected, other signal lines should be kept away from the crystal circuit to prevent induction from interfering with correct oscillation. See figure 6-4. The crystal and its load capacitors should be ...
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Input of External Clock Signal Circuit Configuration: An external clock signal can be input as shown in the examples in figure 6-5. In example (b) in figure 6-5, the external clock signal should be kept high during standby. If ...
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External Clock Input: The external clock signal should have the same frequency as the desired system clock (ø). Clock timing parameters are given in table 6-3 and figure 6-6. Table 6-3 Clock Timing 5.5 V ...
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Table 6-4 shows the external clock output settling delay time, and figure 6-7 shows the external clock output settling delay timing. The oscillator circuit and duty adjustment circuit have a function for adjusting the waveform of the external clock input ...
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Duty Adjustment Circuit When the clock frequency is 5 MHz or above, the duty adjustment circuit adjusts the duty cycle of the signal from the oscillator circuit to generate the system clock (ø). 6.4 Prescaler The 1/2 frequency divider ...
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Overview The H8/3217 Series has five 8-bit input/output ports, one 7-bit input/output port, and one 6-bit input/output port. Table 7-1 lists the functions of each port in each operating mode. As table 7-1 indicates, the port pins are multiplexed, ...
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Table 7-1 (a) H8/3217, H8/3216, and H8/3214 Port Functions Port Description Pins Port 1 • 8-bit I/O port • Can drive 7 PW LEDs • Built-in input pull-ups Port 2 • 8-bit I/O port ...
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Table 7-1 (a) H8/3217, H8/3216, and H8/3214 Port Functions (cont) Port Description Pins Port 5 • 6-bit I/O port Port 6 • 7-bit I/O port ...
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Table 7-1 (b) H8/3212 Port Functions Port Description Pins Port 1 • 8-bit I/O port • Can drive 7 PW LEDs • Built-in input pull-ups Port 2 • 8-bit I/O port • Can drive ...
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Table 7-1 (b) H8/3212 Port Functions (cont) Port Description Pins Port 5 • 6-bit I/O port Port 6 • 7-bit I/O port ...
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Table 7-1 (c) H8/3202 Port Functions Port Description Pins Port 1 • 8-bit I/O port • Can drive 7 LEDs • Built-in input pull-ups Port 2 • 8-bit I/O port • Can drive 15 ...
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Table 7-1 (c) H8/3202 Port Functions (cont) Port Description Pins Port 5 • 6-bit I/O port Port 6 • 7-bit I/O port • Built-in input ...
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Port 1 7.2.1 Overview Port 8-bit input/output port with the pin configuration shown in figure 7-1. The pin functions differ depending on the operating mode. Port 1 has built-in programmable MOS input pull-ups that can be ...
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Register Configuration and Descriptions Table 7-2 summarizes the port 1 registers. Table 7-2 Port 1 Registers Name Port 1 data direction register Port 1 data register Port 1 input pull-up control register Port 1 Data Direction Register (P1DDR) Bit ...
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Port 1 Data Register (P1DR) Bit Initial value 0 Read/Write R/W R/W P1DR is an 8-bit register that stores data for pins read, the value in P1DR is obtained directly, regardless of the ...
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Pin Functions in Each Mode Port 1 has different pin functions in different modes. A separate description for each mode is given below. Pin Functions in Mode 1: In mode 1 (expanded mode with on-chip ROM disabled), port 1 ...
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Mode 2: In mode 2 (expanded mode with on-chip ROM enabled), port 1 can provide lower address output pins, PWM output pins, and general input pins. Each pin becomes a lower address output pin or PWM output pin if its ...
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Mode 3: In mode 3 (single-chip mode), port 1 can provide PWM output pins and general input/output pins. When used for general input/output, the input or output direction of each pin can be selected individually. A pin becomes a general ...
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MOS Input Pull-Ups Port 1 has built-in programmable MOS input pull-ups that are available in modes 2 and 3. The pull-up for each bit can be turned on and off individually. To turn on an input pull-up in mode ...
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Port 2 7.3.1 Overview Port 8-bit input/output port with the pin configuration shown in figure 7-5. The pin functions differ depending on the operating mode. Port 2 has built-in, software-controllable MOS input pull-ups that can be ...
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Register Configuration and Descriptions Table 7-4 summarizes the port 2 registers. Table 7-4 Port 2 Registers Name Port 2 data direction register Port 2 data register Port 2 input pull-up control register Port 2 Data Direction Register (P2DDR) Bit ...
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Port 2 Data Register (P2DR) Bit Initial value 0 Read/Write R/W R/W P2DR is an 8-bit register that stores data for pins read, the value in P2DR is obtained directly, regardless of the actual ...
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Pin Functions in Each Mode Port 2 has different pin functions in different modes. A separate description for each mode is given below. Pin Functions in Mode 1: In mode 1 (expanded mode with on-chip ROM disabled), port 2 ...
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Mode 2: In mode 2 (expanded mode with on-chip ROM enabled), port 2 can provide upper address output pins, PWM output pins, and general input pins. Each pin becomes an upper address output pin or PWM output pin if its ...
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Mode 3: In mode 3 (single-chip mode) port 2 can provide PWM output pins and general input/output pins. When used for general input/output, the input or output direction of each pin can be selected individually. A pin becomes a general ...
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MOS Input Pull-Ups Port 2 has built-in programmable MOS input pull-ups that are available in modes 2 and 3. The pull-up for each bit can be turned on and off individually. To turn on an input pull-up in mode ...
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Port 3 7.4.1 Overview Port 8-bit input/output port that is multiplexed with the data bus and host interface data bus. Its pin configuration is shown in figure 7-9. The pin functions differ depending on the operating ...
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Register Configuration and Descriptions Table 7-6 summarizes the port 3 registers. Table 7-6 Port 3 Registers Name Port 3 data direction register Port 3 data register Port 3 input pull-up control register Port 3 Data Direction Register (P3DDR) Bit ...
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Port 3 Data Register (P3DR) Bit Initial value 0 Read/Write R/W R/W P3DR is an 8-bit register that stores data for pins read, the value in P3DR is obtained directly, regardless of the actual ...
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Pin Functions in Each Mode Port 3 has different pin functions in different modes. A separate description for each mode is given below. Pin Functions in Modes 1 and 2: In mode 1 (expanded mode with on-chip ROM disabled) ...
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Mode 3: In mode 3 (single-chip mode), port input/output port when the host interface enable bit (HIE) in the system control register (SYSCR) is cleared the HIE bit is set to 1 and a ...
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Port 4 7.5.1 Overview Port 8-bit input/output port that is multiplexed with the host interface (HIF) input/output , CS pins (GA ), host interrupt request output pins (HIRQ 20 2 and X, and timer connection input/output ...
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Register Configuration and Descriptions Table 7-8 summarizes the port 4 registers. Table 7-8 Port 4 Registers Name Port 4 data direction register Port 4 data register Notes: 1. Bit 6 is read-only. 2. Bit 6 only is undetermined; the ...
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Port 4 Data Register (P4DR) Bit Initial value 0 Read/Write R/W Note: * Depends on the state of the P4 P4DR is an 8-bit register that stores data for port 4 pins P4 when a P4DDR bit ...
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Pin Functions Port 4 pins are used for 8-bit timer and timer connection input/output and øclock output. Table 7-9 indicates the pin functions of port 4. Table 7-9 Port 4 Pin Functions Pin Pin Functions and Selection Method P4 ...
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Table 7-9 Port 4 Pin Functions (cont) Pin Pin Functions and Selection Method P4 /TMO / Bits OS3 to OS0 in TCSR of 8-bit timer 1, bit SYNCE in STCR, bit HSYNCO/HIRQ the operating mode select the ...
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Table 7-9 Port 4 Pin Functions (cont) Pin Pin Functions and Selection Method P4 /TMO Bits OS3 to OS0 in TCSR of 8-bit timer 0 and bit follows OS3 to OS0 P4 DDR 1 Pin function ...
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Port 5 7.6.1 Overview Port 6-bit input/output port that is multiplexed with input/output pins (TxD TxD , RxD , SCK ) of serial communication interfaces 0 and 1. The port 5 pin functions are the 1 ...
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Port 5 Data Direction Register (P5DDR) 7 Bit — Initial value 1 Read/Write — P5DDR is an 8-bit register that controls the input/output direction of each pin in port 5. A pin functions as an output pin if the corresponding ...
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Pin Functions Port 5 has the same pin functions in each operating mode. Individual pins can also be used as SCI0 or SCI1 input/output pins. Table 7-11 indicates the pin functions of port 5. Table 7-11 Port 5 Pin ...
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Table 7-11 Port 5 Pin Functions (cont) Pin Pin Functions and Selection Method P5 /SCK Bit C/A in SMR of SCI0, bits CKE0 and CKE1 in SCR of SCI0 and bit select the pin function as follows ...
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Port 6 7.7.1 Overview Port 7-bit input/output port that is multiplexed with 16-bit free-running timer (FRT) and timer connection input/output pins (FTCI, FTOA, FTOB, FTI, VSYNCI, VSYNCO), key-sense input pins and with IRQ to IRQ 0 ...
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Register Configuration and Descriptions Table 7-12 summarizes the port 6 registers. Table 7-12 Port 6 Registers Name Port 6 data direction register Port 6 data register Key-sense MOS pull-up control register Port 6 Data Direction Register (P6DDR) Bit 7 ...
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Port 6 Data Register (P6DR) Bit 7 — Initial value 1 Read/Write — R/W P6DR is an 8-bit register that stores data for pins P6 modified and is always read as 1. When a P6DDR bit is set to 1, ...
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Pin Functions Port 6 has the same pin functions in all operating modes. The pins are multiplexed with FRT and timer connection input/output, key-sense input, and IRQ pin functions of port 6. Table 7-13 Port 6 Pin Functions Pin ...
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Table 7-13 Port 6 Pin Functions (cont) Pin Pin Functions and Selection Method P6 /FTI/VSYNCI/ P6 DDR 3 3 KEYIN 3 Pin function P6 /FTOB/ Bit OEB in TCR of the FRT, the SYNCE bit in STCR, and the P6 ...
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Port 7 7.8.1 Overview Port 8-bit input/output port that also provides the bus control signal input/output pins (RD, WR, AS, WAIT), host interface (HIF) input pins (HA 2 and I C bus interface (IIC0 and IIC1) ...
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Register Configuration and Descriptions Table 7-15 summarizes the port 7 registers. Table 7-15 Port 7 Registers Name Port 7 data direction register Port 7 data register Key-sense MOS pull-up control register Port 7 Data Direction Register (P7DDR) 7 Bit ...
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When a port P6DDR bit is cleared port 6 is read, the pin state is obtained; this pin can be selected according to the contents of KMIMR7 to KMIMR4. When KMIMR is set to 1 (initial value), ...
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Pin Functions The pins of port 7 have different functions in modes 1 and 2 and in mode 3. Individual pins are used as bus control signal input/output pins (RD, WR, AS, WAIT), host interface (HIF) input pins , ...
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Table 7-16 Port 7 Pin Functions (cont) Pin Pin Functions and Selection Method P7 /AS/CS Bit 7 DDR and the operating mode select the pin function as follows Operating mode Modes 1 and 2 P7 DDR 4 ...
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Table 7-16 Port 7 Pin Functions (cont) Pin Pin Functions and Selection Method P7 /SCL Bit ICE in ICCR of IIC0 and bit ICE P7 DDR 0 Pin function DDR select the pin function as follows 0 ...
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156 ...
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Section 8 PWM Timers [Incorporated in all models except the H8/3202] 8.1 Overview The H8/3217 Series has an on-chip pulse width modulation (PWM) timer module with sixteen outputs. Sixteen output waveforms are generated from a common time base, enabling PWM ...
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Block Diagram Figure 8-1 shows a block diagram of the PWM timer module /PW ...
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Input and Output Pins Table 8-1 lists the output pins of the PWM timer. There are no input pins. Table 8-1 PWM Timer Module Output Pins Name PWM output pin 0 PWM output pin 1 PWM output pin 2 ...
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Register Configuration Table 8-2 lists the registers of the PWM timer module. Table 8-2 PWM Timer Module Registers Name PWM data register 0 PWM data register 1 PWM data register 2 PWM data register 3 PWM data register 4 ...
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Register Descriptions 8.2.1 PWM Data Registers (PWDR0 to PWDR15) Bit 7 Initial value 0 Read/Write R/W Each PWDR is an 8-bit readable/writable register that specifies the duty cycle of the basic pulse to be output, and the number of ...
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OS Description 0 PWM direct output (PWDR value corresponds to high width of output) 1 PWM inverted output (PWDR value corresponds to low width of output) 8.2.3 PWM Output Enable Registers A and B (PWOERA and PWOERB) PWOERA Bit 7 ...
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Port 1 Data Direction Register (P1DDR) Bit 7 P1 DDR P1 7 Initial value 0 Read/Write W P1DDR is an 8-bit write-only register that specifies the input/output direction and PWM output for each pin of port 1 in bit ...
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Port 2 Data Register (P2DR) Bit Initial value 0 Read/Write R/W P2DR is an 8-bit readable/writable register used to fix PWM output at 1 (when (when OS = 1). For details ...
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From the frequency of the selected internal clock, the PWM resolution, PWM conversion period, and carrier frequency can be calculated as follows. Resolution (minimum pulse width)= 1/internal clock frequency PWM conversion period = resolution Carrier frequency = 16/PWM conversion period ...
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Operation 8.3.1 Correspondence between PWM Data Register Contents and Output Waveform The upper 4 bits of PWDR specify the duty cycle of the basic pulse 15/16 with a resolution of 1/16, as shown in table 8-4. ...
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Table 8-5 Position of Pulses Added to Basic Pulses Lower 4 Bits 0000 0001 0010 0011 0100 Yes 0101 Yes 0110 Yes 0111 Yes 1000 Yes Yes 1001 Yes Yes 1010 Yes Yes 1011 Yes Yes ...
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168 ...
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Section 9 16-Bit Free-Running Timer 9.1 Overview The H8/3217 Series has an on-chip 16-bit free-running timer (FRT) module that uses a 16-bit free- running counter as a time base. Applications of the FRT module include rectangular-wave output (up to two ...
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Block Diagram Figure 9-1 shows a block diagram of the free-running timer. Internal clock sources ø External P clock source ø P ø FTCI P Clock select Compare- match A FTOA FTOB FTI Compare- match B Control logic ICI ...
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Input and Output Pins Table 9-1 lists the input and output pins of the free-running timer module. Table 9-1 Input and Output Pins of Free-Running Timer Module Name Abbreviation Counter clock input FTCI Output compare A FTOA Output compare ...
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Register Descriptions 9.2.1 Free-Running Counter (FRC)—H'FF92 Bit Initial value Read/Write R/W R/W R/W R/W The FRC is a 16-bit readable/writable up-counter that increments on an internal pulse generated from a clock source. ...
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Input Capture Register (ICR)—H'FF98 Bit Initial value Read/Write The input capture register is a 16-bit read-only register. When the rising or falling edge of the signal at the ...
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Timer Control Register (TCR)—H'FF90 Bit 7 ICIE OCIEB Initial value 0 Read/Write R/W TCR is an 8-bit readable/writable register that enables and disables output signals and interrupts, and selects the timer clock source. TCR is initialized to H'00 by ...
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Bit 4—Timer Overflow Interrupt Enable (OVIE): Selects whether to request a free-running timer overflow interrupt (FOVI) when the timer overflow flag (OVF) in the timer status/control register (TCSR) is set to 1. Bit 4 OVIE Description 0 Timer overflow interrupt ...
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Timer Control/Status Register (TCSR)—H'FF91 Bit 7 ICF OCFB Initial value 0 Read/Write R/(W)* R/(W)* Note: * Software can write bits clear the flags, but cannot write these bits. TCSR ...
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Bit 5—Output Compare Flag A (OCFA): This status flag is set to 1 when the FRC value matches the OCRA value. OCFA must be cleared by software set by hardware, however, and cannot be set by software. Bit ...
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Bit 1—Input Edge Select (IEDG): Selects the rising or falling edge of the input capture signal (FTI). Bit 1 IEDG Description 0 FRC contents are transferred to ICR on the falling edge of FTI 1 FRC contents are transferred to ...
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CPU Interface The free-running counter (FRC), output compare registers (OCRA and OCRB), and input capture register (ICR) are 16-bit registers, but they are connected to an 8-bit data bus. When the CPU accesses these registers, to ensure that both ...
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Upper byte write CPU writes data H'AA (2) Lower byte write CPU writes data H'55 Figure 9-2 (a) Write Access to FRC (When CPU Writes H'AA55) 180 Bus interface FRCH [ Bus interface FRCH [H'AA] Module data bus TEMP ...
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Upper byte read CPU writes interface data H'AA (2) Lower byte read CPU writes interface data H'55 Figure 9-2 (b) Read Access to FRC (When FRC Contains H'AA55) Bus FRCH [H'AA] Bus FRCH [ ] Module data bus TEMP ...
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Operation 9.4.1 FRC Incrementation Timing The FRC increments on a pulse generated once for each cycle of the selected (internal or external) clock source. (1) Internal Clock Sources: Can be selected by the CKS1 and CKS0 bits in TCR. ...
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External Clock Input: Can be selected by the CKS1 and CKS0 bits in the TCR. The FRC increments on the rising edge of the FTCI clock signal. The pulse width of the external clock signal must be at least ...
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Output Compare Timing When a compare-match occurs, the logic level selected by the output level bit (OLVLA or OLVLB) in TCSR is output at the output compare pin (FTOA or FTOB). Figure 9-5 shows the timing of this operation ...