UPD754302 Renesas Electronics Corporation., UPD754302 Datasheet
UPD754302
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UPD754302 Summary of contents
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PD754302,754304,754302(A),754304(A) 4-BIT SINGLE-CHIP MICROCONTROLLER The µ PD754304 is one of the “75XL Series” 4-bit single-chip microcontrollers with data processing capability comparable to that of 8-bit microcontrollers. The µ PD754303(A) has a higher reliability than the µ PD754304. The microcontrollers ...
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ORDERING INFORMATION Parts Number µ PD754302GS-××× 36-pin plastic shrink SOP (300 mil, 0.8 mm pitch) µ PD754302GS-×××-A 36-pin plastic shrink SOP (300 mil, 0.8 mm pitch) µ PD754304GS-××× 36-pin plastic shrink SOP (300 mil, 0.8 mm pitch) µ PD754304GS-×××-A 36-pin ...
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Functional Outline Parameter • 0.95, 1.91, 3.81, 15.3 µ 4.19 MHz with system clock) Instruction execution time • 0.67, 1.33, 2.67, 10.7 µ 6.0 MHz with system clock) 2048 × 8 bits ( µ PD754302) On-chip ...
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PIN CONFIGURATION (Top View) ······································································································ BLOCK DIAGRAM ································································································································ PIN FUNCTION ····································································································································· 9 3.1 Port Pins ······································································································································9 3.2 Non-port Pins ···························································································································· 10 3.3 Pin Input/Output Circuits ········································································································· 11 3.4 Recommended Connections for Unused Pins ······································································· 13 ...
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APPENDIX A. COMPARISON OF FUNCTIONS AMONG µ PD750004, 754304, AND 75P4308 ··········· 65 APPENDIX B. DEVELOPMENT TOOLS ································································································· 67 APPENDIX C. RELATED DOCUMENTS ································································································· 70 µ PD754302, 754304, 754302(A), 754304(A) Data Sheet U10797EJ2V1DS 5 ...
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PIN CONFIGURATION (Top View) 36-pin plastic shrink SOP (300 mil, 0.8-mm pitch) µ PD754302GS-××× , µ PD754302GS-×××-A , µ PD754302GS(A)-××× µ PD754304GS-×××, µ PD754304GS-×××-A , µ PD754304GS(A)-××× RESET 4 P33 5 P32 ...
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PIN IDENTIFICATION P00-P03 : PORT0 P10-P13 : PORT1 P20-P23 : PORT2 P30-P33 : PORT3 P50-P53 : PORT5 P60-P63 : PORT6 P70-P73 : PORT7 P80, P81 : PORT8 KR0-KR7 : Key Return 0-7 SCK : Serial Clock SI : Serial Input ...
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BASIC INTERVAL TIMER/ WATCHDOG TIMER INTBT TOUT0 INTT0 COUNTER TI0/TI1/P13 8-BIT CASCADED TIMER/EVENT PTO0/P20 16-BIT COUNTER#0 TIMER/ 8-BIT EVENT TIMER/EVENT PTO1/P21 COUNTER COUNTER#1 INTT1 SI/P03 CLOCKED SO/SB0/P02 SERIAL INTERFACE SCK/P01 INTCSI TOUT0 INT0/P10 INT1/P11 INTERRUPT INT2/P12 CONTROL INT4/P00 KR0-KR3/P60-P63 8 ...
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PIN FUNCTION 3.1 Port Pins Alternate Pin Name Input/Output Function P00 Input INT4 P01 Input/Output SCK P02 Input/Output SO/SB0 P03 Input SI P10 Input INT0 P11 INT1 P12 INT2 P13 TI0/TI1 P20 Input/Output PTO0 P21 PTO1 P22 PCL P23 ...
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Non-port Pins Alternate Pin Name Input/Output Function TI0/TI1 Input P13 PTO0 Output P20 PTO1 P21 PCL P22 SCK Input/Output P01 SO/SB0 P02 SI Input P03 INT4 Input P00 INT0 Input P10 INT1 P11 INT2 Input P12 KR0-KR3 Input P60-P63 ...
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Pin Input/Output Circuits The µ PD754304 pin input/output circuits are shown schematically. TYPE P-ch IN N-ch CMOS specification input buffer. TYPE B IN Schmitt trigger input having hysteresis characteristic. TYPE B P.U.R. P.U.R. P-ch ...
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TYPE F-B P.U.R. enable output V disable (P) data output disable output disable (N) P.U.R. : Pull-Up Resistor 12 µ PD754302, 754304, 754302(A), 754304(A) TYPE M P.U.R. (Mask Option) P-ch data DD output disable P-ch Input IN/OUT instruction ...
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Recommended Connections for Unused Pins Table 3-1. List of Recommended Connections for Unused Pins Pin P00/INT4 P01/SCK P02/SO/SB0 P03/SI P10/INT0-P12/INT2 P13/TI0/TI1 P20/PTO0 P21/PTO1 P22/PCL P23 P30-P33 P50-P53 P60/KR0-P63/KR3 P70/KR4-P73/KR7 P80, P81 IC µ PD754302, 754304, 754302(A), 754304(A) Recommended Connection ...
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SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE 4.1 Difference between Mk I and Mk II Modes The CPU of µ PD754304 has the following two modes and Mk II, either of which can be ...
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Setting Method of Stack Bank Select Register (SBS) Switching between the Mk I mode and Mk II mode can be done by the SBS. Figure 4-1 shows the format. The SBS is set by a 4-bit memory manipulation instruction. ...
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MEMORY CONFIGURATION • Program Memory (ROM) .... .... • Addresses 0000H and 0001H Vector table wherein the program start address and the values set for the RBE and MBE at the time a RESET signal is generated are written. ...
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Figure 5-1. Program Memory Map (1/2) Address MBE RBE 0 0 Internal reset start address Internal reset start address MBE RBE 0 0 INTBT/INT4 INTBT/INT4 0 ...
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Figure 5-1. Program Memory Map (2/2) Address MBE RBE 0 0 Internal reset start address Internal reset start address MBE RBE 0 0 INTBT/INT4 INTBT/INT4 0 ...
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PD754302, 754304, 754302(A), 754304(A) Figure 5-2. Data Memory Map General-purpose register area Data area static RAM (256 × 4) Stack area Peripheral hardware ...
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PERIPHERAL HARDWARE FUNCTIONS 6.1 Digital Input Ports The following three types of I/O ports are provided. • CMOS input (Ports 0, 1) • CMOS I/O (Ports • N-ch open-drain I/O (Port 5) Total Table ...
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Clock Generator • Clock generator configuration The clock generator provides the clock signals to the CPU and peripheral hardware and its configuration is shown in Figure 6-1. The operation of the clock generator is set with the processor clock ...
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Clock Output Circuit The clock output circuit outputs clock pulses from the P22/PCL pin, and is used to apply for remote controller waveform output or to supply clock pulse peripheral LSIs. : Φ, 524, 262, 65.5 kHz (during 4.19-MHz ...
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Basic Interval Timer/Watchdog Timer The basic interval timer/watchdog timer has the following functions. • Interval timer operation to generate a reference time interrupt • Watchdog timer operation to detect a runaway of program and reset the CPU • Selects ...
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Timer/Event Counter The µ PD754304 has two channels of timer/event counters. Its configuration is shown in Figures 6-4 and 6-5. The timer/event counter has the following functions. • Programmable interval timer operation • Square wave output of any frequency ...
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TM06 TM05 TM04 TM03 TM02 TM01 TM00 PORT1.3 Decoder Input buffer TI0/TI1/P13 From clock X MPX generator Timer/event counter (channel ...
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TM16 TM15 TM14 TM13 TM12 TM11 TM10 PORT1.3 Input buffer TI0/TI1/P13 Timer/event counter (channel 0) output MPX From clock generator ...
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Serial Interface The µ PD754304 incorporates the clocked 8-bit serial interface, and the following three modes are provided. • Operation stop mode • 3-wire serial I/O mode • 2-wire serial I/O mode µ PD754302, 754304, 754302(A), 754304(A) Data Sheet ...
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Bit test CSIM P03/SI Selector P02/SO/SB0 P01/SCK P01 output Iatch Internal bus SBIC Slave address register (SVA) (8) Matching RELT signal Address comparator (8) SET CLR Shift register (SIO) D (8) INTCSI Serial clock counter control ...
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Bit Sequential Buffer ....... 16 Bits The bit sequential buffer (BSB special data memory for bit manipulation and the bit manipulation can be easily performed by changing the address specification and bit specification in sequence, therefore it ...
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INTERRUPT FUNCTION AND TEST FUNCTION The µ PD754304 has seven kinds of interrupt sources and one kind of test source. Two types of edge detection testable inputs are provided for INT2 of the test source. The interrupt control circuit ...
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IM2 IM1 IM0 INTBT IRQBT Both edge INT4/P00 IRQ4 detector Edge INT0/P10 Note Selec- IRQ0 tor detector Edge IRQ1 INT1/P11 detector INTCSI IRQCSI INTT0 IRQT0 INTT1 IRQT1 Rising edge INT2/P12 IRQ2 Selec- detector tor KR0/P60 Falling edge ...
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STANDBY FUNCTION In order to save dissipation power while a program standby mode, two types of standby modes (STOP mode and HALT mode) are provided for the µ PD754304. Table 8-1. Operation Status in Standby Mode ...
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RESET FUNCTION There are two reset inputs: external RESET signal and RESET signal sent from the basic interval timer/ watchdog timer. When either one of the RESET signals are input, an internal RESET signal is generated. Figure 9-1 shows ...
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Table 9-1. Status of Each Hardware After Reset (1/2) Hardware µ PD754302 Program counter (PC) µ PD754304 PSW Carry flag (CY) Skip flag (SK0-SK2) Interrupt status flag (IST0, IST1) Bank enable flag (MBE, RBE) Stack pointer (SP) Stack bank select ...
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Table 9-1. Status of Each Hardware After Reset (2/2) Hardware Interrupt Interrupt request flag (IRQ×××) function Interrupt enable flag (IE×××) Interrupt priority select register (IPS) INT0 mode registers (IM0, IM1, IM2) Digital port Output buffer Output latch I/O ...
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MASK OPTION The µ PD754304 has the following mask options: • Mask option of P50 through P53 Pull-up resistors can be connected to these pins. (1) Specify connection of a pull-up resistor in 1-bit units. (2) Do not specify ...
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INSTRUCTION SETS (1) Expression formats and description methods of operands The operand is described in the operand column of each instruction in accordance with the description method for the operand expression format of the instruction. For details, refer to ...
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Legend in explanation of operation register; 4-bit accumulator register register register register register register register ...
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Explanation of symbols under addressing area column * MBE•MBS (MBS = 0, 15 MBE = (000H-07FH (F80H-FFFH) MBE = MBS ...
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Instruction Mnemonic Operand group Transfer MOV A, #n4 reg1, #n4 XA, #n8 HL, #n8 rp2, #n8 A, @HL A, @HL+ A, @HL– A, @rpa XA, @HL @HL, A @HL mem XA, mem mem, A mem reg1 ...
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Instruction Number Mnemonic Operand group of bytes Bit transfer MOV1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit fmem.bit, CY pmem.@L, CY @H+mem.bit, CY Operation ADDS A, #n4 XA, #n8 A, @HL XA, rp' rp'1, XA ADDC A, @HL XA, rp' rp'1, ...
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Instruction Mnemonic Operand group Comparison SKE reg, #n4 @HL, #n4 A, @HL XA, @HL A, reg XA, rp' Carry flag SET1 CY manipulation CLR1 CY SKT CY NOT1 CY Memory bit SET1 mem.bit manipulation fmem.bit pmem.@L @H+mem.bit CLR1 mem.bit fmem.bit ...
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Instruction Mnemonic Operand group Note Branch BR addr addr1 !addr $addr $addr1 PCDE PCXA Note The above operations in the double boxes can be performed only in the Mk II mode. µ PD754302, 754304, 754302(A), 754304(A) Number Number of machine ...
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Instruction Mnemonic Operand group Branch BR BCDE BCXA Note3 BRA !addr1 BRCB !caddr Note3 Subroutine CALLA !addr1 stack control Note3 CALL !addr Notes 1. “0” must be set to the most significant bit of the register C and register B. ...
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Instruction Mnemonic Operand group Note Subroutine CALLF !faddr stack control Note RET Note RETS Note The above operations in the double boxes can be performed only in the Mk II mode. The other operations can be performed only in the ...
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Instruction Mnemonic Operand group Note1 Subroutine RETS stack control Note1 RETI PUSH rp BS POP rp BS Interrupt EI control IE××× DI IE××× Note2 Input/output IN A, PORTn XA, PORTn Note2 OUT PORTn, A PORTn, XA Notes 1. The above ...
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Instruction Mnemonic Operand group CPU control HALT STOP NOP Special SEL RBn MBn Notes 1, 2 GETI taddr Notes 1. The TBR and TCALL instructions are the table definition assembler directives of the GETI instruction. 2. The above operations in ...
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Instruction Mnemonic Operand group Notes 1, 2 Special GETI taddr Notes 1. The TBR and TCALL instructions are the table definition assembler directives of the GETI instruction. 2. The above operations in the double boxes can be performed only in ...
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ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings ( Parameter Symbol Supply voltage V DD Input voltage V Except port Port 5 I2 Output voltage V O Output current, high I Per pin OH For all ...
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System Clock Oscillator Characteristics (T Resonator Recommended Constant Ceramic resonator Crystal resonator External clock X1 X2 Notes 1. Only the oscillator characteristics are shown. For the instruction execution time, refer to AC ...
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Recommended Oscillation Circuit Constants Ceramic Resonator (T = –40 to +85 A Manufacturer Product Frequency Recommended Circuit Constants (pF) Oscillation Voltage Range (V (MHz) Murata CSB1000J Note 1.0 Mfg. Co., Ltd CSA2.00MG 2.0 CST2.00MG CSA3.58MG 3.58 CST3.58MGW CSA3.58MGU CST3.58MGWU CSA4.00MG ...
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Note If using Murata’s CSB1000J (1.0 MHz) as the ceramic resonator, a limited resistor (Rd = 5.6 kΩ) is required (see figure below). If using any other recommended resonator, no limited resistor is needed. Caution The oscillation circuit constants and ...
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DC Characteristics (T = – Parameter Symbol Output current, low I Per pin OL For all pins Input voltage, high V Ports IH1 V Ports RESET IH2 V Port ...
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DC Characteristics (T = –40 to +85 A Parameter Symbol Note1 Supply current I 6.00 MHz DD1 Crystal resonator DD2 I 4.19 MHz DD1 Crystal resonator ...
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AC Characteristics (T = –40 to +85 A Parameter Symbol Note1 CPU clock cycle time t CY (Minimum instruction execution time = 1 machine cycle) TI0, TI1 input frequency f TI TI0, TI1 input high- and TIH ...
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Serial Transfer Operation 2-wire and 3-wire Serial I/O Mode (SCK...Internal clock output) (T Parameter Symbol SCK cycle time 2.7 to 5.5 V KCY1 DD SCK high- and 2.7 to 5.5 V KL1 DD ...
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AC Timing Test Points (Excluding X1 Input) V (MIN (MAX (MIN (MAX.) OL Note For the values, refer to the DC Characteristics. Clock Timing X1 input TI0, TI1 Timing TI0, TI1 µ PD754302, 754304, ...
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Serial Transfer Timing 3-wire Serial I/O Mode SCK SI t KSO1 2-wire Serial I/O Mode SCK SB0 58 µ PD754302, 754304, 754302(A), 754304(A) t KCY1 KL1, 2 KH1 SIK1, 2 KSI1, 2 ...
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Interrupt Input Timing INT0,1,2,4 KR0-7 RESET Input Timing RESET Data Memory STOP Mode Low-Supply Voltage Data Retention Characteristics (T Parameter Symbol Release signal set time t SREL Oscillation stabilization t Release by RESET WAIT Note1 wait time Release by interrupt ...
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Data Retention Timing (on releasing STOP mode by RESET Execution of STOP instruction RESET Data Retention Timing (Standby release signal: on releasing STOP mode by interrupt signal Execution of STOP instruction Standby release signal (interrupt request) ...
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CHARACTERISTICS CURVES (REFERENCE VALUES 5.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 µ PD754302, 754304, 754302(A), 754304(A) (System Clock: 6.0-MHz Crystal Resonator) PCC = 0011 PCC = 0010 PCC = ...
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5.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 µ PD754302, 754304, 754302(A), 754304(A) (System Clock: 4.19-MHz Crystal Resonator) PCC = 0011 PCC = 0010 PCC = 0001 PCC = 0000 ...
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PACKAGE DRAWING 36 PIN PLASTIC SHRINK SOP (300 mil NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. µ PD754302, ...
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RECOMMENDED SOLDERING CONDITIONS The µ PD754302 and µ PD754304 should be soldered and mounted under the following recommended conditions. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Table 15-1. Surface Mounting Type Soldering Conditions (1) ...
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APPENDIX A. COMPARISON OF FUNCTIONS AMONG µ PD750004, 754304, AND 75P4308 Item Program memory Mask ROM 0000H-0FFFH (4096 × 8 bits) 000H-1FFH (512 × 4 bits) Data memory CPU 75XL CPU • 0.67, 1.33, 2.67, or 10.7 µ s (at ...
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Item TM0, 1 registers Bits 0, 1, and 7 are fixed to 0 Vectored interrupt External: 3, internal: 4 Test input External: 1, internal: 1 Test enable flag (IEW) Provided Test request flag (IRQW) Supply voltage V DD Operating ambient ...
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APPENDIX B. DEVELOPMENT TOOLS The following development tools are available for development of application systems using the µ PD754304. In the 75XL Series, a common relocatable assembler is used in combination with a device file dedicated to each model. Language ...
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Debugging tools The in-circuit emulators (IE-75000-R and IE-75001-R) are available as the program debugging tool for the µ PD754304. The system configurations are described as follows. Note 1 Hardware IE-75000-R In-circuit emulator for debugging the hardware and software when developing ...
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OS for IBM PC The following IBM PC OS’s are supported. OS Version TM PC DOS Ver. 5.02 to Ver. 6.3 Note Note J6.1/V to J6.3/V MS-DOS Ver. 5.0 to Ver. 6.22 Note Note 5.0/V to 6.2/V TM Note IBM ...
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APPENDIX C. RELATED DOCUMENTS The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Device related documents Document Name µ PD754302, 754304 Data Sheet µ PD75P4308 Data Sheet µ PD754304 User’s ...
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NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V malfunction. Take care ...
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Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and ...
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MS-DOS is a trademark of Microsoft Corporation. IBM DOS, PC/AT, and PC DOS are trademarks of IBM Corporation. These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to ...