UPD98405GL-PMU Renesas Electronics Corporation., UPD98405GL-PMU Datasheet
UPD98405GL-PMU
Related parts for UPD98405GL-PMU
UPD98405GL-PMU Summary of contents
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ATM INTEGRATED SAR CONTROLLER DESCRIPTION The µ PD98405 (NEASCOT-S20 of ATM cells. It has a PCI bus interface, a SONET/SDH 155 Mbps framer, and a clock recovery circuit and supports an ABR function in hardware. The µ PD98405 conforms ...
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SYSTEM CONFIGURATION EXAMPLE Control memory 2 ATM Interface Card Rx PMD Tx µ PD98405 Expansion ROM TM EEPROM PCI bus Data Sheet S12689EJ3V0DS µ µ µ µ PD98405 ATM network ...
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BLOCK DIAGRAM PMD PMD interface & Clock recovery & Clock synthesizer PCI interface Host system Data Sheet S12689EJ3V0DS µ µ µ µ PD98405 3 ...
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OUTLINE OF PINS 304-pin plastic QFP (0.5 mm fine pitch) (40 × × × × 40) 304 1 JTAG PMD PHY device EEPROM Control memory Data Sheet S12689EJ3V0DS µ µ µ µ PD98405 229 228 153 152 ...
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FBGA (0.8 mm pitch) (19 × × × × 19) (Bottom view) µ µ µ µ PD98405S1- Data Sheet ...
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PIN NAME ABRT_B: Abort ACK64_B: Acknowledge 64-bit transfer AD63 to AD0: Address/data AGND: Ground for analog part ASEL_B: Slave address select ATTN_B: Attention AV : +3.3 V power supply for DD3 analog part BE3_B to BE0_B: Byte enable CA18 to ...
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PIN CONFIGURATION 304-pin plastic QFP (0.5 mm fine pitch) (40 × × × × 40) Generic No. PCI Mode No. PCI Mode Mode 1 GND GND 38 V DD3 AD12 DD3 DD3 3 AD24 AD24 40 ...
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Generic No. PCI Mode No. PCI Mode Mode 149 CD7 CD7 188 CA0 189 GND 150 CD6 CD6 190 V 151 V V DD3 DD3 DD3 191 CBE3_B 152 GND GND 153 GND GND 192 CBE2_B 154 V V 193 ...
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Remarks 1. Open the pins to which no function is allocated (pins marked “–” in the Generic Mode column in the above table) in the Generic mode. Fix pin 5 (IDSEL) to the low/high level this document, the ...
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FBGA (0.8 mm pitch) (19 × × × × 19) No. PCI Mode Generic No. PCI Mode Mode B2 GND GND N1 AD8 PCBE0_B DD3 DD3 B1 AD24 AD24 N4 AD7 C1 PCBE3_B BE3_B ...
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No. PCI Mode Generic No. PCI Mode Mode P19 CA10 CA10 H18 ROMA7 P21 CA9 CA9 G22 ROMA6 P22 CA8 CA8 G21 ROMA5 P18 CA7 CA7 G19 ROMA4 P17 CA6 CA6 G17 ROMA3 N19 GND GND F22 GND N21 CA5 ...
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PIN FUNCTIONS .................................................................................................................................. 13 1.1 PHY Layer Device Interface Signal ........................................................................................... 13 1.1.1 UTOPIA interface ............................................................................................................................. 13 1.1.2 PHY device control interface (external PHY mode, PHM of GMR register = 1)................................ 15 1.2 Bus Interface Signals ................................................................................................................. 16 1.2.1 ...
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PIN FUNCTIONS The package of the µ PD98405 has 304 pins. For details on how to use each pin, refer to µ µ µ µ PD98405 User’s Manual (S12250E). 1.1 PHY Layer Device Interface Signal The PHY Layer device ...
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Pin Name Pin No. QFP FBGA EMPTY_B/ 248 E15 RCLAV (shared with RCIC) RCLK 244 F16 Tx7 to Tx0 255 to 258, A14, E14, 260 to 263 F14, D13, A13, E13, F13, E12 TSOC 250 D15 TENBL_B 251 B15 FULL_B/ ...
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PHY device control interface (external PHY mode, PHM of GMR register = 1) Pin Name Pin No. QFP FBGA PHR/W_B 266 D12 (shared with PHYALM) PHOE_B 265 A12 PHCE_B 267 D11 (shared with SD) PHINT_B 268 A11 (shared with ...
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Bus Interface Signals The µ PD98405 supports a PCI bus interface or generic bus interface. Whether the PCI bus interface or generic bus interface supported is selected by the PCI_MODE signal. The PCI bus interface can ...
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Pin Name Pin No. QFP FBGA SIZE2 63 U2 SIZE1 64 V1 SIZE0 65 T5 DR/W_B 60 T4 ATTN_B 294 D6 GNT_B 291 B6 RDY_B 23 H2 I/O I/O Level O TTL Burst size. These pins indicate the size of ...
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Pin Name Pin No. QFP FBGA ABRT_B 27 J1 ERR_B 28 J5 SR/W_B 24 H1 SEL_B 21 H6 ASEL_B 22 H4 CLK 290 A6 RST_B 289 F7 INTR_B 288 D7 18 I/O I/O Level I TTL Abort. This signal is ...
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PCI bus interface signal (PCI_MODE pin: high level) The µ PD98405 has a 32-/64-bit PCI bus interface. This bus interface can be directly connected to a PCI bus. In addition, the µ PD98405 also has a serial EEPROM interface ...
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Pin Name Pin No. I/O QFP FBGA STOP_B 27 J1 I/O Sustained 3-state DEVSEL_B 24 H1 I/O Sustained 3-state IDSEL Note REQ_B 294 D6 O GNT_B 291 B6 I PERR_B 28 J5 I/O Sustained 3-state SERR_B 29 ...
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PCI bus 64-bit expansion interface signals Open AD63 to AD32, PCBE7_B to PCBE4_B, and PAR64 when using the 32-bit PCI bus interface. Pin Name Pin No. QFP FBGA AD63 71, V2, V4, V5, Y1, AD32 73 ...
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Serial EEPROM interface signals The µ PD98405 has a serial EEPROM interface supporting MICROWIRE EEPROM interface, the contents of the PCI configuration register can be loaded from an EEPROM connected. Remark It is recommended that National Semiconductor’s “NM93C46” be ...
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Control Memory Interface Signals The control memory interface is used by the µ PD98405 to access the external control memory and external PHY layer device. This interface consists of a 19-bit address bus, a 32-bit data bus. The control ...
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PMD Interface Signals (internal PHY mode, PHM of GMR register = 0) The PMD interface is used to connect a module such as an optical transceiver/receiver. Pin Name Pin No. I/O QFP FBGA RDIT 278 A9 RDIC 277 E9 ...
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JTAG Boundary Scan Signals Remark This function can be supported upon request. These signals conform to IEEE1149.1 JTAG Boundary-Scan Standard. Pin Name Pin No. QFP FBGA JDI 285 E8 JDO 284 F8 3-state JMS 283 D8 JCK 282 B8 ...
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Power and Ground Pin Name Pin No. QFP V 8, 20, 32, 44, 56, 67, 81, E2, H5, K1, N5, R6, U5, DD5 93, 105, 287, 299 AA4, W7, U9, B7 14, 26, 38, 50, 62, ...
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Pin Status during and After Reset Pin Name RENBL_B RCLK Tx7 to Tx0 TSOC TENBL_B TCLK PHR/W_B (external PHY)/PHYALM (internal PHY) PHOE_B PHCE_B (external PHY)/SD (internal PHY) AD31 to AD0 PCBE3_B to PCBE0_B (PCI)/BE3_B to BE0_B (Generic) PAR FRAME_B ...
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Pin Name CWE_B COE_B TDOT TDOC Note JDO Note During JRST_B input Remark The internal PHY mode is set (PHM of GMR register = 0) after reset. 28 During Reset 1 1 Undefined Undefined Hi-Z Data Sheet S12689EJ3V0DS µ µ ...
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ELECTRICAL SPECIFICATIONS Some of the electrical specifications for the µ PD98405 vary depending on the device version. The version history is described below for explanation. Device Version History Part Number Version µ PD98405GL-PMU V3.0 V3.1 V4.0 µ PD98405S1-6C V3.1 ...
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Absolute Maximum Ratings Parameter Symbol Supply voltage V DD5 Input/output voltage Operating ambient frequency Storage temperature Notes Clamping diode-dedicated power supply DD5 2. By supplying 5 V for clamping diode, the device can be protected from an ...
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DC Characteristics Parameter Symbol Output voltage, high V OH1 V OH2 V OH3 V OH4 Output voltage, low V OL1 V OL2 V OL3 V OL4 V OL5 Supply current I DD Input leakage current (normal input Note ...
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Capacitance (T = +25° Parameter Symbol Input capacitance C IN CLK input capacitance C CLK IDSEL input capacitance C IDSEL Output capacitance C OUT I/O capacitance C I/O On-chip pull-down resistor Parameter Symbol Note ...
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AC Characteristics (Output pin load: 50 pF) CLK input (BUS interface clock - CLK pin) Parameter Symbol CLK cycle time t CYCLK CLK high-level width t CLKH CLK low-level width t CLKL CLK slew rate slew 2.0 V CLK 1.5 ...
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PCI Bus Interface Bus master read Parameter Symbol CLK ↑→ FRAME_B, REQ64_B valid t time CLK ↑→ FRAME_B, REQ64_B float t DFRAMEF time CLK ↑→ AD (Address) valid time t CLK ↑→ AD (Address) float time t AD (Data) setup ...
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Bus master read CLK t DFRAME FRAME_B REQ64_B t DADDRF t DADDR AD31 to AD0 (Address) AD63 to AD32 t DPCBE PCBE3_B to PCBE0_B t DPCBE PCBE7_B to PCBE4_B t DIRDY IRDY_B TRDY_B DEVSEL_B ACK64_B t DPAR PAR PAR64 PERR_B ...
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Bus master write Parameter Symbol CLK ↑→ FRAME_B, REQ64_B valid t time CLK ↑→ FRAME_B, REQ64_B float t DFRAMEF time CLK ↑→ AD (Address) valid time t CLK ↑→ Data valid time CLK ↑→ Data float time t CLK ↑→ ...
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Bus master write CLK t DFRAME FRAME_B REQ64_B t t DADDR DDATA AD31 to AD0 (Address) AD63 to AD32 t DPCBE PCBE3_B to PCBE0_B t DPCBE PCBE7_B to PCBE4_B t DIRDY IRDY_B TRDY_B DEVSEL_B ACK64_B t DPAR PAR (Output) PAR64 ...
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Target read Parameter Symbol FRAME_B setup time t FRAME_B hold time t AD (Address) setup time AD (Address) hold time t CLK ↑→ AD (Data) valid time CLK ↑→ AD (Data) float time t PCBE_B setup time PCBE_B hold time ...
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Target read CLK t HFRAME t SFRAME FRAME_B t t SADDR HADDR AD31 to AD0 (Address SPCBE HPCBE PCBE3_B to PCBE0_B t SIRDY IRDY_B t DTRDY TRDY_B t DDEVSEL DEVSEL_B t SPAR PAR PERR_B CLK t DSTOP STOP_B ...
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Target write Parameter Symbol FRAME_B setup time t FRAME_B hold time t AD (Address) setup time AD (Address) hold time t AD (Data) setup time AD (Data) hold time PCBE_B setup time PCBE_B hold time IRDY_B setup time IRDY_B hold ...
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Target write CLK t HFRAME t SFRAME FRAME_B t HADDR t SADDR AD31 to AD0 (Address SPCBE HPCBE PCBE3_B to PCBE0_B t SIRDY IRDY_B t DTRDY TRDY_B t DDEVSEL DEVSEL_B t SPAR PAR PERR_B CLK t DSTOP STOP_B ...
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Bus arbitration Parameter Symbol CLK ↑→ REQ_B valid time t DREQ GNT_B setup time t SGNT GNT_B hold time t HGNT Bus arbitration CLK t DREQ REQ_B GNT_B 64-bit bus expansion Parameter Symbol t REQ64_B setup time SREQ64 (to RST_B ...
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Configuration read Parameter Symbol FRAME_B setup time t FRAME_B hold time t AD (Address) setup time AD (Address) hold time t CLK ↑→ AD (Data) valid time CLK ↑→ AD (Data) float time t PCBE_B setup time PCBE_B hold time ...
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Configuration read CLK t SFRAME FRAME_B t SADDR AD31 to AD0 (Address) t SPCBE PCBE3_B to PCBE0_B t SIDSEL IDSEL IRDY_B TRDY_B DEVSEL_B PAR PERR_B 44 t HFRAME t DDATAF t t HADDR DDATA (Data) t HPCBE t HIDSEL t ...
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EEPROM interface Parameter Symbol E2PCLK high-level width t WE2PCKLH E2PCLK low-level width t WE2PCLKL E2PCLK ↓→ E2PCS valid time t E2PCS ↑→ E2PCLK t E2PCLK ↓→ E2PDO valid time t E2PDI → E2PCLK setup time t E2PCLK → E2PDI hold ...
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Expansion ROM interface Parameter Symbol ROMOE_B ↓→ ROMD valid time t DROMOE ROMCS_B ↓→ ROMD valid time t DROMCS ROMA valid time → ROMD valid t ROMACC time ROMOE_B ↑→ ROMD float time t HROMOE ROMCS_B ↑→ ROMD float time ...
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Generic bus interface Slave write access Parameter Symbol ASEL_B setup time t SASEL ASEL_B hold time t HASEL SEL_B setup time t SSEL SEL_B hold time t HSEL Address setup time t SDADD Address hold time t HDADD Data setup ...
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Slave read access Parameter Symbol ASEL_B setup time t SASEL ASEL_B hold time t HASEL SEL_B setup time t SSEL SEL_B hold time t HSEL Address setup time t SDADD Address hold time t HDADD CLK ↑→ data delay time ...
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DMA write access Parameter Symbol CLK ↑→ ATTN_B delay time t DATTN GNT_B setup time t SGNT GNT_B hold time t HGNT CLK ↑→ DR/W_B delay time t DDRW CLK ↑→ SIZE delay time t DSIZE CLK ↑→ address delay ...
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DMA read access Parameter Symbol CLK ↑→ ATTN_B delay time t DATTN GNT_B setup time t SGNT GNT_B hold time t HGNT CLK ↑→ DR/W_B delay time t DDRW CLK ↑→ SIZE delay time t DSIZE CLK ↑→ address delay ...
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DMA read access (Example: 2-word burst) CLK t DATTN ATTN_B t GNT_B t DDRW DR/W_B t DSIZE SIZE2 to SIZE0 AD31 to AD0 BE3_B to BE0_B RDY_B (Normal mode) RDY_B (Early mode) PAR3 to PAR0 t SGNT HGNT t DSADD ...
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ABRT_B, ERR_B, and OE_B pins Parameter Symbol ABRT_B setup time t SABRT ABRT_B hold time t HABRT ERR_B setup time t SERR ERR_B hold time t HERR OE_B ↓→ AD/PAR output t DADOE determination time OE_B ↑→ AD/PAR high-impedance t ...
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UTOPIA interface (external PHY mode) Transmission operation Parameter Symbol SCLK ↑→ TCLK ↑ delay time t DTCLK TCLK ↑→ Tx delay time t TCLK ↑→ TSOC delay time t DTSOC TCLK ↑→ TENBL_B delay time t DTEN FULL_B setup time ...
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UTOPIA interface (1) Transmission timing TCLK t DTX Tx7 to Tx0 TSOC t t DTSOC DTSOC TENBL_B t SFULL FULL_B H1 to H4: ATM header P1 to P9: Payload data ‘00H’ P1 Invalid ...
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UTOPIA interface (2) Reception timing RCLK t t SRX HRX Rx7 to Rx0 RSOC t HRSOC t SRSOC RENBL_B t SEMPT EMPTY_B H1 to H4: ATM header P1 to P7: Payload data Invalid ...
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Control memory access Write Parameter Symbol CA → CWE_B ↓ setup time t SCWE CBE_B → CWE_B ↓ setup time t SCWE2 CWE_B low-level width t CWEL CD hold time (from CWE_ B ↑) t HCD COE_B hold time (from ...
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Read Parameter Symbol Permissible CD delay time t DCDCB (from CBE_B ↓) Permissible CD delay time (from t DCDCA CA) Permissible CD delay time t DCDCO (from COE_B ↓) CD hold time (from CBE_B ↑) t HCDCB CD hold time ...
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Read timing SCLK CBE3_B to CBE0_B CA18 to CA0 “H” CWE_B COE_B CD31 to CD0 CPAR3 to CPAR0 58 t DCDCB t DCDCA t DCDCO (Input) (Input) t DCPCO t DCPCA t DCPCB Data Sheet S12689EJ3V0DS µ µ µ µ ...
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PHY status access Write Parameter Symbol SCLK ↑→ CA delay time t DPCA SCLK ↑→ PHRW_B delay time t DPHRW SCLK ↑→ PHCE_B delay time t DPHCE SCLK ↑→ CD delay time t DPCD1 PHCE_B ↑→ CD delay time t ...
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Read timing 1 clock 6 clocks SCLK t DPCA CA18 to CA0 t DPHRW PHRW_B t DPHCE PHCE_B PHOE_B CD31 to CD0 5 clocks 4 clocks t DPCA t DPHOE t SPCD (Input) t DPHCE t DPHOE t HPOECD ...
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PMD serial interface (internal PHY mode) Parameter Symbol REFCLK cycle time t CYRF REFCLK high-level width t WRFH REFCLK low-level width t WRFL REFCLK Others Parameter Symbol SEL_B recovery time t RVSEL SEL_B ↑→ GNT_B ↓ recovery time t RVSM ...
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PACKAGE DRAWING 304 PIN PLASTIC QFP (FINE PITCH) (40x40) 228 229 304 NOTE Each lead centerline is located within 0. its true position (T.P.) at maximum material condition 153 ...
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PLASTIC FBGA (19x19 Index mark φ ...
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RECOMMENDED SOLDERING CONDITIONS The µ PD98405 should be soldered and mounted under the following recommended conditions. For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other ...
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NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation ...
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NEASCOT-S20 and EEPROM are trademarks of NEC Corporation. MICROWIRE is a trademark of National Semiconductor Corporation. • The information in this document is current as of November, 2000. The information is subject to change without notice. For actual design-in, refer ...