MC68HC705B5CFN Motorola, MC68HC705B5CFN Datasheet

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MC68HC705B5CFN

Manufacturer Part Number
MC68HC705B5CFN
Description
8-bit single chip microcomputer, 6K bytes EPROM, self-check replaced by bootstrap firmware, no EEPROM
Manufacturer
Motorola
Datasheet
MC68HC05B6/D
Rev. 3
HC05
MC68HC05B4
MC68HC705B5
MC68HC05B6
MC68HC05B8
MC68HC05B16
MC68HC705B16
MC68HC05B32
MC68HC705B32
TECHNICAL
DATA

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MC68HC705B5CFN Summary of contents

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HC05 MC68HC05B4 MC68HC705B5 MC68HC05B6 MC68HC05B8 MC68HC05B16 MC68HC705B16 MC68HC05B32 MC68HC705B32 TECHNICAL DATA MC68HC05B6/D Rev. 3 ...

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MODES OF OPERATION AND PIN DESCRIPTIONS SERIAL COMMUNICATIONS INTERFACE PULSE LENGTH D/A CONVERTERS ANALOG TO DIGITAL CONVERTER CPU CORE AND INSTRUCTION SET ELECTRICAL SPECIFICATIONS INTRODUCTION MEMORY AND REGISTERS INPUT/OUTPUT PORTS PROGRAMMABLE TIMER RESETS AND INTERRUPTS MECHANICAL DATA ORDERING INFORMATION APPENDICES ...

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INTRODUCTION 2 MODES OF OPERATION AND PIN DESCRIPTIONS 3 MEMORY AND REGISTERS 4 INPUT/OUTPUT PORTS 5 PROGRAMMABLE TIMER 6 SERIAL COMMUNICATIONS INTERFACE 7 PULSE LENGTH D/A CONVERTERS 8 ANALOG TO DIGITAL CONVERTER 9 RESETS AND INTERRUPTS 10 CPU CORE ...

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... All products are sold on Motorola’s Terms & Conditions of Supply. In ordering a product covered by this document the Customer agrees to be bound by those Terms & Conditions and nothing contained in this document constitutes or forms part of a contract (with the exception of the contents of this Notice). A copy of Motorola’s Terms & Conditions of Supply is available on request. ...

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... ROM areas of the MC68HC05B6 and related devices. As these firmware routines are intended primarily to 7 help Motorola’s engineers test the devices, they may be changed or removed at any time. 8 For this reason, Motorola recommends that the self-check and bootstrap routines are not called from from the user software ...

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... Power consumption during WAIT mode .................................................... 2-9 2.4.3 SLOW mode.................................................................................................... 2-10 2.4.3.1 Miscellaneous register ............................................................................. 2-10 2.5 Pin descriptions ................................................................................................... 2-11 2.5.1 VDD and VSS ................................................................................................. 2-11 2.5.2 IRQ ................................................................................................................. 2-11 2.5.3 RESET ............................................................................................................ 2-11 2.5.4 TCAP1 ............................................................................................................ 2-11 2.5.5 TCAP2 ............................................................................................................ 2-12 2.5.6 TCMP1............................................................................................................ 2-12 2.5.7 TCMP2............................................................................................................ 2-12 2.5.8 OSC1, OSC2 .................................................................................................. 2-12 2.5.8.1 Crystal ....................................................................................................... 2-12 2.5.8.2 Ceramic resonator..................................................................................... 2-12 2.5.8.3 External clock ............................................................................................ 2-13 2.5.9 RDI (Receive data in)...................................................................................... 2-14 2.5.10 TDO (Transmit data out).................................................................................. 2-14 2.5.11 SCLK............................................................................................................... 2-14 MC68HC05B6 Title 1 INTRODUCTION 2 Page Number MOTOROLA i ...

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... Ports A and B ........................................................................................................4-2 4.3 Port C ....................................................................................................................4-3 4.4 Port D ....................................................................................................................4-3 4.5 Port registers .........................................................................................................4-4 4.5.1 Port data registers A and B (PORTA and PORTB) ..........................................4-4 4.5.2 Port data register C (PORTC)..........................................................................4-4 4.5.3 Port data register D (PORTD)..........................................................................4-5 4.5.3.1 A/D status/control register..........................................................................4-5 4.5.4 Data direction registers (DDRA, DDRB and DDRC)........................................4-5 4.6 Other port considerations ......................................................................................4-6 MOTOROLA ii Title 3 4 INPUT/OUTPUT PORTS Page Number MC68HC05B6 ...

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... Receive data in (RDI) ........................................................................................... 6-6 6.8 Start bit detection.................................................................................................. 6-6 6.9 Transmit data out (TDO) ....................................................................................... 6-8 6.10 SCI synchronous transmission ............................................................................. 6-9 6.11 SCI registers ......................................................................................................... 6-10 6.11.1 Serial communications data register (SCDR) ............................................... 6-10 6.11.2 Serial communications control register 1 (SCCR1) ...................................... 6-10 6.11.3 Serial communications control register 2 (SCCR2) ........................................ 6-14 6.11.4 Serial communications status register (SCSR) ............................................. 6-16 MC68HC05B6 Title 5 6 Page Number MOTOROLA iii ...

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... Power-on reset.................................................................................................9-2 9.1.2 Miscellaneous register ...................................................................................9-2 9.1.3 RESET pin .......................................................................................................9-3 9.1.4 Computer operating properly (COP) watchdog reset.......................................9-3 9.1.4.1 COP watchdog during STOP mode ...........................................................9-4 9.1.4.2 COP watchdog during WAIT mode ............................................................9-4 9.1.5 Functions affected by reset..............................................................................9-5 9.2 Interrupts ...............................................................................................................9-6 9.2.1 Interrupt priorities.............................................................................................9-6 9.2.2 Nonmaskable software interrupt (SWI) ............................................................9-6 9.2.3 Maskable hardware interrupts..........................................................................9-7 MOTOROLA iv Title Page Number MC68HC05B6 ...

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... Condition code register (CCR) ...................................................................... 10-2 10.2 Instruction set ..................................................................................................... 10-3 10.2.1 Register/memory Instructions ....................................................................... 10-4 10.2.2 Branch instructions ....................................................................................... 10-4 10.2.3 Bit manipulation instructions ......................................................................... 10-4 10.2.4 Read/modify/write instructions ...................................................................... 10-4 10.2.5 Control instructions ....................................................................................... 10-4 10.2.6 Tables............................................................................................................ 10-4 10.3 Addressing modes .............................................................................................. 10-11 10.3.1 Inherent......................................................................................................... 10-11 10.3.2 Immediate ..................................................................................................... 10-11 10.3.3 Direct............................................................................................................. 10-11 10.3.4 Extended....................................................................................................... 10-12 10.3.5 Indexed, no offset.......................................................................................... 10-12 10.3.6 Indexed, 8-bit offset....................................................................................... 10-12 10.3.7 Indexed, 16-bit offset..................................................................................... 10-12 10.3.8 Relative ......................................................................................................... 10-13 10.3.9 Bit set/clear ................................................................................................... 10-13 10.3.10 Bit test and branch ........................................................................................ 10-13 MC68HC05B6 Title 10 Page Number MOTOROLA v ...

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... MC68HC05B6 mechanical dimensions ...............................................................12-4 12.2.1 52-pin plastic leaded chip carrier (PLCC) .....................................................12-4 12.2.2 64-pin quad flat pack (QFP) .........................................................................12-5 12.2.3 56-pin shrink dual in line package (SDIP)......................................................12-6 ORDERING INFORMATION 13.1 EPROMS .............................................................................................................13-2 13.2 Verification media ................................................................................................13-2 13.3 ROM verification units (RVU)...............................................................................13-2 MOTOROLA vi Title 11 ...............................................................11-4 ..............................................................11-7 ...........................................................................11-9 12 MECHANICAL DATA 13 Page Number MC68HC05B6 ...

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... Bootstrap loader timing diagrams C.5 DC electrical characteristics .................................................................................C-19 C.6 Control timing........................................................................................................C-19 D.1 Self-check routines ..............................................................................................D-1 E.1 EPROM................................................................................................................. E-5 E.1.1 EPROM read operation................................................................................... E-5 E.1.2 EPROM program operation............................................................................. E-5 E.1.3 EPROM/EEPROM/ECLK control register ..................................................... E-6 E.1.4 Mask option register ...................................................................................... E-8 E.1.5 EEPROM options register (OPTR) ................................................................ E-9 E.2 Bootstrap mode .................................................................................................... E-10 E.2.1 Erased EPROM verification ............................................................................ E-13 MC68HC05B6 Title A MC68HC05B4 B MC68HC05B8 C MC68HC705B5 ............................................................C-17 D MC68HC05B16 E MC68HC705B16 Page Number MOTOROLA vii ...

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... EPROM/EEPROM parallel bootstrap..............................................................G-13 G.2.3 Serial RAM loader...........................................................................................G-16 G.2.3.1 Jump to start of RAM ($0051) ...................................................................G-16 G.2.4 Maximum ratings ............................................................................................G-19 G.2.5 Thermal characteristics and power considerations.........................................G-20 G.2.6 DC electrical characteristics G.2.7 A/D converter characteristics G.2.8 Control timing ..........................................................................................G-26 HIGH SPEED OPERATION H.1 DC electrical characteristics ............................................................................... H-2 H.2 A/D converter characteristics .............................................................................. H-3 H.3 Control timing for 5V operation MOTOROLA viii Title ....................................................................... E-23 ..................................................................... E-26 F MC68HC05B32 G MC68HC705B32 ......................................................................G-21 ....................................................................G-24 H ....................................................................... H-4 Page Number MC68HC05B6 ...

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... SCI data clock timing diagram (M=0) .....................................................................6-12 6-10 SCI data clock timing diagram (M=1) .....................................................................6-13 7-1 PLM system block diagram.....................................................................................7-1 7-2 PLM output waveform examples.............................................................................7-2 7-3 PLM clock selection ................................................................................................7-4 8-1 A/D converter block diagram ..................................................................................8-2 8-2 Electrical model of an A/D input pin........................................................................8-6 9-1 Reset timing diagram..............................................................................................9-1 9-2 Watchdog system block diagram ............................................................................9-3 9-3 Interrupt flow chart..................................................................................................9-8 MC68HC05B6 Title Page Number MOTOROLA ix ...

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... EPROM (RAM) serial bootstrap schematic diagram ............................................. C-15 C-8 RAM parallel bootstrap schematic diagram........................................................... C-16 C-9 EPROM parallel bootstrap loader timing diagram ................................................. C-17 C-10 RAM parallel loader timing diagram ..................................................................... C-18 D-1 MC68HC05B16 block diagram .............................................................................. D-2 D-2 Memory map of the MC68HC05B16 ..................................................................... D-3 E-1 MC68HC705B16 block diagram .............................................................................E-2 E-2 Memory map of the MC68HC705B16 ....................................................................E-3 MOTOROLA x Title = 5.5V ................................... 11 3.6V................ 11 3.6V ................................... 11-8 DD Page Number MC68HC05B6 ...

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... Modes of operation flow chart ( ................................................................... G-12 G-5 Timing diagram with handshake ............................................................................ G-14 G-6 Parallel EPROM loader timing diagram ................................................................. G-14 G-7 EPROM parallel bootstrap schematic diagram...................................................... G-15 G-8 RAM load and execute schematic diagram ........................................................... G-17 G-9 Parallel RAM loader timing diagram ...................................................................... G-18 G-10 Equivalent test load ............................................................................................... G-20 G-11 Timer relationship .................................................................................................. G-28 H-1 Timer relationship .................................................................................................. H-4 MC68HC05B6 Title Page Number MOTOROLA xi ...

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... THIS PAGE INTENTIONALLY LEFT BLANK MOTOROLA xii MC68HC05B6 ...

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... Instruction set (2 of 2)...........................................................................................10-9 10-9 M68HC05 opcode map.........................................................................................10-10 11-1 Maximum ratings ..................................................................................................11-1 11-2 Package thermal characteristics...........................................................................11-2 11-3 DC electrical characteristics for 5V operation.......................................................11-3 11-4 DC electrical characteristics for 3.3V operation....................................................11-6 11-5 A/D characteristics for 5V operation .....................................................................11-9 11-6 A/D characteristics for 3.3V operation ..................................................................11-10 11-7 Control timing for 5V operation .............................................................................11-11 11-8 Control timing for 3.3V operation ..........................................................................11-12 MC68HC05B6 LIST OF TABLES Title Page Number MOTOROLA xiii ...

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... Maximum ratings ................................................................................................... G-19 G-7 Package thermal characteristics............................................................................ G-20 G-8 DC electrical characteristics for 5V operation ....................................................... G-21 G-9 DC electrical characteristics for 3.3V operation .................................................... G-23 G-10 A/D characteristics for 5V operation ...................................................................... G-24 G-11 A/D characteristics for 3.3V operation ................................................................... G-25 G-12 Control timing for 5V operation.............................................................................. G-26 G-13 Control timing for operation at 3.3V....................................................................... G-27 H-1 Ordering information.............................................................................................. H-1 H-2 DC electrical characteristics for 5V operation ....................................................... H-2 H-3 A/D characteristics for 5V operation ...................................................................... H-3 MOTOROLA xiv Title Page Number MC68HC05B6 ...

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... INTRODUCTION The MC68HC05B6 microcomputer (MCU member of Motorola’s MC68HC05 family of low-cost single chip microcomputers. This 8-bit MCU contains an on-chip oscillator, CPU, RAM, ROM, EEPROM, A/D converter, pulse length modulated outputs, I/O, serial communications interface, programmable timer system and watchdog. The fully static design allows operation at frequencies down further reduce the already low power consumption to a few micro-amps ...

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... M68HC05BEM emulation module or the M68HC05BEVS evaluation system 1.2 Mask options for the MC68HC05B6 The MC68HC05B6 has three mask options that are programmed during manufacture and must be specified on the order form. • Power-on-reset delay (t MOTOROLA 1 4064 cycles PORL INTRODUCTION MC68HC05B6 ...

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... PLM INTRODUCTION 1 is set to 16 cycles. This PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2/ECLK PC3 PC4 PC5 PC6 PC7 TCMP1 TCMP2 TCAP1 TCAP2 RDI SCLK TDO PLMA D/A PLMB D/A MOTOROLA 1-3 ...

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... THIS PAGE INTENTIONALLY LEFT BLANK MOTOROLA 1-4 INTRODUCTION MC68HC05B6 ...

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... Port C pins PC0–PC3 are monitored for the self-check results (light emitting diodes are shown but other devices could be used), and are interpreted as described in Table 2-2. The self-check mode MC68HC05B6 MODES OF OPERATION AND PIN DESCRIPTIONS 2 PD3 PD4 Mode X X Single chip Self-check 1 0 Serial RAM loader 1 1 Jump to any address 2 MOTOROLA 2-1 ...

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... LED on; ‘1’ indicates LED off MOTOROLA MODES OF OPERATION AND PIN DESCRIPTIONS 2-2 dc (via a 4.7k resistor) to the IRQ pin and 5V dc input (via a 4.7k DD — Functionally exercises ports and D — Counter test for each RAM byte — ...

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... MHz 19 IRQ 23 TCAP2 TCMP2 1 4k7 22 TCAP1 EEPROM tested 32 PB7 4k7 33 PB6 34 PB5 35 PB4 EEPROM not tested 36 PB3 37 PB2 4k7 38 PB1 39 PB0 42 PC7 43 PC6 44 PC5 45 PC4 680 46 PC3 680 47 PC2 680 48 PC1 680 49 VRL PC0 GND +5V 2xV DD BC239 MOTOROLA 2-3 ...

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... SCI is configured for the NRZ data format (idle line, start bit, eight data bits and stop bit). The baud rate is 9600 with a 4 MHz crystal. A program to convert ASCII S-records to the format required by the RAM loader is available from Motorola. If immediate execution is not desired after loading the RAM program possible to hold off execution. This is accomplished by setting the byte count to a value that is greater than the overall length of the loaded data. When the last byte is loaded, the fi ...

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... M 17 OSC2 MHz 19 IRQ PD3 PD4 TCAP1 8 optional VRH 7 VRL 40 VPP1 20 PLMA 21 PLMB 51 SCLK Connect as required for the application 1 TCMP2 23 TCAP2 2 TCMP1 3 PD7 4 PD6 5 PD5 12 PD2 13 PD1 14 PD0 VSS GND +5V 2xV MOTOROLA 2-5 ...

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... Note: These eight resistors are optional; direct connection is possible if pins PA0-PA7, PB0-PB7 and PC0-PC7 are kept in input mode during application. Figure 2-3 MC68HC05B6 ‘jump to any address’ schematic diagram MOTOROLA MODES OF OPERATION AND PIN DESCRIPTIONS 2 VDD ...

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... The timer stops counting; refer to Section 5.6 – The PLM outputs remain at current level; refer to Section 7.2 – The A/D converter is disabled; refer to Section 8.3 – The I-bit in the CCR is cleared MC68HC05B6 MODES OF OPERATION AND PIN DESCRIPTIONS internal cycles delay is provided to give the oscillator time to 2 MOTOROLA 2-7 ...

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... Stop oscillator and all NO IRQ NO external interrupt? YES Wait for time delay to Generate watchdog interrupt (1) Fetch reset vector or (2) Service interrupt: MOTOROLA MODES OF OPERATION AND PIN DESCRIPTIONS 2-8 STOP WAIT Watchdog active? Oscillator active. Timer, SCI, NO A/D, EEPROM clocks active. Processor clocks stopped Clear I-bit clocks. ...

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... WAIT mode important that before entering WAIT mode, the programmer sets the relevant control bits for the individual modules to reflect the desired functionality during WAIT mode. Power consumption may be further reduced by the use of SLOW mode. MC68HC05B6 MODES OF OPERATION AND PIN DESCRIPTIONS 2 MOTOROLA 2-9 ...

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... The SM bit is cleared by external or power-on reset. The SM bit is automatically cleared when entering STOP mode. Note: The bits shown shaded in the above representation are explained individually in the relevant sections of this manual. The complete register plus an explanation of each bit can be found in Section 3.8. MOTOROLA MODES OF OPERATION AND PIN DESCRIPTIONS 2-10 OSC2 pin f ...

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... When a reset condition occurs internally, i.e. from the COP watchdog, the RESET pin provides an active-low open drain output signal that may be used to reset external hardware. 2.5.4 TCAP1 The TCAP1 input controls the input capture 1 function of the on-chip programmable timer system. MC68HC05B6 MODES OF OPERATION AND PIN DESCRIPTIONS 2 MOTOROLA 2-11 ...

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... Figure 2-6(a) is recommended when using either a crystal or a ceramic resonator. Figure 2-6(d) lists the recommended capacitance and feedback resistance values. The manufacturer of the particular ceramic resonator being considered should be consulted for specific information. MOTOROLA MODES OF OPERATION AND PIN DESCRIPTIONS 2-12 ). There is also a software option OP (see Section 11 ...

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... C (b) Crystal equivalent circuit MCU OSC1 External clock (c) External clock source connections Ceramic resonator Unit 2 – 4MHz R (typ OSC1 pF C OSC2 – — Q 1250 OSC2 0 OSC2 NC Unit 4 — MOTOROLA 2-13 ...

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... This 8-bit input only port (D) shares its pins with the A/D converter. When enabled, the A/D converter uses pins PD0/AN0 – PD7/AN7 as its analog inputs. On reset, the A/D converter is disabled which forces the port D pins to be input only port pins (see Section 8.5). MOTOROLA MODES OF OPERATION AND PIN DESCRIPTIONS 2-14 ...

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... ROM The User ROM consists of 5950 bytes of ROM mapped as follows: • 48 bytes of page zero ROM from $0020 to $004F • 5888 bytes of User ROM from $0800 to $1EFF • 14 bytes of User vectors from $1FF2 to $1FFF MC68HC05B6 MEMORY AND REGISTERS 3 3 MOTOROLA 3-1 ...

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... Timer output compare 1& 2 $1FF8–9 Timer input capture 1 & 2 $1FFA–B External IRQ $1FFC–D SWI $1FFE–F Reset/power-on reset Figure 3-1 Memory map of the MC68HC05B6 MOTOROLA 3-2 EEPROM/ECLK control register User vectors (14 bytes) Reserved MEMORY AND REGISTERS Registers $0000 Port A data register ...

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... Once the program/erase EEPROM address has been selected, E1ERA cannot be changed. MC68HC05B6 MEMORY AND REGISTERS ), which removes the need to supply PP1 bit 7 bit 6 bit 5 bit 4 bit 3 bit ECLK E1ERA E1LAT E1PGM 0000 0000 3 State bit 1 bit 0 on reset MOTOROLA 3-3 ...

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... Note: All combinations are not shown in the above table, since the E1PGM and E1ERA bits are cleared when the E1LAT bit is at zero, and will result in a read condition. MOTOROLA 3-4 erase time or t programming time, the E1LAT bit has to be reset ...

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... This condition provides a higher degree of security for the stored data. User programs must be running from the RAM or ROM as the EEPROM will have its address and data buses latched. MC68HC05B6 MEMORY AND REGISTERS 3 MOTOROLA 3-5 ...

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... EEPROM and allows the user to select options in a non-volatile manner. The contents of the OPTR register are loaded into data latches with each power-on or external reset. (1) Options (OPTR) (1) This register is implemented in EEPROM; therefore reset has no effect on the individual bits. MOTOROLA 3-6 . Address bit 7 ...

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... Under normal operating conditions, the charge pump generator is driven by the internal CPU clocks. When the operating frequency is low, e.g. during WAIT mode, the clocking should be done by the internal A/D RC oscillator. The RC oscillator is enabled by setting the ADRC bit of the A/D status/control register at $0009. MC68HC05B6 MEMORY AND REGISTERS programming time in WAIT mode. 3 MOTOROLA 3-7 ...

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... The POR bit is set each time there is a power-on reset. (2) The state of the WDOG bit after reset is dependent on the mask option selected; 1=watchdog enabled, 0=watchdog disabled. (3) This register is implemented in EEPROM; therefore reset has no effect on the individual bits. MOTOROLA 3-8 Table 3-2 Register outline ...

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... INTP INTN INTE SFA Table 3-3 IRQ sensitivity INTN IRQ sensitivity 0 Negative edge and low level sensitive 1 Negative edge only 0 Positive edge only 1 Positive and negative edge sensitive State bit 2 bit 1 bit 0 on reset (2) SFB SM WDOG ?001 000? 3 MOTOROLA 3-9 ...

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... Following a watchdog reset the state of the WDOG bit is as defined by the mask option specified. 1 (set) – Watchdog counter cleared and enabled. 0 (clear) – The watchdog cannot be disabled by software; writing a zero to this bit has no effect. MOTOROLA 3-10 /32). SLOW mode affects all sections of the device, including MEMORY AND REGISTERS /2). OSC MC68HC05B6 ...

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... MCU. During the programmed output state, a read of the data register actually reads the value of the output data latch and not the I/O pin. The operation of the standard port hardware is shown schematically in Figure 4-1. MC68HC05B6 4 INPUT/OUTPUT PORTS 4 MOTOROLA 4-1 ...

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... Reset does not affect the state of the data register, but clears the data direction register, thereby returning all port pins to input mode. Writing a ‘1’ to any DDR bit sets the corresponding port pin to output mode. MOTOROLA 4-2 DDRn DATA ...

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... A/D conversion sequence noise, may be injected on the analog inputs, resulting in reduced accuracy of the A/D. Furthermore, performing MC68HC05B6 bit 7 bit 6 bit 5 bit 4 bit ECLK E1ERA E1LAT E1PGM 0000 0000 INPUT/OUTPUT PORTS State bit 2 bit 1 bit 0 on reset 4 MOTOROLA 4-3 ...

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... In addition, bit 2 of port C is used to output the CPU clock if the ECLK bit in the EEPROM CTL/ECLK register is set (see Section 4.3). The state of the port data registers following reset is not defined. MOTOROLA 4 the port D pins will result in greater ...

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... INPUT/OUTPUT PORTS State bit 2 bit 1 bit 0 on reset PD2 PD1 PD0 Undefined 4 State bit 2 bit 1 bit 0 on reset CH2 CH1 CH0 0000 0000 State bit 2 bit 1 bit 0 on reset 0000 0000 0000 0000 0000 0000 MOTOROLA 4-5 ...

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... This would cause the ‘open-drain’ pin not to output a ‘zero’ when desired. Note: ‘Open-drain’ outputs should not be pulled above V Read buffer output (a) Data direction register bit DDRn (b) V VDD Px0 MOTOROLA 4-6 A DDRn Normal operation – ...

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... The prescaler gives the timer a resolution the inter nal bus cloc MHz. The counter is incremented during the low portion of the internal bus clock. Software can read the counter at any time without affecting its value. MC68HC05B6 5 PROGRAMMABLE TIMER 5 MOTOROLA 5-1 ...

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... ICF1 OCF1 TOF ICF2 Interrupt circuit Input capture Output compare interrupt $1FF8,9 Figure 5-1 16-bit programmable timer block diagram MOTOROLA 5-2 Internal bus Internal 8-bit processor buffer clock Low High Low byte byte byte 4 16-bit $0018 $001E ...

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... PLM results will also be affected while resetting the counter. MC68HC05B6 bit 7 bit 6 bit 5 bit 4 bit 3 bit 7 bit 6 bit 5 bit 4 bit 3 PROGRAMMABLE TIMER State bit 2 bit 1 bit 0 on reset 1111 1111 1111 1100 State bit 2 bit 1 bit 0 on reset 1111 1111 1111 1100 5 MOTOROLA 5-3 ...

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... Interrupt disabled. TOIE — Timer overflow interrupt enable If this bit is set, a timer interrupt is enabled whenever the TOF status flag (in the timer status register) is set. 1 (set) – Interrupt enabled. 0 (clear) – Interrupt disabled. MOTOROLA 5-4 Address bit 7 bit 6 bit 5 bit 4 $0012 ICIE ...

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... TCMP1 pin. When clear, it will be a low level which will appear on the TCMP1 pin. 1 (set) – A high output level will appear on the TCMP1 pin. 0 (clear) – A low output level will appear on the TCMP1 pin. MC68HC05B6 PROGRAMMABLE TIMER 5 MOTOROLA 5-5 ...

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... The timer status register is read or written when TOF is set, and 2 The LSB of the free-running counter is read, but not for the purpose of servicing the flag. Reading the alternate counter register instead of the counter register will avoid this potential problem. MOTOROLA 5-6 Address bit 7 bit 6 ...

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... MC68HC05B6 bit 7 bit 6 bit 5 bit 4 bit 3 PROGRAMMABLE TIMER 5 State bit 2 bit 1 bit 0 on reset Undefined Undefined MOTOROLA 5-7 ...

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... A read of the input capture register 2 LSB ($1C) does not inhibit the free-running counter transfer since the two actions occur on opposite edges of the internal bus clock. Reset does not affect the contents of the input capture 2 register, except when exiting STOP mode (see Section 5.6). MOTOROLA 5-8 Address bit 7 bit 6 ...

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... Write to output compare high 1 to inhibit further compares; – Read the timer status register to clear OCF1 (if set); – Write to output compare low 1 to enable the output compare 1 function. MC68HC05B6 bit 7 bit 6 bit 5 bit 4 bit 3 PROGRAMMABLE TIMER 5 State bit 2 bit 1 bit 0 on reset Undefined Undefined MOTOROLA 5-9 ...

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... The following procedure is recommended: – Write to output compare high 2 to inhibit further compares; – Read the timer status register to clear OCF2 (if set); – Write to output compare low 2 to enable the output compare 2 function. MOTOROLA 5-10 Address bit 7 ...

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... Pulse length modulation A (PLMA) $000A Address Pulse length modulation B (PLMB) $000B MC68HC05B6 bit 7 bit 6 bit 5 bit 4 bit 3 bit 7 bit 6 bit 5 bit 4 bit 3 PROGRAMMABLE TIMER 5 State bit 2 bit 1 bit 0 on reset 0000 0000 State bit 2 bit 1 bit 0 on reset 0000 0000 MOTOROLA 5-11 ...

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... The relationships between the internal clock signals, the counter contents and the status of the flag bits are shown in the following figures. It should be noted that the signals labelled ‘internal’ (processor clock, timer clocks and reset) are not available to the user. MOTOROLA 5-12 PROGRAMMABLE TIMER ...

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... If the input edge occurs in the shaded area from one timer state T10 to the next timer state T10, then the input capture flag will be set during the next T11 state. Figure 5-3 Timer state timing diagram for input capture MC68HC05B6 $FFFC $FFFD $FFFE $F123 $F124 $F125 $???? $F124 PROGRAMMABLE TIMER $FFFF 5 $F126 MOTOROLA 5-13 ...

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... The timer overflow flag is set at timer state T11 (transition of counter from $FFFF to $0000 cleared by a read of the timer status register during the internal processor clock high time, followed by a read of the counter low register. Figure 5-5 Timer state timing diagram for timer overflow MOTOROLA 5-14 $F456 $F457 ...

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... Software selectable word length (eight or nine bits) • Separate transmitter and receiver enable bits • Capable of being interrupt driven • Transmitter clocks available without altering the regular transmitter or receiver functions • Four separate enable bits for interrupt control MC68HC05B6 SERIAL COMMUNICATIONS INTERFACE 6 6 MOTOROLA 6-1 ...

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... Note: The serial communications data register (SCI SCDR) is controlled by the internal R/W signal the transmit data register when written to and the receive data register when read. Figure 6-1 Serial communications interface block diagram MOTOROLA 6-2 Internal bus SCI interrupt + & & ...

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... TC bit will also be set. This will also generate an interrupt if the transmission complete interrupt enable bit (TCIE) is set. If the transmitter is disabled during a transmission, the character being transmitted will be completed before the transmitter gives up control of the TDO pin. MC68HC05B6 SERIAL COMMUNICATIONS INTERFACE 6 MOTOROLA 6-3 ...

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... There is a fixed rate divide-by-16 before the transmitter to compensate for the inherent divide-by-16 of the receiver (sampling). This means that by loading the same value for both the transmitter and receiver baud rate selector, the same baud rates can be obtained. MOTOROLA 6-4 Internal processor clock SCP0 – ...

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... Although RWU may be cleared by a software write to SCCR2, it would be unusual to do so. Normally RWU is set by software and is cleared automatically in hardware by one of the two methods described below. MC68HC05B6 SERIAL COMMUNICATIONS INTERFACE Control bit M selects bit data Start Figure 6-3 Data format 6 0 Stop Start MOTOROLA 6-5 ...

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... A noise flag is set if one of the three verification samples detect a logic one, thus a valid start bit could be assumed with a set noise flag present. MOTOROLA 6-6 SERIAL COMMUNICATIONS INTERFACE ...

Page 75

... Start Start Start edge qualifiers verification samples Start Noise Start Samples 8RT 9RT 10RT 16RT 1RT 6RT 7RT 8RT Next bit MOTOROLA 6-7 ...

Page 76

... Data format is as discussed in Section 6.5 and shown in Figure 6-3. The transmitter generates a bit time by using a derivative of the RT clock, thus producing a transmission rate equal to 1/16th that of the receiver sample clock (assuming the same baud rate is selected for both the receiver and transmitter). MOTOROLA 6-8 Expected stop Artificial edge Data samples a) Case 1: receive line low during artifi ...

Page 77

... These bits should not be changed while the transmitter is enabled. RDI TDO SCLK MC68HC05B6 Output port Figure 6-8 SCI example of synchronous and asynchronous transmission MC68HC05B6 SERIAL COMMUNICATIONS INTERFACE Data out Asynchronous (e.g. Modem) Data in Data in Synchronous Clock (e.g. shift register, display driver, etc.) Enable 6 MOTOROLA 6-9 ...

Page 78

... Serial communications control register 1 (SCCR1) SCI control 1 (SCCR1) The SCI control register 1 (SCCR1) contains control bits related to the nine data bit character format, the receiver wake-up feature and the options to output the transmitter clocks for synchronous transmissions. MOTOROLA 6-10 Address bit 7 bit 6 ...

Page 79

... WAKE — Wake-up mode select This bit allows the user to select the method for receiver wake-up. The WAKE bit can be read or written to any time. See Table 6-1. 1 (set) – Wake-up on address mark. 0 (clear) – Wake-up on idle line. MC68HC05B6 SERIAL COMMUNICATIONS INTERFACE Method of receiver wake-up 6 MOTOROLA 6-11 ...

Page 80

... This bit should not be manipulated while the transmitter is enabled. Idle or preceding transmission clock (CPOL = 0, CPHA = 0) clock (CPOL = 0, CPHA = 1) clock (CPOL = 1, CPHA = 0) clock (CPOL = 1, CPHA = 1) data Figure 6-9 SCI data clock timing diagram (M=0) MOTOROLA 6- data bits) Start Start LSB * ...

Page 81

... Data format 8 bit 8 bit 9 bit 9 bit MC68HC05B6 SERIAL COMMUNICATIONS INTERFACE data bits MSB * LBCL bit controls last data clock Number of clocks on M-bit LBCL bit SCLK pin Idle or next transmission Stop * * * * 8 Stop 6 MOTOROLA 6-13 ...

Page 82

... After this latest transmission, and provided the TDRE bit is set (no new data to transmit), the line remains idle (driven high while TE = 1); otherwise, normal transmission occurs. This function allows the user to neatly terminate a transmission sequence. MOTOROLA 6-14 Address bit 7 ...

Page 83

... If SBK remains set, the transmitter will continually send whole blocks of zeros (sets 11) until cleared. At the completion of the break code, the transmitter sends at least one high bit to guarantee recognition of a valid start bit. MC68HC05B6 SERIAL COMMUNICATIONS INTERFACE 6 MOTOROLA 6-15 ...

Page 84

... IDLE set) followed by a read of the serial communications data register. Once cleared, IDLE will not be set again until after RDRF has been set, (i.e. until after the line has been active and becomes idle again). MOTOROLA 6-16 Address ...

Page 85

... RDRF bit but does not get set in the case of an overrun (OR). The framing error flag inhibits further transfer of data into the receive data register until it is cleared. The FE bit is cleared when the serial communications status register is accessed (with FE set) followed by a read of the serial communications data register. MC68HC05B6 SERIAL COMMUNICATIONS INTERFACE 6 MOTOROLA 6-17 ...

Page 86

... SCI receiver, and by the SCT0–SCT2 bits for the transmitter. 6 SCT2, SCT1,SCT0 — SCI rate select bits (transmitter) These three read/write bits select the baud rates for the transmitter. The prescaler output is divided by the factors shown in Table 6-4. Table 6-4 Second prescaler stage (transmitter) MOTOROLA 6-18 Address bit 7 bit 6 bit 5 ...

Page 87

... These are effectively the highest baud rates which can be achieved using a given crystal. MC68HC05B6 SERIAL COMMUNICATIONS INTERFACE Receiver SCR1 SCR0 division ratio (NR 128 f osc baudTx = --------------------------------- - osc baudRx = ---------------------------------- - MOTOROLA 6-19 ...

Page 88

... Note: The examples shown above do not apply when the part is operating in slow mode (see Section 2.4.3). MOTOROLA 6-20 Table 6-6 SCI baud rate selection NP NT/NR 4.194304 131072 65536 32768 1 1 ...

Page 89

... If required, the SCI system can be disabled prior to entering WAIT mode by writing a zero to the transmitter and receiver enable bits in the serial communication control register 2 at $000F. This action will result in a reduction of power consumption during WAIT mode. MC68HC05B6 SERIAL COMMUNICATIONS INTERFACE 6 MOTOROLA 6-21 ...

Page 90

... THIS PAGE INTENTIONALLY LEFT BLANK MOTOROLA 6-22 SERIAL COMMUNICATIONS INTERFACE MC68HC05B6 ...

Page 91

... MC68HC05B6 PULSE LENGTH D/A CONVERTERS 7 Data bus 8 8 PLMA PLMB register register ‘B’ register buffer buffer ‘A’ ‘B’ comparator Zero detector 8 8 ‘A’ ‘B’ multiplexer 16 16 Timer bus 7 R PLMB D/A Latch pin S SFB bit From timer MOTOROLA 7-1 ...

Page 92

... PLM during the period immediately following an update of the PLM D/A registers). This feature is achieved by double buffering of the PLM D/A registers. Examples of PWM output waveforms are shown in Figure 7-2. $00 $01 T 128 T $80 $ CPU clocks in fast mode and 64 CPU clocks in slow mode MOTOROLA 7-2 Address bit 7 bit 6 bit 5 bit 4 $000A $000B 256 T ...

Page 93

... SLOW mode affects all sections of the device, including OSC SCI, A/D and timer. 0 (clear) – The system runs at normal bus speed (f MC68HC05B6 PULSE LENGTH D/A CONVERTERS bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 POR INTP INTN INTE SFA SFB /2). OSC State bit 1 bit 0 on reset SM WDOG ?001 000? 7 MOTOROLA 7-3 ...

Page 94

... On entering STOP mode, the PLM outputs remain at their particular level. When STOP mode is exited by an interrupt, the PLM systems resume regular operation. If STOP mode is exited by power-on or external reset the registers values are forced to $00. 7.4 PLM during WAIT mode The PLM system is not affected by WAIT mode and continues normal operation. MOTOROLA 7-4 Bus Timer frequency (f ) ...

Page 95

... There are eleven options that can be selected by the multiplexer; AN0–AN7, VRH, (VRH+VRL)/2 or VRL. Selection is done via the CHx bits in the ADSTAT register (see Section 8.2.3). AN0–AN7 are the only input points for A/D conversion operations; the others are reference points that can be used for test purposes. MC68HC05B6 ANALOG TO DIGITAL CONVERTER MOTOROLA 8-1 ...

Page 96

... Warning: Any write to the A/D status/control register will abort the current conversion, reset the conversion complete flag and start a new conversion on the selected channel. At power-on or external reset, both the ADRC and ADON bits are cleared; thus the A/D is disabled. MOTOROLA 8-2 8-bit capacitive DAC ...

Page 97

... ANALOG TO DIGITAL CONVERTER bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 PD7 PD6 PD5 PD4 PD3 PD2 DD bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 State bit 1 bit 0 on reset PD1 PD0 Undefined the pins will SS 8 State bit 1 bit 0 on reset 0000 0000 MOTOROLA 8-3 ...

Page 98

... When the A/D RC oscillator is turned on, it takes a time t Table 11-8). During this time A/D conversion results may be inaccurate. Note: If the MCU bus clock falls below 1MHz, the A/D RC oscillator should be switched on. Power-on or external reset clears the ADRC bit. ADRC MOTOROLA 8-4 Address bit 7 bit 6 bit 5 bit 4 $0009 COCO ADRC ADON 0 ...

Page 99

... AN4 AN5 AN6 AN7 VRH pin (high (VRH + VRL VRL pin (low VRL pin (low VRL pin (low VRL pin (low VRL pin (low VRL pin (low) 8 MOTOROLA 8-5 ...

Page 100

... The equivalent analog input during sampling low-pass filter with a minimum resistance and a capacitance of at least 10pF. It should be noted that these are typical values measured at room temperature. 8 Analog input pin Note: Figure 8-2 Electrical model of an A/D input pin MOTOROLA 8-6 Input protection device + ~20V - ~0.7V < 2pF 400 nA junction leakage The analog switch is closed during the 12 cycle sample time only ...

Page 101

... Figure 9-1 Reset timing diagram MC68HC05B6 RESETS AND INTERRUPTS 9 t CYC t ( (External hardware reset) RL DOGL New 1FFE 1FFF 1FFE 1FFE PC Reset sequence New New Op PCH PCL code Program execution begins 9 New 1FFE 1FFE 1FFF PC New New Op PCH PCL code Program execution begins MOTOROLA 9-1 ...

Page 102

... A power-on reset has occurred. 0 (clear) – No power-on reset has occurred. Note: The bits shown shaded in the above representation are explained individually in the relevant sections of this manual. The complete register plus an explanation of each bit can be found in Section 3.8. MOTOROLA 9-2 PORL Address bit 7 bit 6 bit 5 ...

Page 103

... Section 1.2 can be enabled by software by writing a ‘1’ to the WDOG bit in the miscellaneous register at $000C (see Section 9.1.2). Once enabled, the watchdog system MC68HC05B6 RESETS AND INTERRUPTS ). An internal Schmitt Trigger CYC Power-on S Latch R 8 watchdog counter Schmitt Input Control logic trigger protection Reset pin 9 MOTOROLA 9-3 ...

Page 104

... Watchdog enabled — the watchdog counter will continue to operate during WAIT mode and a reset will occur after time t Watchdog disabled — on entering WAIT mode, the watchdog counter system is reset and disabled. On exiting WAIT mode the counter resumes normal operation. MOTOROLA 9-4 since the last clear or since the enable of the watchdog DOG cycles start-up delay ...

Page 105

... Described action takes place – = Described action does not take place MOTOROLA 9 9-5 ...

Page 106

... The software interrupt (SWI executable instruction and a nonmaskable interrupt executed regardless of the state of the I-bit in the CCR. If the I-bit is zero (interrupts enabled), SWI is executed after interrupts that were pending when the SWI was fetched, but before interrupts MOTOROLA 9-6 RESETS AND INTERRUPTS ...

Page 107

... Register Flags Vector address — — $1FFE, $1FFF — — $1FFC, $1FFD — — $1FFA, $1FFB TSR ICF1, ICF2 $1FF8, $1FF9 TSR OCF1, OCF2 $1FF6, $1FF7 TSR TOF $1FF4, $1FF5 TDRE, TC, OR, SCSR $1FF2, $1FF3 RDRF, IDLE Priority highest lowest 9 MOTOROLA 9-7 ...

Page 108

... Is I-bit set? IRQ external interrupt? Timer internal interrupt? 9 SCI internal interrupt? Fetch next instruction Execute instruction MOTOROLA 9-8 Clear IRQ request latch Load PC from: IRQ: Timer IC: $1FF8-$1FF9 Timer OC: $1FF6-$1FF7 Timer OVF:$1FF4-$1FF5 SCI: Complete interrupt routine and execute RTI Figure 9-3 Interrupt fl ...

Page 109

... POR INTP INTN INTE SFA Table 9-3 IRQ sensitivity INTN IRQ sensitivity 0 Negative edge and low level sensitive 1 Negative edge only 0 Positive edge only 1 Positive and negative edge sensitive State bit 2 bit 1 bit 0 on reset SFB SM WDOG ?001 000? 9 MOTOROLA 9-9 ...

Page 110

... The general sequence for clearing an interrupt is a software sequence of accessing the serial communications status register while the flag is set followed by a read or write of an associated register. Refer to Section 6 for a description of the SCI system and its interrupts. MOTOROLA 9-10 and serviced as soon as the I-bit is cleared. ...

Page 111

... The WAIT instruction causes all processor clocks to stop, but leaves the timer clocks running. This ‘rest’ state of the processor can be cleared by reset, an external interrupt (IRQ), a timer interrupt or an SCI interrupt. There are no special WAIT vectors for these individual interrupts. MC68HC05B6 RESETS AND INTERRUPTS 9 MOTOROLA 9-11 ...

Page 112

... THIS PAGE INTENTIONALLY LEFT BLANK 9 MOTOROLA 9-12 RESETS AND INTERRUPTS MC68HC05B6 ...

Page 113

... Index register 7 0 Program counter 7 0 Stack pointer Condition code register Carry / borrow Zero Negative Interrupt mask Half carry Stack 0 Condition code register Accumulator Index register Program counter high Program counter low 10 Decreasing memory address MOTOROLA 10-1 ...

Page 114

... The CCR is a 5-bit register in which four bits are used to indicate the results of the instruction just executed, and the fifth bit indicates whether interrupts are masked. These bits can be individually tested by a program, and specific actions can be taken as a result of their state. Each bit is explained in the following paragraphs. MOTOROLA 10-2 CPU CORE AND INSTRUCTION SET MC68HC05B6 ...

Page 115

... This instruction allows unsigned multiplication of the contents of the accumulator (A) and the index register (X). The high-order product is then stored in the index register and the low-order product is stored in the accumulator. A detailed definition of the MUL instruction is shown in Table 10-1. MC68HC05B6 CPU CORE AND INSTRUCTION SET 10 MOTOROLA 10-3 ...

Page 116

... Tables for all the instruction types listed above follow. In addition there is a complete alphabetical listing of all the instructions (see Table 10-7 and Table 10-8), and an opcode map for the instruction set of the M68HC05 MCU family (see Table 10-9). MOTOROLA 10-4 CPU CORE AND INSTRUCTION SET ...

Page 117

... MOTOROLA 10-5 ...

Page 118

... Branch if interrupt mask bit is set Branch if interrupt line is low Branch if interrupt line is high Branch to subroutine 10 Function Branch if bit n is set Branch if bit n is clear Set bit n Clear bit n MOTOROLA 10-6 Table 10-3 Branch instructions Relative addressing mode Function Mnemonic Opcode # Bytes # Cycles BRA BRN BHI ...

Page 119

... MOTOROLA 10-7 ...

Page 120

... BSR CLC CLI CLR CMP Address mode abbreviations BSC Bit set/clear BTB Bit test & branch DIR Direct EXT Extended INH Inherent MOTOROLA 10-8 Table 10-7 Instruction set ( Addressing modes IMM DIR EXT REL IX IX1 IX2 IMM Immediate H Half carry (from bit 3) ...

Page 121

... Tested and set if true, cleared otherwise • Not affected ? Load CCR from stack 0 Cleared 1 Set MOTOROLA 10-9 ...

Page 122

... MOTOROLA 10-10 CPU CORE AND INSTRUCTION SET MC68HC05B6 ...

Page 123

... In the direct addressing mode, the effective address of the argument is contained in a single byte following the opcode byte. Direct addressing allows the user to directly address the lowest 256 bytes in memory with a single two-byte instruction. Address bus high MC68HC05B6 CPU CORE AND INSTRUCTION SET HMOS/M146805 CMOS EA = PC+ (PC+1); PC PC+2 0; Address bus low (PC+1) Family Microcomputer/ 10 MOTOROLA 10-11 ...

Page 124

... This address mode can be used in a manner similar to indexed, 8-bit offset except that this three-byte instruction allows tables to be anywhere in memory. As with direct and extended addressing, the Motorola assembler determines the shortest form of indexed addressing. ...

Page 125

... Otherwise, control proceeds to the next instruction. The span of relative addressing is from –126 to +129 from the opcode address. The programmer need not calculate the offset when using the Motorola assembler, since it calculates the proper offset and checks to see that it is within the span of the branch. ...

Page 126

... THIS PAGE INTENTIONALLY LEFT BLANK 10 MOTOROLA 10-14 CPU CORE AND INSTRUCTION SET MC68HC05B6 ...

Page 127

... V MC68HC05B6 ELECTRICAL SPECIFICATIONS 11 Symbol Value V – 0 – – +70 –40 to +85 –40 to +125 T – +150 STG ( Unit MOTOROLA 11-1 ...

Page 128

... A by solving the above equations. The package thermal characteristics are shown in Table 11-2. Voltage Pins 4.5V PA0–7, PB0–7, PC0–7 3.0V PA0–7, PB0–7, PC0–7 MOTOROLA 11-2 Table 11-2 Package thermal characteristics Characteristics Symbol degrees Celsius can be obtained from the following ...

Page 129

... (2) Max Unit — — V — 0.1 – 0.4 — V – 0.4 — 0.1 0.4 V 0.4 1 — — 0.5 1 — — — 0 0 0.2 1 — — — TBD pF 22 TBD pF measured with DD MOTOROLA 11-3 ...

Page 130

... Figure 11-2 Run I 1.2 1 0.8 I (mA) 0.6 DD 0.4 0 Figure 11-3 Run I 11 2.5 2 1.5 I (mA 0 Figure 11-4 Wait I MOTOROLA 11-4 0.5 1 1.5 2 2.5 Internal operating frequency (MHz) vs internal operating frequency (4.5V, 5.5V) DD 0.5 1 1.5 2 2.5 Internal operating frequency (MHz) ( internal operating frequency (4.5V, 5.5V) DD 0.5 1 1.5 2 2.5 Internal operating frequency (MHz) vs internal operating frequency (4.5V, 5.5V) DD ELECTRICAL SPECIFICATIONS 5 ...

Page 131

... Internal operating frequency (MHz) Figure 11 mode vs internal operating frequency MC68HC05B6 ELECTRICAL SPECIFICATIONS 1.5 2 2.5 3 3.5 Internal operating frequency (MHz) 1 1.5 2 2.5 vs frequency for A/D, SCI systems active, VDD = 5.5V 1.5 2 2.5 3 3.5 5.5V 4.5V 4 A/D + SCI A/D SCI 3 11 Run I DD Wait I DD Run I ( Wait I ( 5.5V DD MOTOROLA 11-5 ...

Page 132

... Typical values are at mid point of voltage range and at 25C only. (3) RUN and WAIT I DD from rail loads; maximum load on outputs 50pF (20pF on OSC2). STOP /WAIT I : all ports configured as inputs OSC1 = WAIT I is affected linearly by the OSC2 capacitance. DD MOTOROLA 11-6 = 0Vdc (1) Symbol Min ...

Page 133

... Figure 11-8 Run I 0.6 0.5 0.4 I (mA) DD 0.3 0.2 0 0.5 Internal operating frequency (MHz) Figure 11-9 Run I DD 1.2 1 0.8 I (mA) DD 0.6 0.4 0 0.5 Internal operating frequency (MHz) Figure 11-10 Wait I MC68HC05B6 ELECTRICAL SPECIFICATIONS 1 1 internal operating frequency (3 V, 3.6V 1 internal operating frequency (3V,3.6V internal operating frequency (3V, 3.6V) DD 3.6V 3.0V 2.5 3.6V 3.0V 2.5 11 3.6V 3.0V 2.5 MOTOROLA 11-7 ...

Page 134

... DD 0.3 0.2 0 Figure 11-12 Increase 1.5 I (mA 0 Figure 11-13 I MOTOROLA 11-8 0.5 1 1.5 2 Internal operating frequency (MHz) ( internal operating frequency (3V, 3.6V) DD 0.5 1 1.5 2 Internal operating frequency (MHz) vs frequency for A/D, SCI systems active 0.5 1 1.5 Internal operating frequency (MHz) vs mode vs internal operating frequency ELECTRICAL SPECIFICATIONS 3 ...

Page 135

... (2) Max Unit 8 — Bit — 0.5 LSB — 0.5 LSB — 1 LSB 0 – 0 — V — CYC — GUARANTEED 00 — Hex — FF Hex — CYC — — — MOTOROLA 11-9 ...

Page 136

... Source impedances greater than 10k will adversely affect internal charging time during input sampling. (2) The external system error caused by input leakage current is approximately equal to the product of R source and input current. Input current to A/D channel will be dependent on external source impedance (see Figure 8-2). 11 MOTOROLA 11- ...

Page 137

... Max Unit 4.2 MHz 4.2 MHz 2.1 MHz 2.1 MHz — ns 100 ms 100 ms 100 ms 500 s — t CYC t CYC — t CYC — — t CYC 7168 t CYC — ms — ms — ms — ms — ms — ms — t CYC — ns — t CYC — — t CYC — ns MOTOROLA 11-11 ...

Page 138

... Since a 2-bit prescaler in the timer must count four external cycles (t factor in determining the timer resolution. (3) The minimum period t execute the capture interrupt service routine plus 24 t (4) The minimum period t execute the interrupt service routine plus 21 t MOTOROLA 11-12 Table 11-8 Control timing for 3.3V operation = 0 Vdc ...

Page 139

... TLTL External signal (TCAP1, TCAP2) Figure 11-14 Timer relationship MC68HC05B6 ELECTRICAL SPECIFICATIONS MOTOROLA 11 11-13 ...

Page 140

... THIS PAGE INTENTIONALLY LEFT BLANK 11 MOTOROLA 11-14 ELECTRICAL SPECIFICATIONS MC68HC05B6 ...

Page 141

... MC68HC05B6 pin configurations 12.1.1 52-pin plastic leaded chip carrier (PLCC) VRH 8 PD4/AN4 9 VDD 10 PD3/AN3 11 PD2/AN2 12 PD1/AN1 13 PD0/AN0 OSC1 16 OSC2 17 RESET 18 IRQ 19 PLMA 20 Figure 12-1 52-pin PLCC pinout MC68HC05B6 12 PC3 46 PC4 45 PC5 44 PC6 43 PC7 42 VSS 41 VPP1 40 PB0 39 PB1 38 PB2 37 PB3 36 PB4 35 PB5 34 MECHANICAL DATA 12 MOTOROLA 12-1 ...

Page 142

... PC1 PC0 RDI SCLK TDO TCMP2 TCMP1 PD7/AN7 PD6/AN6 PD5/AN5 NC 12 MOTOROLA 12 Device Pin 27 Pin 57 MC68HC05B4 NC NC MC68HC05B6 MC68HC05B8 NC VPP1 MC68HC05B16 MC68HC05B32 MC68HC705B5 Not available in this package ...

Page 143

... NC PB0 PB1 18 39 PB2 19 38 PB3 20 37 PB4 21 36 PB5 PB6 24 33 PB7 PA0 PA1 27 30 PA2 28 29 PA3 Device Pin 16 Pin VPP1 NC VPP1 NC VPP1 NC VPP1 VPP NC VPP6 VPP1 MECHANICAL DATA 12 MOTOROLA 12-3 ...

Page 144

... Dim. Min. Max. A 19.94 20.19 B 19.94 20.19 C 4.20 4. 2.29 2.79 F 0.33 0.48 G 1.27 BSC H 0.66 0.81 J 0.51 — K 0.64 — R 19.05 19.20 Figure 12-4 52-pin PLCC mechanical dimensions MOTOROLA 12 –P L – –N– Y BRK –M– Case No. 778-02 52 Lead PLCC w/o pedestal W pin 1 –P– 0.18 0. – – ...

Page 145

... Datum -H- Plane M Notes MECHANICAL DATA Detail “A” Base D Metal Section B–B 0. – Dim. Min. Max 0.130 0.170 P 0.40 BSC 0.13 0.30 S 16.20 16.60 T 0.20 REF 16.20 16.60 W 0.042 NOM X 1.10 1.30 MOTOROLA 12-5 ...

Page 146

... B 13.72 14.22 C 3.94 5.08 D 0.36 0.56 E 0.89 BSC F 0.81 1.17 G 1.778 BSC Figure 12-6 56-pin SDIP mechanical dimensions 12 MOTOROLA 12 Case No. 859- lead SDIP Notes 1. Due to space limitations, this case shall be represented by a general case outline, rather than one showing all the leads. ...

Page 147

... This section describes the information needed to order the MC68HC05B6 and other family members. To initiate a ROM pattern for the MCU necessary to contact your local field service office, local sales person or Motorola representative. Please note that you will need to supply details such as: mask option selections; temperature range; oscillator frequency; package type; electrical test requirements ...

Page 148

... ROM code will be generated and returned with a listing verification form. The listing should be thoroughly checked and the verification form completed, signed and returned to Motorola. The signed verification form constitutes the contractual agreement for creation of the custom mask. If desired, Motorola will program blank EPROMs (supplied by the customer) from the data fi ...

Page 149

... No EEPROM Section 3.5, ‘EEPROM’, therefore, does not apply to the MC68HC05B4, and the register at address $07 only allows the user to select whether or not the ECLK should appear at PC2, using bit 3 of $07. All other bits of this register read as ‘0’. MC68HC05B6 A MC68HC05B4 14 MOTOROLA A-1 ...

Page 150

... OSC2 OSC1 VDD VSS PD0/AN0 PD1/AN1 PD2/AN2 PD3/AN3 PD4/AN4 PD5/AN5 PD6/AN6 PD7/AN7 VRH VRL PLMA D/A PLMB D/A 14 MOTOROLA A-2 COP watchdog 4158 bytes Oscillator User ROM (including 14 bytes User vectors) M68HC05 CPU 432 bytes self check ROM 176 bytes RAM 8-bit A/D converter ...

Page 151

... Capture high register 1 $0015 Capture low register 1 $0016 Compare high register 1 $0017 Compare low register 1 $0018 Counter high register Counter low register $0019 $001A $001B Capture high register 2 $001C Capture low register 2 $001D $001E Compare high register 2 Compare low register 2 $001F 14 MOTOROLA A-3 ...

Page 152

... Output compare high 2 Output compare low 2 (1) This bit is set each time there is a power-on reset. (2) The state of the WDOG bit after reset is dependent upon the mask option selected; 1=watchdog enabled, 0=watchdog disabled. 14 MOTOROLA A-4 Table A-1 Register outline Address bit 7 bit 6 bit 5 ...

Page 153

... MC68HC05B8 The MC68HC05B8 is a device similar to the MC68HC05B6, but with an increased ROM size of 7.25 kbytes. The entire MC68HC05B6 data sheet applies to the MC68HC05B8, with the exceptions outlined in this appendix. Features • 7230 bytes User ROM (including 14 bytes User vectors) MC68HC05B6 B MC68HC05B8 14 MOTOROLA B-1 ...

Page 154

... IRQ OSC2 OSC1 VDD VSS PD0/AN0 PD1/AN1 PD2/AN2 PD3/AN3 PD4/AN4 PD5/AN5 PD6/AN6 PD7/AN7 VRH VRL 14 MOTOROLA B-2 256 bytes EEPROM 7230 bytes User ROM Charge pump (including 14 bytes User vectors) COP watchdog Oscillator 432 bytes self check ROM M68HC05 CPU 176 bytes ...

Page 155

... Capture low register 1 $0016 Compare high register 1 $0017 Compare low register 1 $0018 Counter high register Counter low register $0019 $001A $001B Capture high register 2 $001C Capture low register 2 $001D $001E Compare high register 2 Compare low register 2 $001F Options register $0100 14 MOTOROLA B-3 ...

Page 156

... This bit is set each time there is a power-on reset. (2) The state of the WDOG bit after reset is dependent upon the mask option selected; 1=w atchdog enabled, 0=watchdog disabled. (3) This register is implemented in EEPROM; therefore reset has no effect on the individual bits. 14 MOTOROLA B-4 Table B-1 Register outline Address bit 7 ...

Page 157

... Simultaneous programming bytes • Data protection for program code • Optional pull-down resistors on port B and port C • Additional temperature range available; -40 to +105C • MC68HC05B6 mask options are programmable using control bits held in the options register MC68HC05B6 C MC68HC705B5 14 MOTOROLA C-1 ...

Page 158

... RESET IRQ OSC2 OSC1 VDD VSS PD0/AN0 PD1/AN1 PD2/AN2 PD3/AN3 PD4/AN4 PD5/AN5 PD6/AN6 PD7/AN7 VRH VRL 14 MOTOROLA C-2 256 bytes EPROM1 6206 bytes 496 bytes EPROM bootstrap ROM (including 14 bytes User vectors) COP watchdog Oscillator 176 bytes RAM M68HC05 CPU 16-bit ...

Page 159

... Capture low register 1 $0016 Compare high register 1 $0017 Compare low register 1 $0018 Counter high register Counter low register $0019 $001A $001B Capture high register 2 $001C Capture low register 2 $001D $001E Compare high register 2 Compare low register 2 $001F Options register $1EFE 14 MOTOROLA C-3 ...

Page 160

... This bit is set each time the device is powered-on. (3) The state of the WDOG bit after reset depends on the mask option selected; ‘1’ = watchdog enabled and ‘0’ = watchdog disabled. (4) Because this register is implemented in EPROM, reset has no effect on the state of the individual bits. 14 MOTOROLA C-4 Table C-1 Register outline Address bit 7 ...

Page 161

... When the part becomes a PROM, only the cumulative programming of bits to logic 1 is possible if multiple programming is made on the same byte. To allow simultaneous programming bytes, they must be in the same group of addresses which share the same most significant address bits; only the two LSBs can change. MC68HC05B6 MC68HC705B5 . DD 14 MOTOROLA C-5 ...

Page 162

... This bit is the EPROM program enable bit. It can be set to ‘1’ to enable programming only after ELAT is set and at least one byte is written to the EPROM not possible to clear EPGM by software, but clearing ELAT will always clear EPGM. ECLK — External clock option bit See Section 4.3. 14 MOTOROLA C-6 Address bit 7 bit 6 bit 5 ...

Page 163

... WWAT — Watchdog during WAIT mode This bit can modify the status of the watchdog counter during WAIT mode. MC68HC05B6 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 EPP 0 RTIM RWAT WWAT PBPD PCPD Not affected MC68HC705B5 State bit 1 bit 0 on reset 14 MOTOROLA C-7 ...

Page 164

... Volts Volts Volts Volts Don’t care 14 MOTOROLA C active only while the pin is an input active only while the pin is an input. PD Table C-2 Mode of operation selection PD2 PD3 PD4 Single chip Erased EPROM verifi ...

Page 165

... LED flashes Programming OK? N Red LED on Bad EPROM programming Figure C-3 Modes of operation flow chart ( MC68HC05B6 N User mode N Non-user mode Y EPROM N PD2 set? erased Non-user mode Green LED on Y Green LED on EPROM verified MC68HC705B5 N Red LED on EPROM not erased 14 MOTOROLA C-9 ...

Page 166

... Bootstrap RAM PD4 set? Y Load next RAM byte N RAM full? Y Execute RAM program at $0050 Figure C-4 Modes of operation flow chart ( MOTOROLA C-10 N PD3 set Red LED off Transmit last four programmed locations Receive address Receive four data Y Negative Green LED on ...

Page 167

... The entire EPROM can be loaded from the external source desired to leave a segment undisturbed, the data for this segment should be all zeros. Address HDSK out (PC5) DATA HDSK in (PC6) F29 Figure C-5 Timing diagram with handshake MC68HC05B6 Data read MC68HC705B5 14 Data read MOTOROLA C-11 ...

Page 168

... VPP 27C64 A10 23 A11 2 A12 GND 14 14 Figure C-6 EPROM(RAM) parallel bootstrap schematic diagram MOTOROLA C-12 RESET RUN 1N914 100k 1k TCAP1 VRH 1N914 1.0F + IRQ RESET NC red LED TCMP1 470 0.01F TCMP2 PLMA 470 PLMB green LED red LED — programming failed green LED — ...

Page 169

... RS232 link at 9600 baud, 8-bit, no parity and full duplex. Data format is not ASCII, but 8-bit binary complementary program must be run by the host to supply the required format. Such a program is available for the IBM PC from Motorola. The EPROM bootstrap routines are used to customise the OTP EPROM. To increase the speed of programming, four bytes are programmed in parallel while the data is simultaneously transmitted and received in full duplex ...

Page 170

... B inputs available. The EPROM parallel bootstrap loader circuit (Figure C-6) can also be used, provided VPP is tied The high order address lines will be at zero. The LEDs will stay off MOTOROLA C-14 Table C-3 Bootstrap vector targets in RAM Vector targets in RAM SCI interrupt $00E4 Timer overfl ...

Page 171

... PD0 13 47 PC2 PD1 12 48 PC1 PD2 5 49 PC0 PD5 4 PD6 3 23 PD7 TCAP2 2 50 TCMP1 RDI 1 52 TCMP2 TDO 51 SCLK 40 NC VSS VRL 41 7 MC68HC705B5 P1 1 GND 2 + 47F 47F + 10M 4.0 MHz 22pF 1 k 10k BC239C 1nF 14 MOTOROLA C-15 ...

Page 172

... Figure C-8 RAM parallel bootstrap schematic diagram MOTOROLA C-16 RESET RUN 1N914 100k 1k TCAP1 1N914 1.0F + IRQ RESET 0.01F MC68HC705B5 +5V + 100k VPP NC PGM VCC PB0 9 PB1 A11 A1 8 PB2 A12 A2 7 PB3 A3 6 PB4 ...

Page 173

... Figure C-9 EPROM parallel bootstrap loader timing diagram MC68HC05B6 t t COOE COOE t t ADE ADE t t DHE DHE 5 machine cycles 14 machine cycles 117 machine cycles < t < 150 machine cycles COOE (5ms nominal) COOE PROG 1 machine cycle = 1/(2f (Xtal)) 0 MC68HC705B5 t CDDE t ADE t DHE 14 MOTOROLA C-17 ...

Page 174

... Address PC5 out Data PC6 in PD4 Figure C-10 14 MOTOROLA C- ADR t DHR t max HI t max EXR t max (address to data delay; PC6=PC5) ADR t min (data hold time) DHR t (load cycle time; PC6=PC5 (PC5 handshake out delay max (PC6 handshake in, data hold time) ...

Page 175

... EPROM programming time MC68HC05B6 = 25C) Symbol Min Typ I 80 RPD = max V — PP6 DD V 15.0 15.5 PP6 I — — PP6 PP6R Symbol Min Typ t 5 — PROG MC68HC705B5 Max Unit Max Unit MOTOROLA C-19 ...

Page 176

... THIS PAGE INTENTIONALLY LEFT BLANK 14 MOTOROLA C-20 MC68HC705B5 MC68HC05B6 ...

Page 177

... The self-check routines for the MC68HC05B16 are identical to those of the MC68HC05B6 with the following exception. The count byte on the MC68HC05B16 can be any value up to 256 ($00). The first 176 bytes are loaded into RAM I and the remainder is loaded into RAM II starting at $0250. MC68HC05B6 D MC68HC05B16 14 MOTOROLA D-1 ...

Page 178

... RESET IRQ OSC2 OSC1 VDD VSS PD0/AN0 PD1/AN1 PD2/AN2 PD3/AN3 PD4/AN4 PD5/AN5 PD6/AN6 PD7/AN7 VRH VRL 14 MOTOROLA D-2 256 bytes EEPROM Charge pump 496 bytes self-check ROM 15120 bytes ROM COP watchdog Oscillator 352 bytes static RAM M68HC05 CPU 16-bit timer ...

Page 179

... Capture low register 1 $0016 Compare high register 1 $0017 Compare low register 1 $0018 Counter high register Counter low register $0019 $001A $001B Capture high register 2 $001C Capture low register 2 $001D $001E Compare high register 2 Compare low register 2 $001F Options register $0100 14 MOTOROLA D-3 ...

Page 180

... This bit is set each time there is a power-on reset. (2) The state of the WDOG bit after reset is dependent upon the mask option selected; 1=watchdog enabled, 0=watchdog disabled. (3) This register is implemented in EEPROM; therefore reset has no effect on the individual bits. 14 MOTOROLA D-4 Table D-1 Register outline Address bit 7 ...

Page 181

... PLCC and 64-pin QFP packages Note: The electrical characteristics of the MC68HC05B6 as provided in Section 11 do not apply to the MC68HC705B16. Data specific to the MC68HC705B16 can be found in this appendix. MC68HC05B6 E 0, $0C Start watchdog STOP causes immediate watchdog system reset MC68HC705B16 14 MOTOROLA E-1 ...

Page 182

... RESET IRQ OSC2 OSC1 VDD VSS PD0/AN0 PD1/AN1 PD2/AN2 PD3/AN3 PD4/AN4 PD5/AN5 PD6/AN6 PD7/AN7 VRH VRL 14 MOTOROLA E-2 256 bytes EEPROM Charge pump 576 bytes bootstrap ROM 15168 bytes EPROM COP watchdog Oscillator 352 bytes static RAM M68HC05 CPU 16-bit timer ...

Page 183

... Compare high register 1 $0017 Compare low register 1 $0018 Counter high register Counter low register $0019 $001A $001B Capture high register 2 $001C Capture low register 2 $001D $001E Compare high register 2 Compare low register 2 $001F Options register $0100 Mask option register $3DFE 14 MOTOROLA E-3 ...

Page 184

... The state of the WDOG bit after reset is dependent upon the mask option selected; 1=watchdog enabled, 0=watchdog disabled. (3) This register is implemented in EEPROM; therefore reset has no effect on the individual bits. (4) This register is implemented in EPROM; therefore reset has no effect on the individual bits. 14 MOTOROLA E-4 Table E-1 Register outline Address bit 7 ...

Page 185

... To allow simultaneous programming eight bytes, these bytes must be in the same group of addresses which share the same most significant address bits; only the three least significant bits can change. MC68HC05B6 is controlled by one of the PP6 . DD MC68HC705B16 switching PP6 14 MOTOROLA E-5 ...

Page 186

... E6LAT is set and at least one byte is written to the EPROM not possible to clear this bit using software but clearing E6LAT will always clear E6PGM. E6LAT E6PGM Note: The E6PGM bit can never be set while the E6LAT bit is at zero. ECLK See Section 4.3. 14 MOTOROLA E-6 Address bit 7 bit 6 bit 5 bit 4 $0007 ...

Page 187

... The E1PGM and E1ERA bits are cleared when the E1LAT bit is at zero. MC68HC05B6 programming time, the E1LAT bit has to be reset PROG1 Description 0 Read condition 0 Ready to load address/data for program/erase 1 Byte programming in progress 0 Ready for byte erase (load address) 1 Byte erase in progress MC68HC705B16 14 MOTOROLA E-7 ...

Page 188

... PD PCPD — Port C pull-down This bit, when programmed, connects a resistive pull-down on each pin of port C. This pull-down active on a given pin only while input MOTOROLA E-8 Address bit 7 bit 6 bit 5 bit 4 (1) ...

Page 189

... EPROM erase verification mode with PD1 set. When the SEC bit is changed, its new value will have no effect until the next power-on or external reset. 1 (set) – EEPROM/EPROM not protected. 0 (clear) – EEPROM/EPROM protected. MC68HC05B6 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 MC68HC705B16 State bit 1 bit 0 on reset EE1P SEC Not affected 14 MOTOROLA E-9 ...

Page 190

... Don’t care The bootstrap program first copies part of itself in RAM (except ‘RAM parallel load’), as the program cannot be executed in ROM during verification/programming of the EPROM. It then sets the TCMP1 output to a logic high level. 14 MOTOROLA E-10 Table E-4 Mode of operation selection ...

Page 191

... Non-user mode Erased EPROM verification EPROM N N PD2 set? erased Non-user mode Red LED on EPROM not erased Red LED on Y Green LED on EPROM verified MC68HC705B16 Y Green LED on N PD1 set? Y Bulk erase EEPROM1 N EEPROM1 erased? Y Red LED off 14 MOTOROLA E-11 ...

Page 192

... Parallel bootstrap RAM PD4 set? Y Load next RAM byte N RAM1 full? Y Execute RAM program at $0050 Figure E-4 Modes of operation flow chart ( MOTOROLA E-12 Y SEC bit set? Red LED flashes N N PD3 set Transmit last four programmed locations Receive address Receive four data ...

Page 193

... PC5 and PC6. If the data is supplied by a parallel interface, handshaking will be provided by PC5 and PC6 according to the timing diagram of Figure E-5 (see also Figure E-6). Address HDSK out (PC5) Data HDSK in (PC6) F29 Figure E-5 Timing diagram with handshake MC68HC05B6 Data read MC68HC705B16 Data read 14 MOTOROLA E-13 ...

Page 194

... DHE Data t max (address to data delay) ADE t min (data hold time) DHA t (load cycle time) COOE t (programming cycle time) CDDE Figure E-6 Parallel EPROM loader timing diagram 14 MOTOROLA E- COOE COOE t t ADE ADE t t DHE DHE 5 machine cycles 14 machine cycles 117 machine cycles < t < ...

Page 195

... PA6 PC2 PA7 PC1 PC0 VSS MC68HC705B16 P1 1 GND 2 + 47F + 4.0 MHz 22pF Erase check & boot EPROM erase check RAM EPROM 1 k 10k BC239C 1nF +5V HDSK out Short circuit if handshake not used HDSK in A12 A11 A10 MOTOROLA E-15 ...

Page 196

... In response to the first byte prompt, the host sends the first address byte. 3 After receiving the first address byte, the MC68HC705B16 sends the next 14 byte programmed. MOTOROLA E-16 MC68HC705B16 MC68HC705B16 ...

Page 197

... PA7 46 PC3 47 PC2 14 PD0 48 PC1 13 PD1 49 PC0 12 PD2 5 PD5 4 PD6 VPP1 3 23 PD7 TCAP2 2 50 TCMP1 RDI 1 52 TCMP2 TDO 51 SCLK 40 NC VSS VRL 41 7 MC68HC705B16 P1 1 GND 2 + 47F 47F + 4.0 MHz 22pF 1 k & 10k BC239C 1nF 14 MOTOROLA E-17 ...

Page 198

... Table E-5). This allows programmers to use their own service-routine addresses. Each pseudo-vector is allowed three bytes of space rather than the two bytes for normal vectors, because an explicit jump (JMP) opcode is needed to cause the desired jump to the user’s service routine address. 14 MOTOROLA E-18 Table E-5 Bootstrap vector targets in RAM Vector targets in RAM SCI interrupt $02EE Timer overfl ...

Page 199

... PC6=PC5 EXR Figure E-9 Parallel RAM loader timing diagram MC68HC05B6 level. The high order address ADR t DHR t max HI t max EXR 1 machine cycle = 1/(2f (Xtal)) 0 MC68HC705B16 16 machine cycles 4 machine cycles 49 machine cycles 5 machine cycles 10 machine cycles 30 machine cycles 14 MOTOROLA E-19 ...

Page 200

... PD4 must be high during the first 49 program cycles and pulled low before the 68th cycle for immediate jump execution at address $0050 + 4. Figure E-10 RAM parallel bootstrap schematic diagram 14 Note: MOTOROLA E-20 RESET RUN 1N914 100k 1k TCAP1 1N914 1.0F + IRQ RESET ...

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