HD6417014F28 Renesas Electronics Corporation., HD6417014F28 Datasheet
HD6417014F28
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HD6417014F28 Summary of contents
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... The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. SH7014, SH7016, SH7017F-ZTAT 32 Rev.5.00 Revision date: Sep. 27, 2007 Renesas 32-Bit RISC Microcomputer TM SuperH RISC engine family/SH7010 Series SH7014 SH7016 SH7017 TM Hardware Manual HD6417014F28 HD6417014RF28 HD6437016F28 HD64F7017F28 www.renesas.com ...
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This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in ...
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...
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Rev.5.00 Sep. 27, 2007 Page iv of xxxiv REJ09B0398-0500 ...
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The SH7014/16/17 CMOS single-chip microprocessors integrate a Renesas Technology-original architecture, high-speed CPU with peripheral functions required for system configuration. The CPU has a RISC-type instruction set. Most instructions can be executed in one clock cycle, which greatly improves instruction execution ...
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Rev.5.00 Sep. 27, 2007 Page vi of xxxiv REJ09B0398-0500 ...
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Main Revisions for This Edition Item Page All — 1.2 Block Diagram 6 Figure 1.1 Block Diagram of the SH7014 Figure 1.2 Block 7 Diagram of the SH7016, SH7017 Revision (See Manual for Details) Company name and brand names amended ...
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Item Page 1.3.1 Pin Arrangement 9 Figure 1.4 SH7016, SH7017 Pin Arrangement (FP-112 Top View) 5.3.1 Address Error 64 Sources Table 5.5 Bus Cycles and Address Errors 5.4.1 Interrupt Sources 65 6.3.1 Interrupt Priority 82 Registers (IPRA ...
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Item Page 8.2.5 DRAM Area 115 Control Register (DCR) 9.1.1 Features 147 9.2.3 DMA Transfer 153 Count Registers 0, 1 (DMATCR0, DMATCR1) 9.3.5 Number of Bus 176 Cycle States and DREQ Pin Sample Timing Cycle Steal Mode Operations: Figure 9.12 ...
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Item Page 9.3.6 DMA Transfer 187 Ending Conditions Conditions for Ending All Channels Simultaneously: 9.4.2 Example of DMA 189 Transfer between External RAM and External Device with DACK 10.1.1 Features 191 10.1.4 Register 198 Configuration Table 10.3 Register Configuration 10.2.4 ...
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Item Page 10.4.4 Buffer Operation 237 Buffer Operation Examples⎯when TGR Is an Input Capture Register Figure 10.20 Buffer 238 Operation Example (Input Capture Register) 10.4.6 PWM Mode 240 10.4.7 Phase Counting 250 Mode Phase Counting Mode Application Example: 10.6.1 Input/Output ...
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Item Page 10.8.1 Operating 273 Modes 10.8.3 Operation in 273 Case of Re-Setting Due to Error during Operation, Etc. 10.8.4 Overview of 277 Initialization Procedures and Mode Transitions in Case of Error during Operation, etc. (3) Operation when Error Occurs ...
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Item Page 12.2.7 Serial Status 318 Register (SSR) Bit 4—Framing Error (FER): Bit 3—Parity Error (PER): Revision (See Manual for Details) Description amended and notes added Bit 4 FER Description 0 Receiving is in progress or has ended normally* [Clearing ...
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Item Page 12.5.7 Constraints on 366 DMAC Use 13.1.1 Features 367 13.4 Operation 378 13.4.7 Conversion 388 Start Modes Rev.5.00 Sep. 27, 2007 Page xiv of xxxiv REJ09B0398-0500 Revision (See Manual for Details) Description amended • When using an external ...
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Item Page 13.4.8 A/D Conversion 392 Time Table 13.7 A/D Conversion Times Table 13.8 Operating Frequency and CKS Bit Settings 13.6.5 A/D Conversion 394 Termination (HD6417014R only) 14.1.3 Pin 399 Configuration 14.2.1 A/D Data 401 Register (ADDRA ...
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Item Page 15.4.3 Compare Match 428 Flag Clear Timing 16.3.2 Port A Control 446 Registers L1, L2 (PACRL1 and PACRL2) Port A Control Register 447 L1 (PACRL1): Bit 14—PA15 Mode (PA15MD): 16.3.3 Port B I/O 452 Register (PBIOR) 17.2.2 Port ...
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Item Page 17.6.2 Port E Data 485 Register (PEDR) 17.7.2 Port F Data 487 Register (PFDR) 18.4 Register 497 Configuration Table 18.3 Flash Memory Registers Revision (See Manual for Details) Description amended PEDR is initialized by a external power-on reset. ...
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Item Page 18.5.4 RAM Emulation 503 Register (RAMER) 18.7.2 Program-Verify 512 Mode Figure 18.13 Program/ Program-Verify Flowchart Rev.5.00 Sep. 27, 2007 Page xviii of xxxiv REJ09B0398-0500 Revision (See Manual for Details) Description amended RAMER specifies the area of flash memory ...
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Item Page 18.7.3 Erase Mode 517 18.8.2 Software 525 Protection 18.11.4 Auto-Program 538 Mode 18.11.6 Status Read 543 Mode Table 18.19 Status Read Mode Return Commands 22.3.3 Bus Timing 567 Table 22.7 Bus Timing 22.3.4 Direct Memory 579 Access Controller ...
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Item Page 22.3.5 Multifunction 581 Timer Pulse Unit Timing Table 22.9 Multifunction Timer Pulse Unit Timing 22.3.6 I/O Port Timing 582 Table 22.10 I/O Port Timing 22.3.7 Watchdog Timer 583 Timing Table 22.11 Watchdog Timer Timing 22.3.8 Serial 583 Communication ...
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Section 1 SH7014/16/17 Overview 1.1 SH7014/16/17 Overview................................................................................................... 1.1.1 SH7014/16/17 Series Features ............................................................................. 1.2 Block Diagram .................................................................................................................. 1.3 Pin Arrangement and Pin Functions.................................................................................. 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Arrangement by Mode................................................................................... 10 1.3.3 Pin Functions ....................................................................................................... 14 Section 2 CPU ...
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External Clock Input Method............................................................................... 56 4.3 Prescaler............................................................................................................................ 57 Section 5 Exception Processing 5.1 Overview........................................................................................................................... 59 5.1.1 Types of Exception Processing and Priority ........................................................ 59 5.1.2 Exception Processing Operations......................................................................... 60 5.1.3 Exception Processing Vector Table ..................................................................... 61 5.2 Resets ................................................................................................................................ ...
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On-Chip Peripheral Module Interrupts ................................................................ 77 6.2.4 Interrupt Exception Vectors and Priority Rankings ............................................. 77 6.3 Description of Registers.................................................................................................... 81 6.3.1 Interrupt Priority Registers (IPRA to IPRH) ............................................ 81 6.3.2 Interrupt Control Register (ICR).......................................................................... 82 6.3.3 ...
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Wait Control Register 1 (WCR1)......................................................................... 112 8.2.4 Wait Control Register 2 (WCR2)......................................................................... 114 8.2.5 DRAM Area Control Register (DCR) ................................................................. 115 8.2.6 Refresh Timer Control/Status Register (RTCSR) ................................................ 118 8.2.7 Refresh Timer Counter (RTCNT)........................................................................ 121 8.2.8 Refresh Time Constant ...
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Operation........................................................................................................................... 161 9.3.1 DMA Transfer Flow ............................................................................................ 161 9.3.2 DMA Transfer Requests ...................................................................................... 163 9.3.3 Channel Priority ................................................................................................... 165 9.3.4 DMA Transfer Types........................................................................................... 165 9.3.5 Number of Bus Cycle States and DREQ Pin Sample Timing.............................. 172 9.3.6 DMA Transfer ...
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Phase Counting Mode.......................................................................................... 244 10.5 Interrupts........................................................................................................................... 251 10.5.1 Interrupt Sources and Priority Ranking................................................................ 251 10.5.2 DMAC Activation................................................................................................ 252 10.5.3 A/D Converter Activation.................................................................................... 252 10.6 Operation Timing.............................................................................................................. 253 10.6.1 Input/Output Timing ............................................................................................ 253 10.6.2 Interrupt Signal Timing........................................................................................ 258 10.7 Usage ...
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Operation........................................................................................................................... 298 11.3.1 Watchdog Timer Mode ........................................................................................ 298 11.3.2 Interval Timer Mode ............................................................................................ 300 11.3.3 Clearing the Standby Mode.................................................................................. 300 11.3.4 Timing of Setting the Overflow Flag (OVF) ....................................................... 301 11.3.5 Timing of Setting the Watchdog Timer Overflow Flag ...
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Receive Error Flags and Transmitter Operation (Clock Synchronous Mode Only) ........................................................................ 364 12.5.6 Receive Data Sampling Timing and Receive Margin in the Asynchronous Mode .................................................................................................................... 364 12.5.7 Constraints on DMAC Use .................................................................................. 366 12.5.8 Cautions for Clock Synchronous External ...
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Block Diagram ..................................................................................................... 398 14.1.3 Pin Configuration................................................................................................. 399 14.1.4 Register Configuration......................................................................................... 400 14.2 Register Descriptions ........................................................................................................ 401 14.2.1 A/D Data Register (ADDRA to ADDRD) ............................................... 401 14.2.2 A/D Control/Status Register (ADCSR) ............................................................... 402 14.2.3 A/D Control ...
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Section 16 Pin Function Controller (PFC) 16.1 Overview........................................................................................................................... 433 16.2 Register Configuration...................................................................................................... 444 16.3 Register Descriptions ........................................................................................................ 445 16.3.1 Port A I/O Register L (PAIORL)......................................................................... 445 16.3.2 Port A Control Registers L1, L2 (PACRL1 and PACRL2) ................................. 446 16.3.3 Port ...
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Mode Transitions ................................................................................................. 491 18.2.3 On-Board Programming Modes........................................................................... 492 18.2.4 Flash Memory Emulation in RAM ...................................................................... 494 18.2.5 Differences between Boot Mode and User Program Mode.................................. 495 18.2.6 Block Configuration............................................................................................. 496 18.3 Pin Configuration.............................................................................................................. 496 18.4 Register Configuration ...................................................................................................... ...
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Section 20 RAM .................................................................................................................. 549 20.1 Overview........................................................................................................................... 549 Section 21 Power-Down State 21.1 Overview........................................................................................................................... 551 21.1.1 Power-Down States.............................................................................................. 551 21.1.2 Related Register ................................................................................................... 552 21.2 Standby Control Register (SBYCR) ................................................................................. 553 21.3 Sleep Mode ....................................................................................................................... 554 21.3.1 Transition to Sleep ...
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C.1 Pin States........................................................................................................................... 707 C.2 Pin States of Bus Related Signals ..................................................................................... 709 Appendix D Notes when Converting the F-ZTAT Application Software to the Mask-ROM Versions Appendix E Product Code Lineup Appendix F Package Dimensions ................................................................................. 713 .................................................................................. 714 ................................................................................... ...
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Rev.5.00 Sep. 27, 2007 Page xxxiv of xxxiv REJ09B0398-0500 ...
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Section 1 SH7014/16/17 Overview 1.1 SH7014/16/17 Overview The SH7014/16/17 CMOS single-chip microprocessors integrate a Renesas Technology-original architecture, high-speed CPU with peripheral functions required for system configuration. The CPU has a RISC-type instruction set. Most instructions can be executed in one ...
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SH7014/16/17 Overview ⎯ Delayed branch instructions reduce pipeline disruption during branch ⎯ Instruction set based on C language • Instruction execution time: one instruction/cycle (35 ns/instruction at 28.7-MHz operation) • Address space: Architecture supports 4 Gbytes • On-chip multiplier: ...
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DRAM burst access function ⎯ Supports high-speed access mode for DRAM • DRAM refresh function ⎯ Programmable refresh interval ⎯ Supports CAS-before-RAS refresh and self-refresh modes • Wait cycles can be inserted using an external WAIT signal • Address ...
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SH7014/16/17 Overview Watchdog Timer (WDT) (One Channel): • Watchdog timer or interval timer • Count overflow can generate an internal reset, external signal, or interrupt Serial Communication Interface (SCI) (Two Channels): (Per Channel): • Asynchronous or clock-synchronous mode is ...
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... Power-down modes ⎯ Sleep mode ⎯ Software standby mode Clock Pulse Generator (CPG): • On-chip clock pulse generator ⎯ On-chip clock-doubling PLL circuit Product Lineup: On-Chip Product Code ROM HD6417014F28 ROMless HD6417014RF28 ROMless HD6437016F28 64 kB mask ROM HD64F7017F28 128 kB flash memory ...
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SH7014/16/17 Overview 1.2 Block Diagram Figure 1 block diagram of the SH7014. Figure 1 block diagram of the SH7016/17. RES WDTOVF MD3 MD2 MD1 MD0 NMI EXTAL XTAL PLLVCC PLLCAP PLLVSS ...
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RES WDTOVF MD3 MD2 MD1 MD0 NMI EXTAL XTAL PLLV cc PLL PLLCAP PLLV /FWP Interrupt V ss controller Vss Vss ...
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SH7014/16/17 Overview 1.3 Pin Arrangement and Pin Functions 1.3.1 Pin Arrangement Figure 1.3 shows the pin arrangement for the SH7014 (top view). PE0/TIOC0A/DREQ0 85 PE1/TIOC0B/DRAK0 86 87 PE2/TIOC0C/DREQ1 88 PE3/TIOC0D/DRAK1 PE4/TIOC1A PF0/AN0 92 PF1/AN1 ...
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Figure 1.4 shows the pin arrangement for the 144-pin QFP pin arrangement. PE0/TIOC0A/DREQ0 85 PE1/TIOC0B/DRAK0 86 PE2/TIOC0C/DREQ1 87 PE3/TIOC0D/DRAK1 88 PE4/TIOC1A PF0/AN0 91 PF1/AN1 92 PF2/AN2 93 PF3/AN3 94 PF4/AN4 95 PF5/AN5 ...
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SH7014/16/17 Overview 1.3.2 Pin Arrangement by Mode Table 1.1 Pin Arrangement by Mode for SH7017F (FP-112 Pin) Pin No. MCU Mode 1 PE14/DACK0/AH 2 PE15/DACK1 PC0/A0 5 PC1/A1 6 PC2/A2 7 PC3/A3 8 PC4/A4 9 ...
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Pin No. MCU Mode 31 PB8/IRQ6/A20/WAIT 32 PB9/IRQ7/A21 PA14/RD WDTOVF 35 36 PA13/WRH PA12/WRL PA11/CS1 41 PA10/CS0 42 PA9/TCLKD/IRQ3 43 PA8/TCLKC/IRQ2 44 PA7/TCLKB/CS3 45 PA6/TCLKA/CS2 46 PA5/SCK1/DREQ1/IRQ1 47 ...
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SH7014/16/17 Overview Pin No. MCU Mode 64 PD5/ PD4/D4 67 PD3/D3 68 PD2/D2 69 PD1/D1 70 PD0/ XTAL 73 MD3 74 EXTAL 75 MD2 76 NMI 77 V (FWP ...
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Pin No. MCU Mode PF6/AN6 99 PF7/AN7 100 AV CC 101 V SS 102 PE5/TIOC1B 103 V CC 104 PE6/TIOC2A 105 PE7/TIOC2B 106 PE8 107 PE9 108 PE10 109 V SS 110 PE11 111 PE12 112 ...
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SH7014/16/17 Overview 1.3.3 Pin Functions Table 1.2 lists the pin functions. Table 1.2 Pin Functions Classification Symbol Power supply Clock PLLV CC PLLV SS PLLCAP EXTAL XTAL CK RES System control WDTOVF Operating mode MD0 ...
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Classification Symbol Data bus D0 to D15 CS0 to CS3 Bus control RD WRH WRL WAIT RAS CASH CASL RDWR AH Multifunction TCLKA Timer Pulse Unit TCLKB (MTU) TCLKC TCLKD TIOC0A TIOC0B TIOC0C TIOC0D I/O Name Function I/O Data bus ...
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SH7014/16/17 Overview Classification Symbol Multifunction TIOC1A Timer Pulse Unit TIOC1B (MTU) TIOC2A TIOC2B DREQ0 to Direct memory DREQ1 access controller (DMAC) DRAK0 to DRAK1 DACK0 to DACK1 Serial TxD0 to communication TxD1 interface (SCI) RxD0 to RxD1 SCK0 to ...
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Classification Symbol I/O ports PD0 to PD15 (SH7016/17) PE0 to PE15 I/O PF0 to PF7 Usage Notes 1. Unused input pins should be pulled up or pulled down. 2. The WDTOVF pin should not be pulled down in the SH7017 ...
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SH7014/16/17 Overview Rev.5.00 Sep. 27, 2007 Page 18 of 716 REJ09B0398-0500 ...
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Register Configuration The register set consists of sixteen 32-bit general registers, three 32-bit control registers and four 32-bit system registers. 2.1.1 General Registers (Rn) The sixteen 32-bit general registers (Rn) are numbered R0 to R15. General registers are used ...
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CPU 2.1.2 Control Registers The 32-bit control registers consist of the 32-bit status register (SR), global base register (GBR), and vector base register (VBR). The status register indicates processing states. The global base register functions as a base address ...
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System Registers System registers consist of four 32-bit registers: high and low multiply and accumulate registers (MACH and MACL), the procedure register (PR), and the program counter (PC). The multiply and accumulate registers store the results of multiply and ...
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CPU 2.2 Data Formats 2.2.1 Data Format in Registers Register operands are always longwords (32 bits). When the memory operand is only a byte (8 bits word (16 bits sign-extended into a longword when loaded ...
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Word or longword immediate data is not located in the instruction code, but instead is stored in a memory table. An immediate data transfer instruction (MOV) accesses the memory table using the PC relative addressing mode with displacement. 2.3 Instruction ...
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CPU Table 2.3 Delayed Branch Instructions SH7014/16/17 CPU BRA TRGET ADD R1,R0 Multiplication/Accumulation Operation: 16-bit × 16-bit → 32-bit multiplication operations are executed in one to two cycles. 16-bit × 16-bit + 64-bit → 64-bit multiplication/accumulation operations are executed ...
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Table 2.5 Immediate Data Accessing Classification SH7014/16/17 CPU 8-bit immediate MOV 16-bit immediate MOV.W .DATA.W 32-bit immediate MOV.L .DATA.L Note: @(disp, PC) accesses the immediate data. Absolute Address: When data is accessed by absolute address, the value already in the ...
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CPU 2.3.2 Addressing Modes Table 2.8 describes addressing modes and effective address calculation. Table 2.8 Addressing Modes and Effective Addresses Addressing Instruction Mode Format Direct register Rn addressing Indirect register @Rn addressing Post-increment @Rn+ indirect register addressing Pre-decrement @–Rn ...
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Addressing Instruction Mode Format Indirect register @(disp:4, addressing with Rn) displacement Indirect indexed @(R0, Rn) The effective address is the Rn value plus R0. register addressing Indirect GBR @(disp:8, addressing with GBR) displacement Effective Addresses Calculation The effective address is ...
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CPU Addressing Instruction Mode Format Indirect indexed @(R0, GBR) The effective address is the GBR value plus the R0. GBR addressing PC relative @(disp:8, addressing with PC) displacement Rev.5.00 Sep. 27, 2007 Page 28 of 716 REJ09B0398-0500 Effective Addresses ...
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Addressing Instruction Mode Format PC relative disp:8 addressing disp:12 Rn Immediate #imm:8 addressing #imm:8 #imm:8 Effective Addresses Calculation The effective address is the PC value sign-extended with an 8-bit displacement (disp), doubled, and added to the PC value. PC disp ...
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CPU 2.3.3 Instruction Format Table 2.9 lists the instruction formats for the source operand and the destination operand. The meaning of the operand depends on the instruction code. The symbols are used as follows: • xxxx: Instruction code • ...
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Instruction Formats nm format 15 xxxx nnnn mmmm xxxx md format 15 xxxx xxxx dddd mmmm nd4 format 15 xxxx xxxx nnnn dddd nmd format 15 xxxx nnnn mmmm dddd Source Destination Operand Operand mmmm: Direct nnnn: Direct register register ...
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CPU Instruction Formats d format 15 xxxx xxxx dddd dddd d12 format 15 xxxx dddd dddd dddd nd8 format 15 xxxx nnnn dddd dddd i format 15 xxxx xxxx format ...
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Instruction Set by Classification Table 2.10 Classification of Instructions Operation Classification Types Code Data transfer 5 MOV MOVA MOVT SWAP XTRCT Arithmetic 21 ADD operations ADDC ADDV CMP/cond Comparison DIV1 DIV0S DIV0U DMULS DMULU DT EXTS EXTU MAC MUL ...
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CPU Operation Classification Types Code Logic 6 AND operations NOT OR TAS TST XOR Shift 10 ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLLn SHLR SHLRn Branch BRA BRAF BSR BSRF JMP JSR RTS Rev.5.00 Sep. ...
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Operation Classification Types Code System control 11 CLRT CLRMAC LDC LDS NOP RTE SETT SLEEP STC STS TRAPA Total: 62 Table 2.11 shows the format used in tables 2.12 to 2.17, which list instruction codes, operation, and execution states in ...
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CPU Table 2.11 Instruction Code Format Item Format Instruction OP.Sz SRC,DEST MSB ↔ LSB Instruction code →, ← Operation (xx) M/Q/T & <<n >>n ⎯ Execution cycles ⎯ T bit Notes: 1. Depending on the operand ...
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Table 2.12 Data Transfer Instructions Instruction MOV #imm,Rn MOV.W @(disp,PC),Rn MOV.L @(disp,PC),Rn MOV Rm,Rn MOV.B Rm,@Rn MOV.W Rm,@Rn MOV.L Rm,@Rn MOV.B @Rm,Rn MOV.W @Rm,Rn MOV.L @Rm,Rn MOV.B Rm,@–Rn MOV.W Rm,@–Rn MOV.L Rm,@–Rn MOV.B @Rm+,Rn MOV.W @Rm+,Rn MOV.L @Rm+,Rn MOV.B R0,@(disp,Rn) ...
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CPU Instruction MOV.W Rm,@(R0,Rn) MOV.L Rm,@(R0,Rn) MOV.B @(R0,Rm),Rn MOV.W @(R0,Rm),Rn MOV.L @(R0,Rm),Rn MOV.B R0,@(disp,GBR) 11000000dddddddd MOV.W R0,@(disp,GBR) 11000001dddddddd MOV.L R0,@(disp,GBR) 11000010dddddddd MOV.B @(disp,GBR),R0 11000100dddddddd MOV.W @(disp,GBR),R0 11000101dddddddd MOV.L @(disp,GBR),R0 11000110dddddddd MOVA @(disp,PC),R0 MOVT Rn SWAP.B Rm,Rn SWAP.W Rm,Rn XTRCT ...
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Table 2.13 Arithmetic Operation Instructions Instruction Instruction Code ADD Rm,Rn 0011nnnnmmmm1100 ADD #imm,Rn 0111nnnniiiiiiii ADDC Rm,Rn 0011nnnnmmmm1110 ADDV Rm,Rn 0011nnnnmmmm1111 CMP/EQ #imm,R0 10001000iiiiiiii CMP/EQ Rm,Rn 0011nnnnmmmm0000 CMP/HS Rm,Rn 0011nnnnmmmm0010 CMP/GE Rm,Rn 0011nnnnmmmm0011 CMP/HI Rm,Rn 0011nnnnmmmm0110 CMP/GT Rm,Rn 0011nnnnmmmm0111 CMP/PL Rn ...
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CPU Instruction Instruction Code DMULS.L Rm,Rn 0011nnnnmmmm1101 DMULU.L Rm,Rn 0011nnnnmmmm0101 DT Rn 0100nnnn00010000 EXTS.B Rm,Rn 0110nnnnmmmm1110 EXTS.W Rm,Rn 0110nnnnmmmm1111 EXTU.B Rm,Rn 0110nnnnmmmm1100 EXTU.W Rm,Rn 0110nnnnmmmm1101 MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111 MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111 MUL.L Rm,Rn 0000nnnnmmmm0111 MULS.W Rm,Rn 0010nnnnmmmm1111 MULU.W Rm,Rn ...
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Instruction Instruction Code SUB Rm,Rn 0011nnnnmmmm1000 SUBC Rm,Rn 0011nnnnmmmm1010 SUBV Rm,Rn 0011nnnnmmmm1011 Note: * The normal minimum number of execution cycles. (The number in parentheses is the number of cycles when there is contention with following instructions.) Exec. Operation Cycles ...
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CPU Table 2.14 Logic Operation Instructions Instruction AND Rm,Rn AND #imm,R0 AND.B #imm,@(R0,GBR) NOT Rm,Rn OR Rm,Rn OR #imm,R0 OR.B #imm,@(R0,GBR) TAS.B @Rn* TST Rm,Rn TST #imm,R0 TST.B #imm,@(R0,GBR) XOR Rm,Rn XOR #imm,R0 XOR.B #imm,@(R0,GBR) Note: * The on-chip ...
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Table 2.15 Shift Instructions Instruction Instruction Code ROTL Rn 0100nnnn00000100 ROTR Rn 0100nnnn00000101 ROTCL Rn 0100nnnn00100100 ROTCR Rn 0100nnnn00100101 SHAL Rn 0100nnnn00100000 SHAR Rn 0100nnnn00100001 SHLL Rn 0100nnnn00000000 SHLR Rn 0100nnnn00000001 SHLL2 Rn 0100nnnn00001000 SHLR2 Rn 0100nnnn00001001 SHLL8 Rn 0100nnnn00011000 ...
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CPU Table 2.16 Branch Instructions Instruction Instruction Code 10001011dddddddd disp × → PC label 10001111dddddddd Delayed branch disp × BF/S label 10001001dddddddd ...
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Table 2.17 System Control Instructions Instruction Instruction Code CLRT 0000000000001000 CLRMAC 0000000000101000 LDC Rm,SR 0100mmmm00001110 LDC Rm,GBR 0100mmmm00011110 LDC Rm,VBR 0100mmmm00101110 LDC.L @Rm+,SR 0100mmmm00000111 LDC.L @Rm+,GBR 0100mmmm00010111 LDC.L @Rm+,VBR 0100mmmm00100111 LDS Rm,MACH 0100mmmm00001010 LDS Rm,MACL 0100mmmm00011010 LDS Rm,PR 0100mmmm00101010 LDS.L ...
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CPU Instruction Instruction Code STS.L MACH,@–Rn 0100nnnn00000010 STS.L MACL,@–Rn 0100nnnn00010010 STS.L PR,@–Rn 0100nnnn00100010 TRAPA #imm 11000011iiiiiiii Note: The number of execution cycles before the chip enters sleep mode: The execution cycles shown in the table are minimums. The actual ...
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From any state when RES = 0 When an interrupt source or DMA address error occurs source occurs SBY bit cleared for SLEEP instruction Sleep mode Power-down state Figure 2.6 Transitions between Processing States Power-on reset state RES = 1 ...
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CPU Reset State: The CPU resets in the reset state. When the RES pin level goes low, a power-on reset results. Exception Processing State: The exception processing state is a transient state that occurs when exception processing sources such ...
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To return from standby mode, use a power-on reset or an NMI interrupt. For resets, the CPU returns to ordinary program execution state through the exception processing state when placed in a reset state for the duration of the oscillator ...
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CPU Rev.5.00 Sep. 27, 2007 Page 50 of 716 REJ09B0398-0500 ...
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Section 3 Operating Modes 3.1 Operating Modes, Types, and Selection This LSI has five operating modes and three clock modes, determined by the setting of the mode pins (MD3 to MD0). Do not change the mode pin settings during LSI ...
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Operating Modes 3.2 Explanation of Operating Modes Table 3.3 describes the operating modes. Table 3.3 Operating Modes Mode (MCU) Mode 0 (MCU) Mode 1 (MCU) Mode 2 Mode 3 (single chip mode) Clock mode 3.3 Pin Configuration Table 3.4 ...
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Section 4 Clock Pulse Generator (CPG) 4.1 Overview This LSI has an on-chip clock pulse generator (CPG) that generates the system clock (φ), as well as the internal clock (φ/2 to φ/8192). The CPG consists of an oscillator, a PLL, ...
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Clock Pulse Generator (CPG) 4.2 Oscillator Clock pulses can be supplied from a connected crystal resonator or an external clock. 4.2.1 Connecting a Crystal Oscillator Circuit Configuration: A crystal oscillator can be connected as shown in figure 4.2. Use ...
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Table 4.2 Crystal Oscillator Parameters Parameter Rs max (Ω) Co max (pF) Notes on Board Design: When connecting a crystal oscillator, observe the following precautions: • To prevent induction from interfering with correct oscillation, do not route any signal lines ...
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Clock Pulse Generator (CPG) External circuitry such as that shown in figure 4.5 is recommended around the PLL. PLLCAP PLLV PLLV V V Note and CPB are laminated ceramic capacitors (Recommended values) Figure 4.5 Cautions for Use ...
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EXTAL XTAL Figure 4.6 Example of External Clock Connection 4.3 Prescaler The prescaler divides the system clock (φ) to generate an internal clock (φ/2 to φ/8192) for supply to peripheral modules. Open Rev.5.00 Sep. 27, 2007 Page 57 of 716 ...
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Clock Pulse Generator (CPG) Rev.5.00 Sep. 27, 2007 Page 58 of 716 REJ09B0398-0500 ...
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Section 5 Exception Processing 5.1 Overview 5.1.1 Types of Exception Processing and Priority Exception processing is started by four sources: resets, address errors, interrupts and instructions and have the priority shown in table 5.1. When several exception processing sources occur ...
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Exception Processing 5.1.2 Exception Processing Operations The exception processing sources are detected and begin processing according to the timing shown in table 5.2. Table 5.2 Timing of Exception Source Detection and the Start of Exception Processing Exception Source Power-on ...
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Exception Processing Vector Table Before exception processing begins running, the exception processing vector table must be set in memory. The exception processing vector table stores the start addresses of exception service routines. (The reset exception processing table holds the ...
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Exception Processing Exception Sources Interrupts IRQ0 IRQ1 IRQ2 IRQ3 (Reserved by system) (Reserved by system) Interrupt IRQ6 IRQ7 On-chip peripheral module* Note: * The vector numbers and vector table address offsets for each on-chip peripheral module interrupt are given ...
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Resets 5.2.1 Power-on Reset When the RES pin is driven low, the LSI does a power-on reset. To reliably reset the LSI, the RES pin should be kept at low for at least the duration of the oscillation settling ...
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Exception Processing 5.3 Address Errors 5.3.1 Address Error Sources Address errors occur when instructions are fetched or data read or written, as shown in table 5.5. Table 5.5 Bus Cycles and Address Errors Bus Cycle Bus Type Master Bus ...
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Address Error Exception Processing When an address error occurs, the bus cycle in which the address error occurred ends. When the executing instruction then finishes, address error exception processing starts up. The CPU operates as follows: 1. The status ...
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Exception Processing 5.4.2 Interrupt Priority Level The interrupt priority order is predetermined. When multiple interrupts occur simultaneously (overlap), the interrupt controller (INTC) determines their relative priorities and starts up processing according to the results. The priority order of interrupts ...
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Exceptions Triggered by Instructions 5.5.1 Types of Exceptions Triggered by Instructions Exception processing can be triggered by trap instructions, general illegal instructions, and illegal slot instructions, as shown in table 5.8. Table 5.8 Types of Exceptions Triggered by Instructions ...
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Exception Processing 5.5.3 Illegal Slot Instructions An instruction placed immediately after a delayed branch instruction is said to be placed in a delay slot. When the instruction placed in the delay slot is undefined code, illegal slot exception processing ...
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When Exception Sources Are Not Accepted When an address error or interrupt is generated after a delayed branch instruction or interrupt- disabled instruction sometimes not accepted immediately but stored instead, as shown in table 5.9. When this ...
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Exception Processing 5.7 Stack Status after Exception Processing Ends The status of the stack after exception processing ends is as shown in table 5.10. Table 5.10 Types of Stack Status After Exception Processing Ends Types Address error Trap instruction ...
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Usage Notes 5.8.1 Value of Stack Pointer (SP) The value of the stack pointer must always be a multiple of four not, an address error will occur when the stack is accessed during exception processing. 5.8.2 ...
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Exception Processing Rev.5.00 Sep. 27, 2007 Page 72 of 716 REJ09B0398-0500 ...
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Section 6 Interrupt Controller (INTC) 6.1 Overview The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC has registers for setting the priority of each interrupt which can be used by ...
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Interrupt Controller (INTC) NMI IRQ0 IRQ1 Input IRQ2 control IRQ3 IRQ6 IRQ7 (Interrupt request) DMAC (Interrupt request) MTU (Interrupt request) CMT (Interrupt request) SCI (Interrupt request) A/D (Interrupt request) WDT (Interrupt request) BSC Legend: DMAC: Direct memory access controller ...
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Pin Configuration Table 6.1 shows the INTC pin configuration. Table 6.1 Pin Configuration Name Non-maskable interrupt input pin Interrupt request input pins 6.1.4 Register Configuration The INTC has the 10 registers shown in table 6.2. These registers set the ...
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Interrupt Controller (INTC) 6.2 Interrupt Sources There are three types of interrupt sources: NMI, IRQ, and on-chip peripheral modules. Each interrupt has a priority expressed as a priority level (0 to 16, with 0 the lowest and 16 the ...
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On-Chip Peripheral Module Interrupts On-chip peripheral module interrupts are interrupts generated by the following on-chip peripheral modules: • Direct memory access controller (DMAC) • Multifunction timer pulse unit (MTU) • Compare match timer (CMT) • Serial communication interface (SCI) ...
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Interrupt Controller (INTC) Table 6.3 Interrupt Exception Processing Vectors and Priorities Interrupt Vector Vector Interrupt Source No. NMI 11 IRQ0 64 IRQ1 65 IRQ2 66 IRQ3 67 IRQ6 70 IRQ7 71 DMAC0 DEI0 72 DMAC1 DEI1 76 MTU0 TGI0A ...
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Interrupt Vector Vector Interrupt Source No. MTU1 TGI1A 96 TGI1B 97 TCI1V 100 TCI1U 101 MTU2 TGI2A 104 TGI2B 105 TCI2V 108 TCI2U 109 SCI0 ERI0 128 RXI0 129 TXI0 130 TEI0 131 SCI1 ERI1 132 RXI1 133 TXI1 134 ...
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Interrupt Controller (INTC) Interrupt Vector Vector Interrupt Source No. A/D* ADI 136 138 CMT0 CMI0 144 CMT1 CMI1 148 WDT ITI 152 BSC CMI 153 Note: * Vector No. 136 = SH7014 only 138 = SH7016, SH7017 only Rev.5.00 ...
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Description of Registers 6.3.1 Interrupt Priority Registers (IPRA to IPRH) Interrupt priority registers (IPRA to IPRH) are 16-bit readable/writable registers that set priority levels from for IRQ interrupts and on-chip ...
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Interrupt Controller (INTC) As indicated in table 6.4, four IRQ pins or groups of 4 on-chip peripheral modules are allocated to each register. Each of the corresponding interrupt priority ranks are established by setting a value from H'0 (0000) ...
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Bit 8⎯NMI Edge Select (NMIE) Bit 8 NMIE Description 0 Interrupt request is detected on falling edge of NMI input (initial value) 1 Interrupt request is detected on rising edge of NMI input Bits 0⎯IRQ0 to ...
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Interrupt Controller (INTC) Bits 0⎯IRQ0 to IRQ3, IRQ6, IRQ7 Flags (IRQ0F to IRQ3F, IRQ6F, IRQ7F): These bits display the IRQ0 to IRQ3, IRQ6, IRQ7 interrupt request status. Bits IRQ0F to ...
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Interrupt Operation 6.4.1 Interrupt Sequence The sequence of interrupt operations is explained below. Figure 6 flowchart of the operations. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects ...
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Interrupt Controller (INTC) Program execution state No Interrupt? Yes No NMI? Yes Save SR to stack Save PC to stack Copy accept-interrupt level Reads exception vector table Branches to exception service routine Legend ...
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Stack after Interrupt Exception Processing Figure 6.4 shows the stack after interrupt exception processing. Address 4n–8 4n–4 Notes: 1. PC: Start address of the next instruction (return destination instruction) after the executing instruction 2. Always be certain that SP ...
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Interrupt Controller (INTC) 6.5 Interrupt Response Time Table 6.5 indicates the interrupt response time, which is the time from the occurrence of an interrupt request until the interrupt exception processing starts and fetching of the first instruction of the ...
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IRQ Instruction (instruction replaced by interrupt exception processing) Overrun fetch Interrupt service routine start instruction Legend: F: Instruction fetch (instruction fetched from memory where program is stored). D: Instruction decoding (fetched instruction is decoded). E: Instruction execution (data operation ...
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Interrupt Controller (INTC) 6.6 Data Transfer with Interrupt Request Signals The following data transfers can be done using interrupt request signals: • Activate DMAC only, without generating CPU interrupt Among interrupt sources, those designated as DMAC activating sources are ...
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Section 7 Cache Memory (CAC) 7.1 Overview The LSI has an on-chip cache memory (CAC: CAChe) with 1 kbyte of cache data and a 256-entry cache tag. The cache data and cache tag space can be used as on-chip RAM ...
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Cache Memory (CAC) 7.1.2 Block Diagram Figure 7.2 shows a block diagram of the cache. CCR Cache tag Cache controller Cache data Cache Legend: CCR: Cache control register Rev.5.00 Sep. 27, 2007 Page 92 of 716 REJ09B0398-0500 External bus ...
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Register Configuration The cache has one register, which can be used to control the enabling or disabling of each cache space. The register configuration is shown in table 7.1. Table 7.1 Register Configuration Name Abbreviation Cache control register CCR ...
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Cache Memory (CAC) 7.2 Register Explanation 7.2.1 Cache Control Register (CCR) The cache control register (CCR) selects the cache enable/disable of each space. The CCR is a 16-bit readable/writable register initialized to H'0000 by power on resets, ...
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Bit 3⎯CS3 Space Cache Enable (CECS3): Selects whether to use CS3 space as a cache object (enable exclude it (disable disables, and a 1 enables such use. Bit 3 CECS3 Description 0 CS3 space cache disabled ...
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Cache Memory (CAC) 7.3 Address Array and Data Array There is a special cache space for controlling the cache. This space is divided into an address array and a data array, where addresses (tag address, including valid bit) and ...
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Cache Data Array Read/Write Space The cache data array has a compulsory read/write (figure 7.4). 31 Upper 22 bits of the data array space address Address 31 Data Data Array Read: Designates entry address and reads out the corresponding ...
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Cache Memory (CAC) 7.4 Usage Notes 7.4.1 Cache Initialization Always initialize the cache before enabling it. Specifically, use an address array write to write 0 to all valid bits for all entries (256 times), that is,those in the address ...
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CK Internal address Address CSn RD Data Figure 7.5 Cache Fill Timing in Case of Non-Consecutive Cache Miss from Normal Space CK Internal Miss-hit address Address CSn RD Data Figure 7.6 Cache Fill Timing in Case of Consecutive Cache Misses ...
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Cache Memory (CAC) CK Internal Miss-hit address Idle cycle Address RAS CASx Data Figure 7.7 Cache Fill Timing in Case of Non-Consecutive Cache Miss from DRAM Space (Normal Mode, TPC = 0, RCD = 0, No Wait) CK Internal ...
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Section 8 Bus State Controller (BSC) 8.1 Overview The bus state controller (BSC) divides up the address spaces and outputs control for various types of memory. This enables memories like DRAM, SRAM, and ROM to be linked directly to the ...
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Bus State Controller (BSC) 8.1.2 Block Diagram Figure 8.1 shows the BSC block diagram. WAIT CS0 to CS3 AH RD RDWR WRH, WRL CASH, CASL RAS CMI interrupt request Interrupt controller Legend: WCR1: Wait control register 1 WCR2: Wait ...
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Pin Configuration Table 8.1 shows the bus state controller pin configuration. Table 8.1 Pin Configuration Signal I/O Description A21 Address output (A21 to A18 become input ports in power-on reset) D15 to D0 I/O 16-bit data ...
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Bus State Controller (BSC) Table 8.2 Register Configuration Name Bus control register 1 Bus control register 2 Wait state control register 1 Wait state control register 2 DRAM area control register Refresh timer control/status register RTCSR Refresh timer counter ...
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Table 8.3 shows an address map. Table 8.3 Address Map • In on-chip ROM enabled mode* Address 4 H'00000000 to H'0001FFFF* H'00020000 to H'001FFFFF H'00200000 to H'003FFFFF H'00400000 to H'007FFFFF H'00800000 to H'00BFFFFF H'00C00000 to H'00FFFFFF CS3 space H'01000000 to ...
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Bus State Controller (BSC) • In on-chip ROM disabled mode Address H'00000000 to H'003FFFFF H'00400000 to H'007FFFFF H'00800000 to H'00BFFFFF H'00C00000 to H'00FFFFFF CS3 space H'01000000 to H'01FFFFFF H'02000000 to H'FFFF7FFF H'FFFF8000 to H'FFFF87FF On-chip H'FFFF8800 to H'FFFFEFFF Reserved ...
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Description of Registers 8.2.1 Bus Control Register 1 (BCR1) BCR1 is a 16-bit read/write register that selects multiplex I/O, and specifies the bus size of the CS spaces. Write bits BCR1 during the initialization stage ...
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Bus State Controller (BSC) Bits 7 to 4⎯Reserved: These bits read 0 after a reset. The write value should always be 0. Operation is not guaranteed if the write value is 1. Bit 3⎯CS3 Space Size Specification (A3SZ): Specifies ...
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Bus Control Register 2 (BCR2) BCR2 is a 16-bit read/write register that specifies the number of idle cycles and CS signal assert extension of each CS space. BCR2 is initialized by power-on resets to H'FFFF, but is not initialized ...
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Bus State Controller (BSC) Bit 13 Bit 12 IW21 IW20 Description idle cycle after accessing CS2 space 1 Inserts one idle cycle 1 0 Inserts two idle cycles 1 Inserts three idle cycles Bit 11 Bit ...
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Bit 6 CW2 Description 0 No CS2 space continuous access idle cycles 1 One CS2 space continuous access idle cycle Bit 5 CW1 Description 0 No CS1 space continuous access idle cycles 1 One CS1 space continuous access idle cycle ...
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Bus State Controller (BSC) Bit 1 SW1 Description No CS1 space CS assert extension 0 CS1 space CS assert extension 1 Bit 0 SW0 Description No CS0 space CS assert extension 0 CS0 space CS assert extension 1 8.2.3 ...
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Bits 11 to 8⎯CS2 Space Wait Specification (W23, W22, W21, W20): Specifies the number of waits for CS2 space access. Bit 11 Bit 10 Bit 9 W23 W22 W21 ⋅⋅⋅ Bits ...
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Bus State Controller (BSC) 8.2.4 Wait Control Register 2 (WCR2) WCR2 is a 16-bit read/write register that specifies the number of access cycles for DRAM space and CS space for DMA single address mode transfers. Do not perform any ...
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Bits 3 to 0⎯CS Space DMA Single Address Mode Access Wait Specification (DSW3, DSW2, DSW1, DSW0): Specifies the number of waits for CS space access (0 to 15) during DMA single address mode accesses. These bits are independent of the ...
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Bus State Controller (BSC) Bit 14⎯RAS-CAS Delay Cycle Count (RCD): Specifies the number of row address output cycles. Bit 14 RCD Description 0 1 cycle 1 2 cycles Bits 13 and 12⎯CAS-Before-RAS Refresh RAS Assert Cycle Count (TRAS1 and ...
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Bit 7⎯DRAM Idle Cycle Count (DIW): Specifies whether to insert idle cycles, either when accessing a different external space (CS space) or when doing a DRAM write, after DRAM reads. Bit 7 DIW Description 0 No idle cycles 1 1 ...
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Bus State Controller (BSC) Bits 1 and 0⎯DRAM Address Multiplex (AMX1 and AMX0): Specifies the DRAM address multiplex count. Bit 1 Bit 0 AMX1 AMX0 8.2.6 Refresh Timer Control/Status Register (RTCSR) RTCSR is ...
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Bit 6⎯Compare Match Flag (CMF): This status flag, which indicates that the values of RTCNT and RTCOR match, is set/cleared under the following conditions: Bit 6 CMF Description 0 Clear condition: After RTCSR is read when CMF ...
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Bus State Controller (BSC) Bit 1⎯Refresh Control (RFSH): Selects whether to use refresh control for DRAM. Bit 1 RFSH Description 0 Do not refresh DRAM 1 Refresh DRAM Bit 0⎯Refresh Mode (RMD): When the RFSH bit is 1, this ...
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Refresh Timer Counter (RTCNT) RTCNT is a 16-bit read/write register that is used as an 8-bit up counter for refreshes or generating interrupt requests. RTCNT counts up with the clock selected by the CKS2 to CKS0 bits of the ...
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Bus State Controller (BSC) 8.2.8 Refresh Time Constant Register (RTCOR) RTCOR is a 16-bit read/write register that establishes the compare match period with RTCNT. The values of RTCOR and RTCNT are constantly compared. When the values correspond, the compare ...
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Accessing Ordinary Space A strobe signal is output by ordinary space accesses to provide primarily for SRAM or ROM direct connections. 8.3.1 Basic Timing Figure 8.3 shows the basic timing of ordinary space accesses. Ordinary access bus cycles are ...
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Bus State Controller (BSC) 8.3.2 Wait State Control The number of wait states inserted into ordinary space access states can be controlled using the WCR settings (figure 8.4). The specified number of Tw cycles are inserted as software wait ...
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Address CSn RD Read Data WRx Write Data WAIT Figure 8.5 Wait State Timing of Ordinary Space Access (Wait States from Software Wait 2 State + WAIT Signal) 8. Bus State Controller (BSC ...
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Bus State Controller (BSC) CS Assert Period Extension 8.3.3 Idle cycles can be inserted to prevent extension of the RD signal or WRx signal assert period beyond the length of the CSn signal assert period by setting the SW3 ...
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DRAM Access 8.4.1 DRAM Direct Connection When address space A31 to A24 = H'01 has been accessed, the corresponding space becomes a 16-Mbyte DRAM space, and the DRAM interface function can be used to directly connect this LSI to ...
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Bus State Controller (BSC) 8.4.2 Basic Timing This LSI supports 2 CAS format DRAM access. The DRAM access basic timing is a minimum of 3 cycles for normal mode. Figure 8.7 shows the basic DRAM access timing. DRAM space ...
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Wait State Control Wait state insertion during DRAM space access is controlled by setting the TPC, RCD, DWW1, DWW0, DWR1, and DWR0 bits of the DCR. TPC and RCD are common to both reads and writes. The timing with ...
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Bus State Controller (BSC Address Data RAS Write CASx RDWR Data RAS Read CASx RDWR Figure 8.9 DRAM Bus Cycle (Normal Mode, TPC = 1, RCD = 1, Two Waits) Rev.5.00 Sep. 27, 2007 Page 130 ...
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Address Data RAS Write CASx RDWR Data RAS Read CASx RDWR Figure 8.10 DRAM Bus Cycle (Normal Mode, TPC = 0, RCD = 0, Three Waits cw1 cw2 Row Column Rev.5.00 ...
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Bus State Controller (BSC Address Data RAS Write CASx RDWR Data RAS Read CASx RDWR WAIT (Normal Mode, TPC = 0, RCD = 0, Two Waits + Wait Due to WAIT Signal) Rev.5.00 Sep. 27, 2007 ...
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Burst Operation High-Speed Page Mode: When the burst enable bit (BE) of the DCR is set, burst accesses can be performed using high speed page mode. The timing is shown in figure 8.12. Wait cycles can be inserted during ...
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Bus State Controller (BSC) DRAM access Address Row RAS CASx Data Figure 8.13 DRAM Access Normal Operation (RAS Up Mode Address RAS CASx Data Rev.5.00 Sep. 27, 2007 Page 134 of 716 REJ09B0398-0500 CS ...
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Refresh Timing The bus state controller is equipped with a function to control refreshes of DRAM. CAS-before- RAS (CBR) refresh or self-refresh can be selected by setting the RTCSR's RMD bit. CAS-before-RAS Refresh: For CBR refreshes, set the RCR's ...
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Bus State Controller (BSC RAS CASx 8.5 Address/Data Multiplex I/O Space Access When the BCR1 register IOE bit is set to 1, the D15 to D0 pins can be used for multiplexed address/data I/O for ...
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Address CS3 AH RD Read Data WRx Write Data Figure 8.17 Address/Data Multiplex I/O Space Access Timing (No Waits Address output Address output Rev.5.00 Sep. 27, 2007 Page 137 of 716 ...
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Bus State Controller (BSC) 8.5.2 Wait State Control Setting the WCR controls waits during address/data multiplex I/O space accesses. Software wait and external wait insertion timing is the same as during ordinary space accesses. The timing for one software ...
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CS Assertion Extension The timing diagram when CS assertion extension is set for address/data multiplexed I/O space access is shown in figure 8.19 Address CS3 AH RD Read Data WRx Write Data Figure 8.19 Wait Timing for ...
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Bus State Controller (BSC) 8.6 Waits between Access Cycles When a read from a slow device is completed, data buffers may not go off in time to prevent data conflicts with the next access. If there is a data ...
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Address CSn CSm RD WRx Data CSn space read Figure 8.20 Idle Cycle Insertion Example IW31 and IW30 specify the number of idle cycles required after a CS3 space read either to read other external spaces, or ...
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Bus State Controller (BSC) 8.6.2 Simplification of Bus Cycle Start Detection For consecutive accesses of the same CS space, waits are inserted so that the number of idle cycles designated by the CW3 to CW0 bits of the BCR2 ...
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Bus Arbitration It has two internal bus masters, the CPU and the DMAC. The priority ranking for determining bus right transfer between these bus masters is: Refresh > DMAC > CPU 8.8 Memory Connection Examples Figures 8.22 to 8.27 ...
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Bus State Controller (BSC) Figure 8.24 8-Bit Data Bus Width SRAM Connection SH7014/16/17 Figure 8.25 16-Bit Data Bus Width SRAM Connection Rev.5.00 Sep. 27, 2007 Page 144 of 716 REJ09B0398-0500 123 k × 8 bits SH7014/16/17 CSn RD A0 ...
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Figure 8.26 8-Bit Data Bus Width DRAM Connection SH7014/16/17 Figure 8.27 16-Bit Data Bus Width DRAM Connection 8.9 On-chip Peripheral I/O Register Access On-chip peripheral I/O registers are accessed from the bus state controller, as shown in Table 8.5. Table ...
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Bus State Controller (BSC) 8.10 CPU Operation when Program Is in External Memory In the SH7014, SH7016, and SH7017 F-ZTAT™, two words (equivalent to two instructions) are normally fetched in a single instruction fetch. This is also true when ...
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Section 9 Direct Memory Access Controller (DMAC) 9.1 Overview The SH7014 includes an on-chip two-channel direct memory access controller (DMAC). The DMAC can be used in place of the CPU to perform high-speed data transfers among external devices equipped with ...
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Direct Memory Access Controller (DMAC) 9.1.2 Block Diagram Figure 9 block diagram of the DMAC. On-chip ROM* On-chip RAM On-chip peripheral module DREQ0, DREQ1 MTU SCI0, SCI1 A/D converter DEIn DACK0, DACK1 DRAK0, DRAK1 External ROM External ...
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Pin Configuration Table 9.1 shows the DMAC pins. Table 9.1 DMAC Pin Configuration Channel Name 0 DMA transfer request DMA transfer request acknowledge DREQ0 acceptance confirmation 1 DMA transfer request DMA transfer request acknowledge DREQ1 acceptance confirmation 9. Direct ...
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Direct Memory Access Controller (DMAC) 9.1.4 Register Configuration Table 9.2 summarizes the DMAC registers. DMAC has a total of 9 registers. Each channel has four control registers. One other control register is shared by all channels. Table 9.2 DMAC ...
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Register Descriptions 9.2.1 DMA Source Address Registers 0, 1 (SAR0, SAR1) DMA source address registers 0, 1 (SAR0, SAR1) are 32-bit read/write registers that specify the source address of a DMA transfer. These registers have a count function, and ...
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Direct Memory Access Controller (DMAC) 9.2.2 DMA Destination Address Registers 0, 1 (DAR0, DAR1) DMA destination address registers 0, 1 (DAR0, DAR1) are 32-bit read/write registers that specify the destination address of a DMA transfer. These registers have a ...
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DMA Transfer Count Registers 0, 1 (DMATCR0, DMATCR1) DMA transfer count registers 0, 1 (DMATCR0, DMATCR1) are 16-bit read/write registers that specify the transfer count for the channel (byte count, word count, or longword count). Specifying a H'000001 gives ...
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Direct Memory Access Controller (DMAC) 9.2.4 DMA Channel Control Registers 0, 1 (CHCR0, CHCR1) DMA channel control registers 0, 1 (CHCR0, CHCR1 32-bit read/write register where the operation and transmission of each channel is designated. Bits 31 ...
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Bit 18⎯Request Check Level (RL): Selects whether to output DRAK notifying external device of DREQ received, with active high or active low. Bit 18 RL Description 0 Output DRAK with active high 1 Output DRAK with active low Bit 17⎯Acknowledge ...
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Direct Memory Access Controller (DMAC) Bits 13 and 12⎯Source Address Mode 1, 0 (SM1 and SM0): These bits specify increment/decrement of the DMA transfer source address. These bit specifications are ignored when transferring data from an external device to ...
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Bit 6⎯DREQ Select (DS): Sets the sampling method for the DREQ pin in external request mode to either low-level detection or falling-edge detection. When specifying an on-chip peripheral module or auto-request as the transfer request source, this bit setting is ...
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Direct Memory Access Controller (DMAC) Bit 1⎯Transfer End Flag (TE): This bit is set to 1 after the number of data transfers specified by the DMATCR. At this time, if the IE bit is set interrupt ...
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DMAC Operation Register (DMAOR) The DMAOR is a 16-bit read/write register that specifies the transfer mode of the DMAC. Bits this register always read as 0. The write value should always be 0. Register values ...
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Direct Memory Access Controller (DMAC) Bit 1⎯NMI Flag (NMIF): Indicates input of an NMI. This bit is set irrespective of whether the DMAC is operating or suspended. If this bit is set during a data transfer, transfers on all ...
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Operation When there is a DMA transfer request, the DMAC starts the transfer according to the predetermined channel priority order; when the transfer end conditions are satisfied, it ends the transfer. Transfers can be requested in three modes: auto-request, ...
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Direct Memory Access Controller (DMAC) Figure 9 flowchart of this procedure. Start Initial settings (SAR, DAR, DMATCR, CHCR, DMAOR) DE, DME = 1 and NMIF, AE Yes Transfer request 1 occurs?* Yes Transfer (1 ...
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DMA Transfer Requests DMA transfer requests are usually generated in either the data transfer source or destination, but they can also be generated by devices and on-chip peripheral modules that are neither the source nor the destination. Transfers can ...
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Direct Memory Access Controller (DMAC) On-Chip Peripheral Module Request Mode: In this mode a transfer is performed at the transfer request signal (interrupt request signal on-chip peripheral module. As indicated in table 9.4, there are eight transfer ...
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When an on-chip peripheral module's interrupt request signal is used as a DMA transfer request signal, interrupts for the CPU are not generated. When a DMA transfer is conducted corresponding with one of the transfer request signals in table 9.4, ...
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Direct Memory Access Controller (DMAC) Address Modes Single Address Mode: In the single address mode, both the transfer source and destination are external; one (selectable) is accessed by a DACK signal while the other is accessed by an address. ...