M306H3FCFP Renesas Electronics Corporation., M306H3FCFP Datasheet
M306H3FCFP
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M306H3FCFP Summary of contents
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Protection Figure 2.6.1. PRCR Register ...
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Watchdog Timer ...
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M306H3MC-XXXFP/FCFP CPU clock HOLD Write to WDTS register RESET Figure 2.8.1. Watchdog Timer Block Diagram Watchdog timer control register Note 1: The WDC5 bit is always “1” (warm start) no matter how ...
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Serial I/O 2.11.1 UARTi (i ...
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Figure 2.11.1. UARTi Block Diagram ...
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SP SP PAR SP SP PAR Figure 2.11.2. UARTi Transmit/Receive Unit ...
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Figure 2.11.3. U0TB to U2TB Register, U0RB to U2RB Register, and U0BRG to U2BRG Register ...
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Figure 2.11.4. U0MR to U2MR Register and U0C0 to U2C0 Register ...
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Figure 2.11.5. U0C1 to U2C1 Registers ...
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Figure 2.11.6. UCON Register and U0SMR to U2SMR Registers ...
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Figure 2.11.7. U0SMR2 to U2SMR2 Registers and U0SMR3 to U2SMR3 Registers ...
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Figure 2.11.8. U0SMR4 to U2SMR4 Registers ...
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Special Mode 3 (IE mode) Table 2.11.16. Registers to Be Used and Settings in IE Mode ...
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UiSMR register ABSCS bit (bus collision detect sampling clock select) (2) UiSMR register ACSE bit (auto clear of transmit enable bit) (3) UiSMR register SSS bit (Transmit start condition select) Figure 2.11.29. Bus Collision Detect Function-Related Bits ...
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Special Mode 4 (SIM Mode) (UART2) Table 2.11.17. SIM Mode Specifications ...
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Table 2.11.18. Registers to Be Used and Settings in SIM Mode ...
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Figure 2.11.30. Transmit and Receive Timing in SIM Mode ...
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Figure 2.11.31. SIM Interface Connection (a) Parity Error Signal Output Figure 2.11.32. Parity Error Signal Output Timing ...
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Format Figure 2.11.33. SIM Interface Format ...
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CRC Calculation Figure 2.13.1. CRC Circuit Block Diagram Figure 2.13.2. CRCD Register and CRCIN Register ...
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Setup procedure and CRC operation when generating CRC code “80C4 Figure 2.13.3. CRC Calculation ” 16 ...
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