HD6433048F Renesas Electronics Corporation., HD6433048F Datasheet
HD6433048F
Available stocks
Related parts for HD6433048F
HD6433048F Summary of contents
Page 1
REJ09B0325-0300 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 8 Rev. 3.00 Revision Date: Sep ...
Page 2
Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...
Page 3
General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test ...
Page 4
Rev. 3.00 Sep 27, 2006 page iv of xxvi ...
Page 5
The H8/3048B Group is a series of high-performance microcontrollers that integrate system supporting functions together with an H8/300H CPU core. In addition, the H8/3048F-ONE is equipped with an on-chip emulator (E10T) * The H8/300H CPU has a 32-bit internal architecture ...
Page 6
Notes on using the on-chip emulator (E10T) installed in the H8/3048F-ONE H8/3048 Group products and H8/3048B Group products have different specifications regarding the pin arrangement (pin 1, VCL), flash memory, and maximum operating frequency. Refer to Comparison of H8/3048 Group ...
Page 7
Comparison of H8/3048 Group Product Specifications There are eight members of the H8/3048 Group; the H8/3048F-ZTAT (H8/3048F * ONE * 2 ), H8/3048ZTAT, H8/3048 mask ROM version, H8/3048B mask ROM version, H8/3047 mask ROM version, H8/3045 mask ROM version, and ...
Page 8
Hardware Manual ROM Type ZTAT RAM Capacity 4 kbytes H8/3048: 4 kbytes H8/3047: 4 kbytes H8/3045: 2 kbytes H8/3044: 2 kbytes ROM Capacity 128 kbytes H8/3048: 128 kbytes H8/3047: 96 kbytes H8/3045: 64 kbytes H8/3044: 32 kbytes Flash Memory — ...
Page 9
Main Revisions for This Edition Item Page All — 1.3.1 Pin 8 Arrangement Figure 1.3 H8/3048B Group Pin Arrangement (FP- 100B or TFP-100B, Top View) 1.3.3 Pin Functions 18, 19 Table 1.4 Pin Functions 1.4.2 Product Type 21 Names and ...
Page 10
Item Page 5.5.4 Usage Notes on 120 External Interrupts Figure 5.9 IRQnF Flag When Interrupt Processing Is Not Conducted 10.2.3 Timer Mode 335 Register (TMDR) Bit 6—Phase Counting Mode Flag (MDF) 13.2.8 Bit Rate 473, Register (BRR) 475 Table 13.3 ...
Page 11
Item Page 13.3.3 Multiprocessor 495 Communication Figure 13.11 Example of SCI Transmit Operation (8-Bit Data with Multiprocessor Bit and One Stop Bit) 13.3.4 Synchronous 500 Operation Clock 14.2.3 Serial Mode 521 Register (SMR) Bit 7—GSM Mode (GM) 18.5.1 Flash Memory ...
Page 12
Item Page 21.2 Electrical 675 to Characteristics of 689 H8/3048B (Mask ROM) 21.2.2 DC 678 Characteristics Table 21.13 DC Characteristics (2) B.1 Addresses (For 742 H8/3048F-ONE, H8/3048B Mask ROM Version) B.3 Function 829 ADCR ADCR 829 SYSCR 833 Rev. 3.00 ...
Page 13
Section 1 Overview ............................................................................................................. 1.1 Overview........................................................................................................................... 1.2 Block Diagram .................................................................................................................. 1.3 Pin Description.................................................................................................................. 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Assignments in Each Mode ........................................................................... 1.3.3 Pin Functions ....................................................................................................... 15 1.4 Notes on H8/3048F-ONE (Single Power Supply) ............................................................ 20 1.4.1 Voltage ...
Page 14
Effective Address Calculation ............................................................................. 58 2.8 Processing States............................................................................................................... 62 2.8.1 Overview.............................................................................................................. 62 2.8.2 Program Execution State...................................................................................... 62 2.8.3 Exception-Handling State .................................................................................... 63 2.8.4 Exception-Handling Sequences ........................................................................... 64 2.8.5 Bus-Released State............................................................................................... 65 2.8.6 Reset State............................................................................................................ 66 2.8.7 Power-Down State ............................................................................................... ...
Page 15
Interrupts ........................................................................................................................... 88 4.4 Trap Instruction................................................................................................................. 89 4.5 Stack Status after Exception Handling.............................................................................. 89 4.6 Notes on Stack Usage ....................................................................................................... 90 Section 5 Interrupt Controller 5.1 Overview........................................................................................................................... 91 5.1.1 Features................................................................................................................ 91 5.1.2 Block Diagram ..................................................................................................... 92 5.1.3 Pin Configuration................................................................................................. ...
Page 16
Wait Control Register (WCR).............................................................................. 128 6.2.4 Wait State Controller Enable Register (WCER) .................................................. 129 6.2.5 Bus Release Control Register (BRCR) ................................................................ 130 6.2.6 Chip Select Control Register (CSCR).................................................................. 132 6.3 Operation .......................................................................................................................... 133 6.3.1 Area Division ....................................................................................................... 133 6.3.2 ...
Page 17
Functional Overview............................................................................................ 201 8.1.4 Input/Output Pins ................................................................................................. 203 8.1.5 Register Configuration......................................................................................... 203 8.2 Register Descriptions (Short Address Mode).................................................................... 205 8.2.1 Memory Address Registers (MAR) ..................................................................... 205 8.2.2 I/O Address Registers (IOAR) ............................................................................. 206 8.2.3 Execute Transfer Count Registers (ETCR).......................................................... ...
Page 18
Port 1................................................................................................................................. 263 9.2.1 Overview.............................................................................................................. 263 9.2.2 Register Descriptions ........................................................................................... 264 9.3 Port 2................................................................................................................................. 266 9.3.1 Overview.............................................................................................................. 266 9.3.2 Register Descriptions ........................................................................................... 267 9.4 Port 3................................................................................................................................. 270 9.4.1 Overview.............................................................................................................. 270 9.4.2 Register Descriptions ........................................................................................... 270 9.5 Port 4................................................................................................................................. 272 ...
Page 19
Register Configuration......................................................................................... 328 10.2 Register Descriptions ........................................................................................................ 331 10.2.1 Timer Start Register (TSTR)................................................................................ 331 10.2.2 Timer Synchro Register (TSNC) ......................................................................... 332 10.2.3 Timer Mode Register (TMDR) ............................................................................ 334 10.2.4 Timer Function Control Register (TFCR)............................................................ 337 10.2.5 Timer Output Master ...
Page 20
Port A Data Direction Register (PADDR) ........................................................... 419 11.2.2 Port A Data Register (PADR) .............................................................................. 419 11.2.3 Port B Data Direction Register (PBDDR)............................................................ 420 11.2.4 Port B Data Register (PBDR) .............................................................................. 420 11.2.5 Next Data Register A (NDRA) ............................................................................ ...
Page 21
Section 13 Serial Communication Interface 13.1 Overview........................................................................................................................... 455 13.1.1 Features................................................................................................................ 455 13.1.2 Block Diagram ..................................................................................................... 457 13.1.3 Input/Output Pins ................................................................................................. 458 13.1.4 Register Configuration......................................................................................... 458 13.2 Register Descriptions ........................................................................................................ 459 13.2.1 Receive Shift Register (RSR) .............................................................................. 459 13.2.2 Receive Data ...
Page 22
Usage Notes ...................................................................................................................... 538 Section 15 A/D Converter 15.1 Overview........................................................................................................................... 541 15.1.1 Features................................................................................................................ 541 15.1.2 Block Diagram ..................................................................................................... 542 15.1.3 Input Pins ............................................................................................................. 543 15.1.4 Register Configuration......................................................................................... 544 15.2 Register Descriptions ........................................................................................................ 545 15.2.1 A/D Data Registers A to ...
Page 23
Section 18 ROM (H8/3048F-ONE: Single Power Supply, H8/3048B Mask ROM Version) 18.1 Flash Memory Overview .................................................................................................. 573 18.1.1 Notes on H8/3048F-ONE (Single Power Supply) ............................................... 573 18.1.2 Mode Pin Settings ................................................................................................ 574 18.2 Flash Memory Features..................................................................................................... 575 18.2.1 Block Diagram ...
Page 24
Notes when Converting the F-ZTAT (Single Power Supply) Application Software to the Mask-ROM Versions .............................................................................................. 627 Section 19 Clock Pulse Generator 19.1 Overview........................................................................................................................... 629 19.1.1 Block Diagram ..................................................................................................... 630 19.2 Oscillator Circuit............................................................................................................... 630 19.2.1 Connecting a Crystal Resonator........................................................................... 630 ...
Page 25
Section 21 Electrical Characteristics 21.1 Electrical Characteristics of H8/3048F-ONE (Single-Power Supply) .............................. 655 21.1.1 Absolute Maximum Ratings ................................................................................ 655 21.1.2 DC Characteristics ............................................................................................... 656 21.1.3 AC Characteristics ............................................................................................... 663 21.1.4 A/D Conversion Characteristics........................................................................... 669 21.1.5 D/A Conversion Characteristics........................................................................... 670 21.1.6 ...
Page 26
C.6 Port 6 Block Diagrams...................................................................................................... 842 C.7 Port 7 Block Diagrams...................................................................................................... 846 C.8 Port 8 Block Diagrams...................................................................................................... 847 C.9 Port 9 Block Diagrams...................................................................................................... 850 C.10 Port A Block Diagrams ..................................................................................................... 854 C.11 Port B Block Diagrams ..................................................................................................... 858 Appendix D ...
Page 27
Overview The H8/3048B Group is a series of microcontrollers (MCUs) that integrate system supporting functions together with an H8/300H CPU core having an original Renesas Technology architecture. In addition, the H8/3048F-ONE is equipped with an on-chip emulator (E10T) * ...
Page 28
Section 1 Overview Table 1.1 Features Feature Description CPU Upward-compatible with the H8/300 CPU at the object-code level General-register machine Sixteen 16-bit general registers (also usable as sixteen 8-bit registers + eight 16-bit registers or eight 32- bit registers) High-speed ...
Page 29
Feature Description Refresh DRAM refresh controller Directly connectable to 16-bit-wide DRAM CAS-before-RAS refresh Self-refresh mode selectable Pseudo-static RAM refresh Self-refresh mode selectable Usable as an interval timer DMA controller Short address mode (DMAC) Maximum four channels available Selection of I/O ...
Page 30
Section 1 Overview Feature Description Programmable Maximum 16-bit pulse output, using ITU as time base timing pattern Up to four 4-bit pulse output groups (or one 16-bit group, or two 8-bit groups) controller (TPC) Non-overlap mode available Output data can ...
Page 31
Feature Description Power-down Sleep mode state Software standby mode Hardware standby mode Module standby function Programmable system clock frequency division Other features On-chip clock pulse generator Product lineup Model (5 V) HD64F3048BTE HD64F3048BVTE 100-pin TQFP (TFP-100B) HD64F3048BF HD6433048BTE HD6433048BVTE 100-pin ...
Page 32
Section 1 Overview 1.2 Block Diagram Figure 1.1 shows an internal block diagram EXTAL XTAL STBY RES *1 RESO/FWE NMI P6 /LWR 6 P6 /HWR /BACK ...
Page 33
Pin Description 1.3.1 Pin Arrangement Figure 1.3 shows the pin arrangement of the H8/3048B Group. The pin arrangement of the H8/3048B Group is shown in figure 1.3. Differences in the H8/3048 Group pin arrangements are shown in table 1.2. ...
Page 34
Section 1 Overview REF ...
Page 35
Pin Assignments in Each Mode Table 1.3 lists the pin assignments in each mode. Table 1.3 Pin Assignments in Each Mode (FP-100B or TFP-100B) Pin No. Mode 1 Mode 2 Mode ...
Page 36
Section 1 Overview Pin Mode 1 Mode 2 Mode DREQ DREQ DREQ / / ...
Page 37
Pin Mode 1 Mode 2 Mode 3 No ...
Page 38
Section 1 Overview Pin Mode 1 Mode 2 Mode 3 No ...
Page 39
Pin Mode 1 Mode 2 Mode ...
Page 40
Section 1 Overview Notes: Pins marked NC should be left unconnected. For details on PROM mode see section 18, ROM (H8/3048F-ONE: Single Power Supply, H8/3048B Mask ROM Version modes and 6 the P4 after a ...
Page 41
Pin Functions Table 1.4 summarizes the pin functions. For the H8/3048B Group which operates the external capacitor is required for the V Table 1.4 Pin Functions Type Symbol Power Internal step- V ...
Page 42
Section 1 Overview Type Symbol Operating mode control RES System control RESO (RESO FWE * 3 STBY BREQ BACK Interrupts NMI IRQ to 5 IRQ 0 Address bus ...
Page 43
Type Symbol Bus control HWR LWR WAIT RFSH Refresh controller HWR LWR Pin No. I/O Name and Function 99, Output Chip select: Select signals for areas 7 ...
Page 44
Section 1 Overview Type Symbol DREQ DMA controller , 1 DREQ (DMAC) 0 TEND , 1 TEND 0 16-bit integrated TCLKD to timer unit (ITU) TCLKA TIOCA to 4 TIOCA 0 TIOCB to 4 TIOCB 0 TOCXA 4 TOCXB 4 ...
Page 45
Type Symbol A/D and D/A V REF converters I/O ports ...
Page 46
Section 1 Overview 1.4 Notes on H8/3048F-ONE (Single Power Supply) There are two models of the H8/3048F-ZTAT with on-chip flash memory: a dual power supply model (H8/3048F) and single power supply model (H8/3048F-ONE). Points to be noted when using the ...
Page 47
Product Type Names and Markings Table 1.5 shows examples of product type names and markings for the H8/3048F (dual power supply model), H8/3048F-ONE (single power supply), and the differences in flash memory programming power source. Table 1.5 Differences in ...
Page 48
Section 1 Overview Table 1.6 Differences between H8/3048F and H8/3048F-ONE Models with Dual Power Supply: H8/3048F * 1 Item Pin Pin specifications Pin 10: V /RESO PP ROM/RAM 128-kbyte flash memory with dual power supply, RAM: 4 ...
Page 49
Models with Dual Power Supply: H8/3048F * 1 Item Write Before writing, sets the block with the processing address to be written to EBR1/EBR2 FLMCR FLMCR (H'FF40 EBR EBR1 (H'FF42) LB7 LB6 LB5 LB4 LB3 ...
Page 50
Section 1 Overview Models with Dual Power Supply: H8/3048F * 1 Item Division of RAM On-chip RAM emulation block H'EF10 H'F000 H'F1FF H'FF0F Reset during The RES signal must be kept low during operation at least 6 system clock (6 ...
Page 51
Models with Dual Power Supply: H8/3048F * 1 Item Clock oscillator Setting of standby timer select settling time bits (SYSCR STS2 STS2 STS1 to STS0 Details on flash Refer to section ...
Page 52
Section 1 Overview 1.4.4 V Pin CL The H8/3048B Group 5 V operation models have a V internal voltage stabilization capacitor must be connected. The method of connecting the external capacitor is shown in figure 1.4. Do not connect the ...
Page 53
External capacitor operation model Figure 1.5 Difference between 5 V and 3 V Operation Models 1.4.5 Note on Changeover to H8/3048 Group Mask ROM Version Care is required when changing from the H8/3048F-ONE with ...
Page 54
Section 1 Overview 1.5 Setting Oscillation Settling Wait Time When software standby mode is used, after exiting software standby mode a wait period must be provided to allow the clock to stabilize. Select the length of time for which the ...
Page 55
Overview The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ...
Page 56
Section 2 CPU 16 16-bit register-register multiply: 32 ÷ 16-bit register-register divide: Two CPU operating modes Normal mode (not available in the H8/3048B Group) Advanced mode Low-power mode Transition to power-down state by SLEEP instruction 2.1.2 Differences from H8/300 CPU ...
Page 57
CPU Operating Modes The H8/300H CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports Mbytes. See figure 2.1. The H8/3048B Group can be used only in ...
Page 58
Section 2 CPU 2.3 Address Space The maximum address space of the H8/300H CPU is 16 Mbytes. The H8/3048B Group has various operating modes (MCU modes), some providing a 1-Mbyte address space, the others supporting the full 16 Mbytes. Figure ...
Page 59
Register Configuration 2.4.1 Overview The H8/300H CPU has the internal registers shown in figure 2.3. There are two types of registers: general registers and control registers. General Registers (ERn) 15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 Control ...
Page 60
Section 2 CPU 2.4.2 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used without distinction between data registers and address registers. When a general register is used as ...
Page 61
General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.5 shows the stack. SP (ER7) 2.4.3 Control Registers The control registers are ...
Page 62
Section 2 CPU executed, the H flag is set there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is ...
Page 63
Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … byte operand data. ...
Page 64
Section 2 CPU General Data Type Register Data Format Word data Rn 15 Word data En MSB 31 Longword data ERn MSB Legend: ERn: General register En: General register E Rn: General register R RnH: General register RH RnL: General ...
Page 65
Memory Data Formats Figure 2.8 shows the data formats on memory. The H8/300H CPU can access word data and longword data on memory, but word or longword data must begin at an even address attempt is made ...
Page 66
Section 2 CPU 2.6 Instruction Set 2.6.1 Instruction Set Overview The H8/300H CPU has 62 types of instructions, which are classified in table 2.1. Table 2.1 Instruction Classification Function Instruction MOV, PUSH * Data transfer Arithmetic operations ADD, SUB, ADDX, ...
Page 67
Instructions and Addressing Modes Table 2.2 indicates the instructions available in the H8/300H CPU. Table 2.2 Instructions and Addressing Modes Function Instruction Data MOV BWL transfer POP, PUSH — MOVFPE * , — MOVTPE * Arithmetic ADD, CMP BWL ...
Page 68
Section 2 CPU 2.6.3 Tables of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The operation notation used in these tables is defined next. Operation Notation General register (destination General register ...
Page 69
Table 2.3 Data Transfer Instructions Size * Instruction MOV B/W/L MOVFPE B MOVTPE B POP W/L PUSH W/L Note: * Size refers to the operand size. B: Byte W: Word L: Longword Function (EAs) Rd, Rs (EAd) Moves data between ...
Page 70
Section 2 CPU Table 2.4 Arithmetic Operation Instructions Size * Instruction ADD, SUB B/W/L ADDX, SUBX B INC, DEC B/W/L ADDS, SUBS L DAA, DAS B MULXU B/W MULXS B/W DIVXU B/W DIVXS B/W Rev. 3.00 Sep 27, 2006 page ...
Page 71
Size * Instruction CMP B/W/L NEG B/W/L EXTS W/L EXTU W/L Note: * Size refers to the operand size. B: Byte W: Word L: Longword Function Rd – Rs, Rd – #IMM Compares data in a general register with data ...
Page 72
Section 2 CPU Table 2.5 Logic Operation Instructions Size * Instruction AND B/W/L OR B/W/L XOR B/W/L NOT B/W/L Note: * Size refers to the operand size. B: Byte W: Word L: Longword Table 2.6 Shift Instructions Size * Instruction ...
Page 73
Table 2.7 Bit Manipulation Instructions Size * Instruction BSET B BCLR B BNOT B BTST B BAND B BIAND B BOR B BIOR B Function 1 (<bit-No.> of <EAd>) Sets a specified bit in a general register or memory operand ...
Page 74
Section 2 CPU Size * Instruction BXOR B BIXOR B BLD B BILD B BST B BIST B Note: * Size refers to the operand size. B: Byte Rev. 3.00 Sep 27, 2006 page 48 of 872 REJ09B0325-0300 Function C ...
Page 75
Table 2.8 Branching Instructions Instruction Size Bcc — JMP — BSR — JSR — RTS — Function Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic Description BRA (BT) Always (true) ...
Page 76
Section 2 CPU Table 2.9 System Control Instructions Size * Instruction TRAPA — RTE — SLEEP — LDC B/W STC B/W ANDC B ORC B XORC B NOP — Note: * Size refers to the operand size. B: Byte W: ...
Page 77
Table 2.10 Block Transfer Instruction Instruction Size EEPMOV.B — EEPMOV.W — Function if R4L 0 then repeat @ER5+ @ER6+, R4L – 1 until R4L = 0 else next then repeat @ER5+ @ER6+, R4 – 1 until R4 ...
Page 78
Section 2 CPU 2.6.4 Basic Instruction Formats The H8/300H instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (OP field), a register field (r field), an effective address extension (EA field), and a condition field (cc). ...
Page 79
Notes on Use of Bit Manipulation Instructions The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, modify a bit in the byte, then write the byte back. Care is required when these instructions are used ...
Page 80
Section 2 CPU After Execution of BCLR Instruction Input/output Output Output DDR Explanation of BCLR Instruction To execute the BCLR instruction, the CPU begins by reading P4DDR. Since P4DDR is a write- ...
Page 81
Table 2.11 Addressing Modes No. Addressing Mode 1 Register direct 2 Register indirect 3 Register indirect with displacement 4 Register indirect with post-increment Register indirect with pre-decrement 5 Absolute address 6 Immediate 7 Program-counter relative 8 Memory indirect 1. Register ...
Page 82
Section 2 CPU 4. Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @–ERn Register indirect with post-increment—@ERn+ The register field of the instruction code specifies an address register (ERn) the lower 24 bits of which contain the address of a memory ...
Page 83
Immediate—#xx:8, #xx:16, or #xx:32 The instruction code contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The instruction codes of the ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. The instruction codes of ...
Page 84
Section 2 CPU When a word-size or longword-size memory operand is specified, or when a branch address is specified, if the specified memory address is odd, the least significant bit is regarded as 0. The accessed data or instruction code ...
Page 85
Table 2.13 Effective Address Calculation Addressing Mode and No. Instruction Format 1 Register direct (Rn Register indirect (@ERn Register indirect with displacement @(d:16, ERn)/@(d:24, ERn disp 4. Register indirect with post-increment ...
Page 86
Section 2 CPU Addressing Mode and No. Instruction Format 5 Absolute address @aa:8 op abs @aa:16 op abs @aa:24 op abs 6 Immediate #xx:8, #xx:16, or #xx:32 op IMM 7 Program-counter relative @(d:8, PC) or @(d:16, PC) op disp Rev. ...
Page 87
Addressing Mode and No. Instruction Format 8 Memory indirect @@aa:8 Normal mode op abs Advanced mode op abs Legend: r, rm, rn: Register field op: Operation field disp: Displacement IMM: Immediate data abs: Absolute address Effective Address Calculation 23 8 ...
Page 88
Section 2 CPU 2.8 Processing States 2.8.1 Overview The H8/300H CPU has five processing states: the program execution state, exception-handling state, power-down state, reset state, and bus-released state. The power-down state includes sleep mode, software standby mode, and hardware standby ...
Page 89
Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal program flow due to a reset, interrupt, or trap instruction. The CPU fetches a starting address from the exception vector table and ...
Page 90
Section 2 CPU End of bus release Bus request Bus-released state End of exception handling Exception-handling state RES = High Reset state * 1 Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs ...
Page 91
CPU sets both the I bit and the UI bit in the condition code register to 1. Then the CPU fetches a start address from the exception vector table and execution branches to that address. ...
Page 92
Section 2 CPU 2.8.6 Reset State When the RES input goes low all current processing stops and the CPU enters the reset state. The I bit in the condition code register is set reset. All interrupts ...
Page 93
Basic Operational Timing 2.9.1 Overview The H8/300H CPU operates according to the system clock ( ). The interval from one rise of the system clock to the next rise is referred “state.” A memory cycle or ...
Page 94
Section 2 CPU Address bus AS RD HWR LWR , , , Figure 2.16 Pin States during On-Chip Memory Access 2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in three states. ...
Page 95
Address bus AS RD HWR LWR , , , Figure 2.18 Pin States during Access to On-Chip Supporting Modules 2.9.4 Access to External Address Space The external address space is divided into eight areas (areas ...
Page 96
Section 2 CPU Rev. 3.00 Sep 27, 2006 page 70 of 872 REJ09B0325-0300 ...
Page 97
Section 3 MCU Operating Modes 3.1 Overview 3.1.1 Operating Mode Selection The H8/3048B Group has seven operating modes (modes that are selected by the mode pins ( indicated in table 3.1. The input ...
Page 98
Section 3 MCU Operating Modes Modes 5 and 6 are externally expanded modes that enable access to external memory and peripheral devices and also enable access to the on-chip ROM. Mode 5 supports a maximum address space of 1 Mbyte. ...
Page 99
Bits 7 and 6—Reserved: Read-only bits, always read as 1. Bits 5 to 3—Reserved: Read-only bits, always read as 0. Bits 2 to 0—Mode Select (MDS2 to MDS0): These bits indicate the logic levels at pins MD ...
Page 100
Section 3 MCU Operating Modes Bit 7—Software Standby (SSBY): Enables transition to software standby mode. (For further information about software standby mode see section 20, Power-Down State.) When software standby mode is exited by an external interrupt, this bit remains ...
Page 101
Bit 2—NMI Edge Select (NMIEG): Selects the valid edge of the NMI input. Bit 2: NMIEG Description 0 An interrupt is requested at the falling edge of NMI 1 An interrupt is requested at the rising edge of NMI Bit ...
Page 102
Section 3 MCU Operating Modes 3.4.4 Mode 4 Ports 1, 2, and 5 and part of port A function as address pins A maximum 16-Mbyte address space. The initial bus mode after a reset is 16 bits, with 16-bit access ...
Page 103
Pin Functions in Each Operating Mode The pin functions of ports and port A vary depending on the operating mode. Table 3.3 indicates their functions in each operating mode. Table 3.3 Pin Functions in Each Mode ...
Page 104
Section 3 MCU Operating Modes Modes 1 and 2 (1-Mbyte expanded modes with on-chip ROM disabled) H'00000 Vector area H'000FF H'07FFF H'1FFFF H'20000 H'3FFFF H'40000 H'5FFFF H'60000 External address space H'7FFFF H'80000 H'9FFFF H'A0000 H'BFFFF H'C0000 H'DFFFF H'E0000 H'F8000 H'FEF0F ...
Page 105
Mode 5 (1-Mbyte expanded mode with on-chip ROM enabled) H'00000 Vector area H'000FF On-chip ROM H'07FFF Area 0 H'1FFFF H'20000 Area 1 H'3FFFF H'40000 Area 2 H'5FFFF H'60000 External address Area 3 space H'7FFFF H'80000 Area 4 H'9FFFF H'A0000 Area ...
Page 106
Section 3 MCU Operating Modes Rev. 3.00 Sep 27, 2006 page 80 of 872 REJ09B0325-0300 ...
Page 107
Section 4 Exception Handling 4.1 Overview 4.1.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or ...
Page 108
Section 4 Exception Handling 4.1.3 Exception Vector Table The exception sources are classified as shown in figure 4.1. Different vectors are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. • Reset Exception • ...
Page 109
Table 4.2 Exception Vector Table Exception Source Reset Reserved for system use External interrupt (NMI) Trap instruction (4 sources) External interrupt IRQ 0 External interrupt IRQ 1 External interrupt IRQ 2 External interrupt IRQ 3 External interrupt IRQ 4 External ...
Page 110
Section 4 Exception Handling 4.2 Reset 4.2.1 Overview A reset is the highest-priority exception. When the RES pin goes low, all processing halts and the chip enters the reset state. A reset initializes the internal state of the CPU and ...
Page 111
Figure 4.2 Reset Sequence (Modes 1 and 3) Section 4 Exception Handling Rev. 3.00 Sep 27, 2006 page 85 of 872 REJ09B0325-0300 ...
Page 112
Section 4 Exception Handling RES Address bus RD HWR LWR , High (1), (3) Address of reset vector: (1) = H'000000, (3) = H'000002 (2), (4) Start address (contents of reset vector) (5) Start address ...
Page 113
RES Internal address bus Internal read signal Internal write signal Internal data bus (16 bits wide) (1), (3) Address of reset vector ((1) = H'000000, (2) = H'000002) (2), (4) Start address (contents of reset vector) (5) Start address (6) ...
Page 114
Section 4 Exception Handling 4.3 Interrupts Interrupt exception handling can be requested by seven external sources (NMI, IRQ 30 internal sources in the on-chip supporting modules. Figure 4.5 classifies the interrupt sources and indicates the number of interrupts of each ...
Page 115
Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. If the UE bit is set the system control register (SYSCR), the exception handling sequence sets the I bit CCR. ...
Page 116
Section 4 Exception Handling 4.6 Notes on Stack Usage When accessing word data or longword data, the H8/3048B Group regards the lowest address bit as 0. The stack should always be accessed by word access or longword access, and the ...
Page 117
Section 5 Interrupt Controller 5.1 Overview 5.1.1 Features The interrupt controller has the following features: Interrupt priority registers (IPRs) for setting interrupt priorities Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis in interrupt ...
Page 118
Section 5 Interrupt Controller 5.1.2 Block Diagram Figure 5.1 shows a block diagram of the interrupt controller. ISCR NMI input IRQ input section ISR OVF TME . . . . . . . . . . ADI ADIE Interrupt controller ...
Page 119
Pin Configuration Table 5.1 lists the interrupt pins. Table 5.1 Interrupt Pins Name Nonmaskable interrupt External interrupt request Note: * For the H8/3048F-ONE (single power supply with flash memory), the NMI input may be prohibited. For ...
Page 120
Section 5 Interrupt Controller 5.2 Register Descriptions 5.2.1 System Control Register (SYSCR) SYSCR is an 8-bit readable/writable register that controls software standby mode, selects the action of the UI bit in CCR, selects the NMI edge, and enables or disables ...
Page 121
Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in CCR as a user bit or an interrupt mask bit. Bit 3: UE Description 0 UI bit in CCR is used as interrupt mask bit 1 UI ...
Page 122
Section 5 Interrupt Controller Interrupt Priority Register A (IPRA) IPRA is an 8-bit readable/writable register in which interrupt priority levels can be set. Bit 7 IPRA7 IPRA6 Initial value 0 Read/Write R/W R/W Priority level A6 Selects the priority level ...
Page 123
Bit 7—Priority Level A7 (IPRA7): Selects the priority level of IRQ Bit 7: IPRA7 Description 0 IRQ interrupt requests have priority level 0 (low priority IRQ interrupt requests have priority level 1 (high priority) 0 Bit 6—Priority Level ...
Page 124
Section 5 Interrupt Controller Bit 2—Priority Level A2 (IPRA2): Selects the priority level of ITU channel 0 interrupt requests. Bit 2: IPRA2 Description 0 ITU channel 0 interrupt requests have priority level 0 (low priority) (Initial value) 1 ITU channel ...
Page 125
Interrupt Priority Register B (IPRB) IPRB is an 8-bit readable/writable register in which interrupt priority levels can be set. Bit 7 IPRB7 IPRB6 Initial value 0 Read/Write R/W R/W Priority level B6 Selects the priority level of ITU channel 4 ...
Page 126
Section 5 Interrupt Controller Bit 7—Priority Level B7 (IPRB7): Selects the priority level of ITU channel 3 interrupt requests. Bit 7: IPRB7 Description 0 ITU channel 3 interrupt requests have priority level 0 (low priority) (Initial value) 1 ITU channel ...
Page 127
Bit 3—Priority Level B3 (IPRB3): Selects the priority level of SCI channel 0 interrupt requests. Bit 3: IPRB3 Description 0 SCI0 interrupt requests have priority level 0 (low priority) 1 SCI0 interrupt requests have priority level 1 (high priority) Bit ...
Page 128
Section 5 Interrupt Controller 5.2.3 IRQ Status Register (ISR) ISR is an 8-bit readable/writable register that indicates the status of IRQ requests. Bit 7 Initial value 0 Read/Write Reserved bits Note: * Only 0 can be written, to clear flags. ...
Page 129
IRQ Enable Register (IER) IER is an 8-bit readable/writable register that enables or disables IRQ Bit 7 Initial value 0 Read/Write R/W R/W Reserved bits IER is initialized to H' reset and in hardware standby mode. Bits ...
Page 130
Section 5 Interrupt Controller 5.2.5 IRQ Sense Control Register (ISCR) ISCR is an 8-bit readable/writable register that selects level sensing or falling-edge sensing of the inputs at pins IRQ to IRQ . 5 0 Bit 7 Initial value 0 Read/Write ...
Page 131
Interrupt Sources The interrupt sources include external interrupts (NMI, IRQ 5.3.1 External Interrupts There are seven external interrupts: NMI, and IRQ can be used to exit software standby mode. NMI NMI is the highest-priority interrupt and is always accepted, ...
Page 132
Section 5 Interrupt Controller IRQn input Note Figure 5.2 Block Diagram of Interrupts IRQ Figure 5.3 shows the timing of the setting of the interrupt flags (IRQnF). IRQn input pin IRQnF Note ...
Page 133
Internal Interrupts Thirty internal interrupts are requested from the on-chip supporting modules. Each on-chip supporting module has status flags for indicating interrupt status, and enable bits for enabling or disabling interrupts. Interrupt priority levels can be assigned in IPRA ...
Page 134
Section 5 Interrupt Controller Table 5.3 Interrupt Sources, Vector Addresses, and Priority Interrupt Source Origin NMI External pins IRQ 0 IRQ 1 IRQ 2 IRQ 3 IRQ 4 IRQ 5 Reserved — WOVI Watchdog (interval timer) timer CMI Refresh (compare ...
Page 135
Interrupt Source Origin IMIA2 ITU channel 2 (compare match/ input capture A2) IMIB2 (compare match/ input capture B2) OVI2 (overflow 2) Reserved — IMIA3 ITU channel 3 (compare match/ input capture A3) IMIB3 (compare match/ input capture B3) OVI3 (overflow ...
Page 136
Section 5 Interrupt Controller Interrupt Source Origin ERI0 SCI channel 0 (receive error 0) RXI0 (receive data full 0) TXI0 (transmit data empty 0) TEI0 (transmit end 0) ERI1 SCI channel 1 (receive error 1) RXI1 (receive data full 1) ...
Page 137
Interrupt Operation 5.4.1 Interrupt Handling Process The H8/3048B Group handles interrupts differently depending on the setting of the UE bit. When interrupts are controlled by the I bit. When interrupts are controlled by ...
Page 138
Section 5 Interrupt Controller Priority level 1? No IRQ 0 Yes IRQ Figure 5.4 Process Up to Interrupt Acceptance when Rev. 3.00 Sep 27, 2006 page 112 of 872 REJ09B0325-0300 Program execution state Interrupt requested? Yes Yes ...
Page 139
If an interrupt condition occurs and the corresponding interrupt enable bit is set interrupt request is sent to the interrupt controller. When the interrupt controller receives one or more interrupt requests, it selects the highest- priority request, ...
Page 140
Section 5 Interrupt Controller a. All interrupts are unmasked I 0 Figure 5.5 Interrupt Masking State Transitions (Example) Figure 5 flowchart showing how interrupts are accepted when interrupt condition occurs and the corresponding ...
Page 141
Program execution state Interrupt requested? Yes Priority level 1? Yes No IRQ 0 Yes No IRQ 1 Yes ADI Yes Yes Yes Save PC and CCR I Read vector address Branch to interrupt service routine Figure 5.6 ...
Page 142
Section 5 Interrupt Controller 5.4.2 Interrupt Sequence Figure 5.7 shows the interrupt sequence in mode 2 when the program code and stack are in an external memory area accessed in two states via a 16-bit bus. Figure 5.7 Interrupt Sequence ...
Page 143
Interrupt Response Time Table 5.5 indicates the interrupt response time from the occurrence of an interrupt request until the first instruction of the interrupt service routine is executed. Table 5.5 Interrupt Response Time No. Item 1 Interrupt priority decision ...
Page 144
Section 5 Interrupt Controller 5.5 Usage Notes 5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction When an instruction clears an interrupt enable bit disable the interrupt, the interrupt is not disabled until after execution of the instruction is ...
Page 145
Instructions That Inhibit Interrupts The LDC, ANDC, ORC, and XORC instructions inhibit interrupts. When an interrupt occurs, after determining the interrupt priority, the interrupt controller requests a CPU interrupt. If the CPU is currently executing one of these interrupt-inhibiting ...
Page 146
Section 5 Interrupt Controller Occurrence conditions 1. When IRQaF = 1, for the IRQaF flag to clear, ISR register read is executed. Thereafter interrupt processing is carried out and IRQbF flag clears. 2. IRQaF flag clear and IRQbF flag generation ...
Page 147
In this situation, conduct one of the following countermeasures. Countermeasure 1: When clears IRQaF flag, do not use the bit manipulation instruction, read the ISR in bytes. Then write a value in bytes which sets IRQaF flag to 0 and ...
Page 148
Section 5 Interrupt Controller 3. This chip has a break function to implement on-board emulation for specific customers. To use this break function, execute the BRK instruction (H'5770). Note that the BRK instruction is usually undefined. Therefore, if the CPU ...
Page 149
Section 6 Bus Controller 6.1 Overview The H8/3048B Group has an on-chip bus controller that divides the address space into eight areas and can assign different bus specifications to each. This enables different types of memory to be connected easily. ...
Page 150
Section 6 Bus Controller 6.1.2 Block Diagram Figure 6.1 shows a block diagram of the bus controller. Internal address bus Area decoder Chip select control signals WAIT Internal signals CPU bus request signal DMAC bus request signal Refresh controller bus ...
Page 151
Input/Output Pins Table 6.1 summarizes the bus controller’s input/output pins. Table 6.1 Bus Controller Pins Name Abbreviation Chip select Address strobe RD Read HWR High write LWR Low write WAIT Wait ...
Page 152
Section 6 Bus Controller 6.1.4 Register Configuration Table 6.2 summarizes the bus controller’s registers. Table 6.2 Bus Controller Registers Address * Name H'FFEC Bus width control register H'FFED Access state control register H'FFEE Wait control register H'FFEF Wait state controller ...
Page 153
Bits 7 to 0—Areas Bus Width Control (ABW7 to ABW0): These bits select 8-bit access or 16-bit access to the corresponding address areas. Bits ABW7 to ABW0 Description 0 Areas are ...
Page 154
Section 6 Bus Controller 6.2.3 Wait Control Register (WCR) WCR is an 8-bit readable/writable register that selects the wait mode for the wait-state controller (WSC) and specifies the number of wait states. Bit 7 Initial value 1 Read/Write Reserved bits ...
Page 155
Wait State Controller Enable Register (WCER) WCER is an 8-bit readable/writable register that enables or disables wait-state control of external three-state-access areas by the wait-state controller. Bit 7 WCE7 WCE6 Initial value 1 Read/Write R/W WCER is initialized to ...
Page 156
Section 6 Bus Controller 6.2.5 Bus Release Control Register (BRCR) BRCR is an 8-bit readable/writable register that enables address output on bus lines A enables or disables release of the bus to an external device. Bit 7 A23E Initial value ...
Page 157
Bit 5—Address 21 Enable (A21E): Enables this bit enables A address output from PA 21 modified and PA has its ordinary input/output functions. 6 Bit 5: A21E Description the ...
Page 158
Section 6 Bus Controller 6.2.6 Chip Select Control Register (CSCR) CSCR is an 8-bit readable/writable register that enables or disables output of chip select signals chip select signal (CS 7 ...
Page 159
Operation 6.3.1 Area Division The external address space is divided into areas Each area has a size of 128 kbytes in the 1-Mbyte modes Mbytes in the 16-Mbyte modes. Figure 6.2 shows a general ...
Page 160
Section 6 Bus Controller to CS Chip select signals (CS 7 can be selected in ABWCR, ASTCR, WCER, and WCR as shown in table 6.3. Table 6.3 Bus Specifications ABWCR ASTCR WCER ABWn ASTn WCEn 0 0 — ...
Page 161
Chip Select Signals For each of areas the H8/3048B Group can output a chip select signal (CS low to indicate when the area is selected. Figure 6.3 shows the output timing 7). ...
Page 162
Section 6 Bus Controller 6.3.3 Data Bus The H8/3048B Group allows either 8-bit access or 16-bit access to be designated for each of areas 8-bit-access area uses the upper data bus (D upper data bus (D ...
Page 163
Bus Control Signal Timing 8-Bit, Three-State-Access Areas Figure 6.4 shows the timing of bus control signals for an 8-bit, three-state-access area. The upper ) is used to access these areas. The LWR pin is always high. Wait states can ...
Page 164
Section 6 Bus Controller 8-Bit, Two-State-Access Areas Figure 6.5 shows the timing of bus control signals for an 8-bit, two-state-access area. The upper ) is used to access these areas. The LWR pin is always high. Wait states address bus ...
Page 165
Three-State-Access Areas Figures 6.6 to 6.8 show the timing of bus control signals for a 16-bit, three-state-access area. In these areas, the upper address bus (D address bus ( used to access odd addresses. Wait ...
Page 166
Section 6 Bus Controller Address bus Read access HWR LWR Write access Note ...
Page 167
Address bus Read access HWR LWR Write access Note Figure 6.8 ...
Page 168
Section 6 Bus Controller 16-Bit, Two-State-Access Areas Figures 6.9 to 6.11 show the timing of bus control signals for a 16-bit, two-state-access area. In these areas, the upper address bus (D address bus ( used to ...
Page 169
Address bus CSn AS RD Read access HWR LWR Write access Note Figure 6.10 Bus ...
Page 170
Section 6 Bus Controller Address bus Read access HWR LWR Write access Note Figure 6.11 ...
Page 171
Wait Modes Four wait modes can be selected as shown in table 6.5. Table 6.5 Wait Mode Selection ASTCR WCER ASTn Bit WCEn Bit WMS1 Bit WMS0 Bit WSC Control 0 — — — ...
Page 172
Section 6 Bus Controller WAIT pin Address bus AS RD Read access Data bus HWR , LWR Write access Data bus Note: * Arrows indicate time of sampling of the Wait Modes in Areas Where Wait-State Controller is Enabled External ...
Page 173
Figure 6.13 shows the timing when the wait count is 1 (WC1 = 0, WC0 = 1) and one additional wait state is inserted by WAIT input. WAIT pin Address bus AS RD Read access Data bus HWR, LWR Write ...
Page 174
Section 6 Bus Controller Pin Auto-Wait Mode: If the WAIT pin is low, the number of wait states (T WC1 and WC0 are inserted. In pin auto-wait mode, if the WAIT pin is low at the fall of the system ...
Page 175
Programmable Wait Mode: The number of wait states (T inserted in all accesses to external three-state-access areas. Figure 6.15 shows the timing when the wait count is 1 (WC1 = 0, WC0 = 1). Address bus AS RD Read access ...
Page 176
Section 6 Bus Controller Example of Wait State Control Settings A reset initializes ASTCR and WCER to H'FF and WCR to H'F3, selecting programmable wait mode and three wait states for all areas. Software can select other wait modes for ...
Page 177
Interconnections with Memory (Example) For each area, the bus controller can select two- or three-state access and 16-bit data bus width. In three-state-access areas, wait states can be inserted in a variety of modes, simplifying the ...
Page 178
Section 6 Bus Controller H8/3048B Group WAIT RD HWR LWR Figure 6.18 Interconnections with Memory (Example) Rev. 3.00 Sep ...
Page 179
Bus Arbiter Operation The bus controller has a built-in bus arbiter that arbitrates between different bus masters. There are four bus masters: the CPU, DMA controller (DMAC), refresh controller, and an external bus master. When a bus master has ...
Page 180
Section 6 Bus Controller DMAC When the DMAC receives an activation request, it requests the bus right from the bus arbiter. If the DMAC is bus master and the refresh controller or an external bus master requests the bus, the ...
Page 181
Figure 6.19 shows the timing when the bus right is requested by an external bus master during a read cycle in a two-state-access area. There is a minimum interval of two states from when the BREQ signal goes low until ...
Page 182
Section 6 Bus Controller 6.4 Usage Notes 6.4.1 Connection to Dynamic RAM and Pseudo-Static RAM A different bus control signal timing applies when dynamic RAM or pseudo-static RAM is connected to area 3. For details see section 7, Refresh Controller. ...
Page 183
DDR Write Timing Data written to a data direction register (DDR) to change a CS input, or vice versa, takes effect starting from the T shows the timing when the CS Address bus CS 1 High-impedance BRCR Write Timing Data ...
Page 184
Section 6 Bus Controller BREQ Input Timing BREQ BREQ BREQ 6.4.3 After driving the BREQ pin low, hold it low until BACK goes low. If BREQ returns to the high level before BACK goes low, the bus arbiter may operate ...
Page 185
Section 7 Refresh Controller 7.1 Overview The H8/3048B Group has an on-chip refresh controller that enables direct connection of 16-bit- wide DRAM or pseudo-static RAM (PSRAM). DRAM or pseudo-static RAM can be directly connected to area 3 of the external ...
Page 186
Section 7 Refresh Controller Features as a Pseudo-Static RAM Refresh Controller: RFSH signal output for refresh control Software-selectable refresh interval Software-selectable self-refresh mode Wait states can be inserted Features as an Interval Timer: Refresh timer counter (RTCNT) can be used ...
Page 187
Block Diagram Figure 7.1 shows a block diagram of the refresh controller. /2, /8, /32, /128, /512, /2048, /4096 Clock selector Comparator Legend: RTCNT: Refresh timer counter RTCOR: Refresh time constant register RTMCSR: Refresh timer control/status register RFSHCR: Refresh ...
Page 188
Section 7 Refresh Controller 7.1.3 Input/Output Pins Table 7.1 summarizes the refresh controller’s input/output pins. Table 7.1 Refresh Controller Pins Signal Pin Name RFSH Refresh HWR Upper write/upper column address strobe LWR Lower write/lower column address strobe RD Column address ...
Page 189
Register Descriptions 7.2.1 Refresh Control Register (RFSHCR) RFSHCR is an 8-bit readable/writable register that selects the operating mode of the refresh controller. Bit 7 SRFMD PSRAME Initial value 0 Read/Write R/W R/W PSRAM enable and DRAM enable These bits ...
Page 190
Section 7 Refresh Controller Bit 7—Self-Refresh Mode (SRFMD): Specifies DRAM or pseudo-static RAM self-refresh during software standby mode. When PSRAME = 1 and DRAME = 0, after the SRFMD bit is set to 1, pseudo-static RAM can be self-refreshed when ...
Page 191
Bit 3—Address Multiplex Mode Select (M9/M8 The setting of this bit is valid when PSRAME = 0 and DRAME = 1. This bit is write-disabled when the PSRAME or DRAME bit is set Bit 3: ...
Page 192
Section 7 Refresh Controller 7.2.2 Refresh Timer Control/Status Register (RTMCSR) RTMCSR is an 8-bit readable/writable register that selects the clock source for RTCNT. It also enables or disables interrupt requests when the refresh controller is used as an interval timer. ...
Page 193
Bit 6—Compare Match Interrupt Enable (CMIE): Enables or disables the CMI interrupt requested when the CMF flag is set RTMCSR. The CMIE bit is always cleared to 0 when PSRAME = 1 or DRAME = 1. Bit ...
Page 194
Section 7 Refresh Controller 7.2.3 Refresh Timer Counter (RTCNT) RTCNT is an 8-bit readable/writable up-counter. Bit 7 Initial value 0 Read/Write R/W RTCNT is an up-counter that is incremented by an internal clock selected by bits CKS2 to CKS0 in ...
Page 195
Operation 7.3.1 Overview One of three functions can be selected for the H8/3048B Group refresh controller: interfacing to DRAM connected to area 3, interfacing to pseudo-static RAM connected to area 3, or interval timing. Table 7.3 summarizes the register ...
Page 196
Section 7 Refresh Controller DRAM Interface To set up area 3 for connection to 16-bit-wide DRAM, initialize RTCOR, RTMCSR, and RFSHCR in that order, clearing bit PSRAME to 0 and setting bit DRAME to 1. Set bit ...
Page 197
DRAM Refresh Control Refresh Request Interval and Refresh Cycle Execution The refresh request interval is determined by the settings of RTCOR and bits CKS2 to CKS0 in RTMCSR. Figure 7.2 illustrates the refresh request interval. RTCOR H'00 Refresh request ...
Page 198
Section 7 Refresh Controller When a refresh request occurs in the refresh request pending state, the refresh controller acquires the bus right, then executes a refresh cycle. If another refresh request occurs during execution of the refresh cycle ...
Page 199
Table 7.5 Address Multiplexing Address Pins Address signals during row address output Address signals M9/ during column address output M9/ Address bus ...
Page 200
Section 7 Refresh Controller CAS CAS and 2WE CAS Modes 2CAS The CAS/WE bit in RFSHCR can select two control modes for 16-bit-wide DRAM: one using UCAS and LCAS; the other using UW and LW. These DRAM ...