M34283G2 Renesas Electronics Corporation., M34283G2 Datasheet
M34283G2
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M34283G2 Summary of contents
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... Minimum instruction execution time ............................ 8.0 s (at f 4.0 MHz, system clock = f(X IN • Supply voltage ................................................. 1 3.6 V • Subroutine nesting ..................................................... 4 levels Part number M34283G2-XXXGP M34283G2GP Rev.1.01 Mar 20, 2006 page REJ03B0109-0101 • Timer Timer 1 ................................................................... 8-bit timer 7 key matrix and has (This has a reload register and carrier wave output auto-control function) Timer 2 ...
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Group PIN CONFIGURATION (TOP VIEW OUT Rev.1.01 Mar 20, 2006 page REJ03B0109-0101 ...
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Group BLOCK DIAGRAM Rev.1.01 Mar 20, 2006 page REJ03B0109-0101 ...
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Group PERFORMANCE OVERVIEW Parameter Number of basic instructions Minimum instruction execution time Memory sizes ROM RAM Input/Output D –D Output 0 3 ports D –D I –E Input Output 0 1 ...
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Group CONNECTIONS OF UNUSED PINS Pin Open. D – Connect Open (Set the output latch to “1” – Open (Set the output latch to “0” ). Connect ...
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Group PORT BLOCK DIAGRAMS Decoder Register Y SD instruction RD instruction CLD instruction Register Y Decoder SD instruction RD instruction CLD instruction Skip decision (SZD instruction) Key-on wakeup Register (Note 3) OEA T instruction ...
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Group FUNCTION BLOCK OPERATIONS CPU (1) Arithmetic logic unit (ALU) The arithmetic logic unit ALU performs 4-bit arithmetic such as 4-bit data addition, comparison, and bit manipulation. (2) Register A and carry flag Register 4-bit register ...
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Group (5) Most significant ROM code reference enable flag (URS) URS flag controls whether to refer to the contents of the most significant 1 bit (bit 8) of ROM code when executing the TABP p instruction. If URS flag ...
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Group (8) Program counter (PC) Program counter (PC) is used to specify a ROM address (page and address). It determines a sequence in which instructions stored in ROM are read binary counter that increments the number ...
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... Rev.1.01 Mar 20, 2006 page REJ03B0109-0101 0000 007 0080 00 0100 Pages 017 0180 15 the special page for 07 Fig. 10 ROM map of M34283G2 RAM 64 words 4 bits (256 bits) Fig. 11 RAM map Subroutine special page ...
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Group TIMERS The 4283 Group has the programmable timer. • Programmable timer The programmable timer has a reload register and enables the frequency dividing ratio to be set decremented from a setting value n. When it underflows ...
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Group V1 (Note CARRY 1 1 Reload register R1 (8) (TAB1) Register (Note 1/2 1 (TAB2) CAR flag SCAR instruction RCAR instruction ...
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Group Table 4 Control registers related to timer Timer control register V1 V1 Carrier wave output auto-control bit 2 V1 Timer 1 count source selection bit 1 V1 Timer 1 control bit 0 Timer control register V2 V2 Carrier ...
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Group (3) Timer 1 Timer 8-bit binary down counter with the timer 1 reload register (R1). When timer is stopped, data can be set simultaneously in timer 1 and the reload register (R1) with the T1AB ...
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Group “ 1 ” “ 0 ” “ H ” ...
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Group In this case, the following is set; • To expand “H” interval of carrier wave is invalid (V2 • Timer 2 carrier wave generation function is valid (V2 • Count source X /2 selected (V2 IN • “L” ...
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Group WATCHDOG TIMER Watchdog timer provides a method to reset and restart the system when a program runs wild. Watchdog timer consists of 14-bit timer (WDT) and watchdog timer flags (WDF1, WDF2). Watchdog timer downcounts the instruction clock (INSTCK) ...
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Group RESET FUNCTION The 4283 Group has the power-on reset circuit, though it does not have RESET pin. System reset is performed automatically at power-on, and software starts program from address 0 in page 0. In order to make ...
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Group • Program counter (PC) .............................................................. Address 0 in page 0 is set to program counter. • Power down flag (P) ................................................................. • Timer 1 underflow flag (T1F) ................................................... • Timer 2 underflow flag (T2F) ................................................... • Timer control ...
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Group RAM BACK-UP MODE The 4283 Group has the RAM back-up mode. When the POF instruction is executed, system enters the RAM back-up state. As oscillation stops retaining RAM, the functions and states of reset circuit at RAM back-up ...
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Group (4) Return signal An external wakeup signal is used to return from the RAM back-up mode. Table 8 shows the return condition for each return source. Table 8 Return source and return condition Return source Return condition Ports ...
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Group CLOCK CONTROL The clock control circuit consists of the following circuits. • System clock generating circuit • Control circuit to stop the clock oscillation • Control circuit to return from the RAM back-up state ...
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Group LIST OF PRECAUTIONS Noise and latch-up prevention Connect a capacitor on the following condition to prevent noise and latch-up; • connect a bypass capacitor (approx. 0.01 F) between pins V and V at the shortest distance ...
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Group Power-on reset Under the following condition, the system reset occurs by the built-in the power-on reset circuit of this product; - when the supply voltage (V ) rises from 2.2 V, within DD 1 ms. ...
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Group INSTRUCTIONS The 4283 Group has the 68 instructions. Each instruction is described as follows; (1) List of instruction function (2) Machine instructions (index by alphabet) (3) Machine instructions (index by function) (4) Instruction code table SYMBOL The symbols ...
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Group LIST OF INSTRUCTION FUNCTION Mnemonic Function Groupi n g TAB (A) (B) TBA (B) (A) TAY (A) (Y) TYA (Y) (A) TEAB (ER – (ER – TABE (B) (ER –ER ...
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Group Grouping Mnemonic Function (A) = (M(DP)) ? SEAM SEA – ( ( ...
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Group LIST OF INSTRUCTION FUNCTION (CONTINUED) Groupi n g Mnemonic Function (D) 0 CLD RD (D(Y (D(Y ( (D(Y SZD ( ...
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Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET (Add n and accumulator) Instrunction D 8 code Operation: (A) ( (Add accumulator and Memory) Instrunction ...
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Group BA a (Branch to address a + Accumulator) Instrunction D 8 code Operation: ( – – ...
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Group BML p, a (Branch and Mark Long to address a in page p) Instrunction D 8 code Operation: (SK(SP)) (PC) (SP) ...
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Group CMA (CoMplement of Accumulator) Instrunction D 8 code Operation: (A) (A) DEY (DEcrement register Y) Instrunction D 8 code Operation: (Y) (Y) – 1 IAE (Input ...
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Group INY (INcrement register Y) Instrunction D 8 code Operation: (Y) ( (Load n in Accumulator) Instrunction D 8 code Operation: (A) ...
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Group NOP (No OPeration) Instrunction D 8 code Operation: (PC) (PC OEA (Output port E from Accumulator) Instrunction D 8 code Operation ...
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Group RAR (Rotate Accumulator Right) Instrunction D 8 code Operation (Reset Bit) Instrunction D 8 code ...
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Group RD (Reset port D specified by register Y) Instrunction D 8 code Operation: (D(Y)) 0 However, ( (ReTurn from subroutine) Instrunction D 8 code ...
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Group SC (Set Carry flag) Instrunction D 8 code Operation: (CY) 1 SCAR (Set CAR flag) Instrunction D 8 code Operation: (CAR (Set port D ...
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Group SEAM (Skip Equal, Accumulator with Memory) Instrunction D 8 code Operation: (A) = (M(DP)) ? SNZP (Skip if Non Zero condition of Power down flag) Instrunction D 8 code ...
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Group SZB j (Skip if Zero, Bit) Instrunction D 8 code Operation: (Mj(DP SZC (Skip if Zero, Carry flag) Instrunction D 8 code 0 0 ...
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Group T2AB (Transfer data to timer 2 and register R2L from Accumulator and register B) Instrunction D 8 code Operation: (R2L –R2L ) ( (R2L –R2L ) ( (T2 ...
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Group TAB1 (Transfer data to Accumulator and register B from timer 1) Instrunction D 8 code Operation: (B) (T1 – (A) (T1 – TAB2 (Transfer data to ...
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Group TAM j (Transfer data to Accumulator from Memory) Instrunction D 8 code Operation: (A) (M(DP)) (X) (X)EXOR( TAY (Transfer data to Accumulator from register Y) Instrunction D ...
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Group TEAB (Transfer data to register E from Accumulator and register B) Instrunction D 8 code Operation: (ER – (ER – TLOA (Transfer data to ...
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Group TV1A (Transfer data to register V1 from Accumulator) Instrunction D 8 code Operation: (V1 – – TV2A (Transfer data to register V2 from Accumulator) Instrunction ...
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Group WRST (Watchdog timer ReSeT) Instrunction D 8 code Operation: (WDF1) 0 XAM j (eXchange Accumulator and Memory data) Instrunction D 8 code Operation: (A) (M(DP)) (X) ...
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Group MACHINE INSTRUCTIONS (INDEX BY FUNCTION) Parameter Mnemonic instructions TAB TBA TAY 0 0 ...
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Group Skip condition – – Transfers the contents of register B to register A. – – Transfers the contents of register A to register B. – – Transfers the contents of register Y to register A. – – Transfers ...
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Group MACHINE INSTRUCTIONS (CONTINUED) Parameter Mnemonic instructions TABP ...
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Group Skip condition Continuous – Loads the value n in the immediate field to register A. description When the LA instructions are continuously coded and executed, only the first LA instruction is executed and other LA instructions coded continuously ...
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Group MACHINE INSTRUCTIONS (CONTINUED) Parameter Mnemonic instructions SZB j 0 ...
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Group Skip condition – – Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). – – Clears (0) the contents of bit j (bit specified by the value j ...
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Group MACHINE INSTRUCTIONS (CONTINUED) Parameter Mnemonic instructions BML ...
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Group Skip condition – – Call the subroutine in page 2 : Calls the subroutine at address a in page 2. – – Call the subroutine : Calls the subroutine at address a in page p. – – Call ...
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Group MACHINE INSTRUCTIONS (CONTINUED) Parameter Mnemonic instructions TAB2 TV2A SNZT2 ...
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Group Skip condition – – Transfers the contents of timer 2 to registers A and B. – – Transfers the contents of register A to registers V2. (T2F – Clears T2F flag and skips the next instruction ...
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Group Parameter Mnemonic instructions NOP POF SNZP CCK 0 ...
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Group Skip condition – – No operation – – Puts the system in RAM back-up state. ( – Skips the next instruction when P flag is “1.” After skipping, P flag remains unchanged. – – System clock ...
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Group INSTRUCTION CODE TABLE 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 D – – Hex notation SZB NOP BLA BL ...
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Group REGISTER STRUCTURE Timer control register V1 V1 Carrier wave output auto-control bit 2 Timer 1 count source selection bit Timer 1 control bit 0 Timer control register V2 V2 Carrier wave “H” interval expansion bit ...
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Group ABSOLUTE MAXIMUM RATINGS Symbol Parameter V Supply voltage DD V Input voltage I V Output voltage O P Power dissipation d T Operating temperature range opr T Storage temperature range stg RECOMMENDED OPERATING CONDITIONS (Ta = –20 °C ...
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Group ELECTRICAL CHARACTERISTICS (Ta = –20 ° ° unless otherwise noted) DD Symbol Parameter V “L” level output voltage Port CARR OL V “L” level output voltage X OL OUT V “H” level ...
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Group PACKAGE OUTLINE JEITA Package Code RENESAS Code P-LSSOP20-4.4x6.5-0.65 PLSP0020JB Index mark * Rev.1.01 Mar 20, 2006 page REJ03B0109-0101 Previous Code MASS[Typ.] 20P2F-A 0. NOTE) ...
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REVISION HISTORY Rev. Date Page 1.00 Jan. 07, 2005 – 1.01 Mar. 20, 2006 24 62 Description First edition issued. The followings of LIST OF PRECAUTIONS revised. (12)Overvoltage (12)QzROM revised. (13)Notes On ROM Code Protect added. Pages 27, 38, 52-55: ...
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...