MDS108AL Zarlink Semiconductor, MDS108AL Datasheet
MDS108AL
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MDS108AL Summary of contents
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... Provides port-based prioritization of packets ports Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved. Unmanaged 9-Port 10/100 Mbps MDS108AL - Input ports are defined to be high or low priority - Allows explicit identification of IP phone ports • ...
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... Operating at 66 MHz internally, and with a 66 MHz interface to the external SBRAM, the MDS108 sustains full wire- speed switching on all 9 ports. The chip is packaged in a small 208 pin Plastic Quad Flat-Pak (PQFP) package. MDS108 2 Zarlink Semiconductor Inc. Data Sheet ...
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... Buffer Mem Interface RMII Port Interfaces Zarlink Semiconductor Inc. Data Sheet 156 L_OE# L_WE# 154 VSS L_CLK 152 VDD L_A[17] 150 L_A[2] VSS 148 ...
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... VDD 60 M4_TXEN 61 M4_TXD[0] 62 M4_TXD[1] 63 M4_CRS_DV 64 M4_RXD[0] 65 M4_RXD[1] 66 VSS 67 M5_TXEN 68 M5_TXD[0] 69 M5_TXD[1] 70 M5_CRS_DV 4 Zarlink Semiconductor Inc. Data Sheet 71 M5_RXD[0] 72 M5_RXD[1] 73 VDD (CORE) 74 M6_TXEN 75 M6_TXD[0] 76 M6_TXD[1] 77 M6_CRS_DV 78 M6_RXD[0] 79 M6_RXD[1] 80 VSS (CORE) 81 M7_TXEN 82 M7_TXD[0] 83 M7_TXD[1] 84 M7_CRS_DV 85 M7_RXD[0] 86 M7_RXD[1] 87 VDD ...
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... L_D[6] 170 L_D[7] 171 VSS (CORE) 172 L_D[8] 173 L_D[9] 174 L_D[10] 175 VDD 176 L_D[11] 177 L_D[12] 5 Zarlink Semiconductor Inc. Data Sheet 178 L_D[13] 179 L_D[14] 180 VSS 181 L_D[15] 182 L_D[16] 183 L_D[17] 184 VDD (CORE) 185 L_D[18] 186 ...
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... MDS108 Figure 2 - MDS108 Block Diagram 6 Zarlink Semiconductor Inc. Data Sheet ...
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... Quality of Service The MDS108 applies Zarlink Semiconductor’s architecture to provide new QoS capabilities for unmanaged switch applications. Similar to the QoS capabilities of the other Zarlink chipset members, the MDS108 offers two transmit queues per output port. ...
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... IP precedence and DTR subfields are referred to as TOS/DS[0:2] and TOS/DS[3:5] in the IP TOS/DS byte Half Duplex mode, QoS scheduling functions are disabled by default. MDS108 1 to resolve the transmission priority 2 must be enabled using bit 7 in the Transmission Scheduling 8 Zarlink Semiconductor Inc. Data Sheet ...
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... WRED may cause some packet loss, but with no such head-of-line blocking problem. Which method of handling traffic congestion should be chosen will depend on the application. MDS108 Condition for Low Drop Percentage for Priority Queue High-Drop Packet @LPBT 72 buffers occupied 84 buffers occupied 9 Zarlink Semiconductor Inc. Data Sheet 1 . When flow control is Drop Percentage Drop Percentage for Low-Drop Packet 50% 0% 75% 25% ...
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... When port priorities are enabled, the remaining ports will provide QoS based upon the VLAN Tag or TOS DS field mappings in the configuration registers. Only those ports that have port priorities enabled will override the priority mappings. MDS108 10 Zarlink Semiconductor Inc. Data Sheet ...
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... The MDS108 also provides a safe fail-over mode for port trunking. If one of the two ports goes down, as identified by the port’s link status signal, then the MDS108 will switch all traffic over to the remaining port in the trunk. Thus, the trunk link is maintained, albeit at a lower effective bandwidth. MDS108 11 Zarlink Semiconductor Inc. Data Sheet ...
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... MDS108 Mirror_Control [2] Mirror_Control [ Table 2 - Port Mirroring Configuration 12 Zarlink Semiconductor Inc. Data Sheet Mirror_Control [ ...
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... A simple 2 wire serial interface is provided to allow the configuration of the MDS108 from an external EEPROM. The MDS108 utilizes bit EEPROM with an I MDS108 Xlink Data Rate L_A[10:9] Strap Level 100 Mbps 11 200 Mbps 10 300 Mbps 01 400 Mbps 00 Table 3 - XLink Port Strap Options 2 C interface. 13 Zarlink Semiconductor Inc. Data Sheet ...
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... DATA is sampled low and STROBE is rising, followed by DATA being sampled high when STROBE falls. 1. The 3-bit parallel interface is not "parallel" in the usual sense of the word actually a synchronous serial architecture. However, the MDS108 management interface adheres to IEEE 1284 parallel port standards. MDS108 1 . Figure 3 - Write Command Figure 4 - Read Command 14 Zarlink Semiconductor Inc. Data Sheet ...
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... BIST In-Progress 0: Normal Mode Bit 3 RAM error during BIST 1: RAM Error 0: No Error Bits [5:4] Reserved Bits [7:6] Revision number 00: Initial Silicon 01: Second Silicon MDS108 2 C interface. Some registers are only (Default = 0) (Default = 0) (Default = 0) (Default = Zarlink Semiconductor Inc. Data Sheet ...
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... WRED is triggered Use IP precedence subfield (TOS[0:2]) for Transmission Priority Use IP precedence subfield (TOS[0:2]) for Drop Level 2 C, Read/Write Number of frame buffers reserved for low-drop traffic 16 Zarlink Semiconductor Inc. Data Sheet (Default = 80) (Default = 3F) (Default = 0) (Default = 0) (Default 3F) ...
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... Use TOS instead of VLAN priority for IP packet 2 C, Read/Write Lower 8 bits of VLAN type code 2 C, Read/Write Upper 8 bits of VLAN type code 2 C, Read/Write 17 Zarlink Semiconductor Inc. Data Sheet (Default = 8) (Default = 000) (Default = 0) (Default = 00) (Default 81) (Default 0) (Default 0) (Default 0) (Default 0) (Default 0) (Default 0) (Default 0) ...
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... Port 0: Priority high low Bit 2 EN1 Port 1: Enable enabled Bit 3 P0 Port 1: Priority high low MDS108 2 C, Read/Write 2 C, Read/Write Read/Write 18 Zarlink Semiconductor Inc. Data Sheet (Default 0) (Default 0) (Default 0) (Default 0) (Default 0) (Default 0) (Default 0) (Default 0) (Default 0) (Default 0) (Default 0) (Default 0) (Default 0) (Default 0) ...
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... Permits a non-standard address for the Phy Status Register. When low and high Address bytes are 0, the MDS108 will use the standard address. Bit [7:0] Low order address byte MDS108 2 C, Read/Write 2 C, Read/Write 2 C, Read/Write 19 Zarlink Semiconductor Inc. Data Sheet (Default 0) (Default 0) (Default 0) (Default 0) (Default 0) (Default 0) (Default 0) (Default 0) (Default 0) (Default 0) ...
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... Mbps 0 – 100 Mbps 1 – Half Duplex 0 – Full Duplex 1 – Flow Control Off 0 – Flow Control On Port-based VLAN ID 20 Zarlink Semiconductor Inc. Data Sheet (Default 00) (Default 25) (Default 01) The default setting provides a 300 second aging time. (Default 0000) (Default 000) ...
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... Autonegotiate and advertise based on Bits [2:0] 1 – 10 Mbps 0 – 100 Mbps 1 – Half Duplex 0 – Full Duplex 1 – Flow Control Off 0 – Flow Control On Port-based VLAN Read/Write 21 Zarlink Semiconductor Inc. Data Sheet (Default 0000) (Default 000) (Default 0000) (Default 000) (Default 0000) ...
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... Full Duplex 1 – Flow Control Off 0 – Flow Control On Port-based VLAN Read/Write 1 – Force configuration based on Bits [2:0] 0 – Autonegotiate and advertise based on Bits [2:0] 1 – 10 Mbps 0 – 100 Mbps 22 Zarlink Semiconductor Inc. Data Sheet (Default 000) (Default 0000) (Default 000) (Default 0000) ...
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... Autonegotiate and advertise based on Bits [2:0] 1 – 10 Mbps 0 – 100 Mbps 1 – Half Duplex 0 – Full Duplex 1 – Flow Control Off 0 – Flow Control On Port-based VLAN ID 23 Zarlink Semiconductor Inc. Data Sheet (Default 000) (Default 0000) (Default 000) (Default 0000) (Default 000) ...
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... Mbps 0 – 100 Mbps 1 – Half Duplex 0 – Full Duplex 1 – Flow Control Off 0 – Flow Control On Port-based VLAN Read/Write (Default FF Read/Write (Default 00 Read/Write (Default 96 Read/Write (Default 8E) 24 Zarlink Semiconductor Inc. Data Sheet (Default 0000) (Default 000) ...
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... Address: h24 The calculation is [0x100 - ((sum of registers 0x00~0x23) & 0xFF)]. For example, based on the default register settings, the CHECKSUM value would be 0xEE. Bits [7:0] Checksum MDS108 2 C, Read/Write (Default 99 Read/Write (Default 9A Read/Write (Default 00) 25 Zarlink Semiconductor Inc. Data Sheet ...
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... Data Pin O, U, OD, 5 Acknowledge Pin I, U Port 0 Receive Data I, D Port 0 Carrier Sense and Data Valid O Port 0 Transmit Data O Port 0 Transmit Enable I, U Port 1 Receive Data I, D Port 1 Carrier Sense and Data Valid 26 Zarlink Semiconductor Inc. Data Sheet Name & Functions ...
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... Port 7 Carrier Sense and Data Valid O Port 7 Transmit Data O Port 7 Transmit Enable I, U Port 8 Receive Data O Port 8 Transmit Data O Port 8 Transmit Enable I, D Port 8 Receive Data Valid I, U Port 8 Receive Clock I/O, U Port 8 Transmit Clock 27 Zarlink Semiconductor Inc. Data Sheet Name & Functions ...
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... Leave as No Connect (NC) O Test Outputs I/O, U Test Outputs No Connect Input +3.3 Volt DC Supply for Core Logic (7 pins) Input +3.3 Volt DC Supply for I/O Pads (13 pins) Input Ground for Core Logic (7 pins) Input Ground for I/O Pads (13 pins) 28 Zarlink Semiconductor Inc. Data Sheet Name & Functions ...
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... M8_REFCLK input frequency is equal to 25% of the Port 8 speed (data rate) Port 8 Configuration Mode Reg. 10/100 M 2x 200 M 3x 300 M 4x 400 M MDS108 Speed Input/Output Output Input Input Input 29 Zarlink Semiconductor Inc. Data Sheet M8_REFCLK Freq. M_CLK/2 50 MHz 75 MHz 100 MHz ...
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... SBRAM Self Test Note 1: If the MDS108AL is configured from EEPROM preset (L_A[6] pulled down at reset), it will try to load its configuration from the EEPROM. If the EEPROM is blank or not preset, it will not boot up. The parallel port can be used to program the EEPROM at any time. ...
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... Thermal resistance with 2 m/s air flow Thermal resistance between junction and case jc MDS108 -65GC to +150C -40C to +85C +125C + (VDD +3.3 V) -0.5V to (VDD +0 -40C to +85 C AMBIENT Min. 2.4 2.0 < VDD) IN < OUT 31 Zarlink Semiconductor Inc. Data Sheet Typ. Max 580 0.4 VDD + 2.0 0 29.7 28.8 26.8 12.6 Unit MHz mA ...
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... 66. 100 M 32 Zarlink Semiconductor Inc. Data Sheet Note: L_CLK = SCLK M_MDC = SCLK/32 SCL = M_CLK/1000 Output L_CLK M_MDC =SCLK =SCLK/32 =SCLK =SCLK/32 =SCLK =SCLK/32 =SCLK =SCLK/32 =SCLK =SCLK/32 =SCLK ...
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... L_WE# output valid delay L9 L_OE# output valid delay Table 4 - Frame Buffer Memory Interface Timing MDS108 L_D[31:0] Figure 5 - Frame Buffer Memory Interface Parameter Min. (ns Zarlink Semiconductor Inc. Data Sheet 50 MHz Note Max. (ns ...
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... M8_TXCLK input fall time require *Inf. = infinite MDS108 50 MHz Min. (ns Table 5 - RMII Timing Requirements Figure 6 - Transmit Timing Parameter Table 6 - Transmit Timing Requirements 34 Zarlink Semiconductor Inc. Data Sheet Note: Max. (ns) Reference Input Clock Time Unit Min. ...
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... M8_RXCLK High wide 10 M8_RXCLK Low wide M8_RXCLK input rise time require M8_RXCLK input fall time require Table 7 - Receive Timing Requirements MDS108 Figure 7 - Receive Timing Time Min Zarlink Semiconductor Inc. Data Sheet Unit Max Inf. ...
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... Pin 1 indicator may be a corner chamfer, dot or both. 2. Controlling dimensions are in millimeters. 3. The top package body size may be smaller than the bottom package body size by a max. of 0.15 mm. 4. Dimension D1 and E1 do not include mould protusion. c Zarlink Semiconductor 2003 All rights reserved. ISSUE ACN DATE APPRD. = 0° ...
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