ADV7176 Analog Devices, ADV7176 Datasheet
ADV7176
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ADV7176 Summary of contents
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... CD Video/Karaoke Professional Studio Quality PC Video/Multimedia GENERAL DESCRIPTION The ADV7175/ADV7176 is an integrated digital video encoder that converts Digital CCIR-601 4:2:2 component video data into a standard analog baseband television signal compatible with world wide standards NTSC, PAL B/D/G/H/I, PAL M or PAL N. In addition to the composite output signal, there is the facility to out- put S-VHS Y/C video, YUV or RGB video ...
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... PAL MODE >50 dB Attenuation <0.06 dB Attenuation PAL MODE <40 dB Attenuation >0.1 dB Attenuation Lower Power Mode Lower Power Mode RMS Peak Periodic = 100 C. J correspondingly. DAC –2– = 1.235 150 . All specifications REF SET ADV7175/ADV7176 Min Typ Max Units 10 Bits 1 LSB 1 LSB ...
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... Timing reference points at 50% for inputs and –3– ADV7175/ADV7176 Units Condition % Referenced to 40 IRE NTSC PAL % Referenced to 714 mV (NTSC) % Referenced to 700 mV (PAL All specifications unless otherwise noted) ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV7175/ADV7176 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... MPU Port Serial Data Input/Output. TTL Address Input. This signal set up the LSB of the MPU address. The input resets the on chip timing generator and sets the ADV7175/ADV7176 into default mode. This is NTSC operation, Timing Slave Mode 0, 8-bit operation, 2 composite & S VHS out. ...
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... Functionally the ADV7175 and ADV7176 are the same with the exception that the ADV7175 can output the Macrovision (Revision 6.1/7.x) anticopy algorithm. The ADV7175/ADV7176 is fabricated CMOS pro- cess. Its monolithic CMOS construction ensures greater func- tionality with low power dissipation. ...
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... FREQUENCY – MHz Figure 9. NTSC/PAL Extended Mode Filter –7– ADV7175/ADV7176 0 TYPE A –20 TYPE B –40 –60 –80 –100 –120 FREQUENCY – MHz Figure 7. PAL Low-Pass Filter 0 –20 – ...
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... CLOCK. The inputs follow the sequence Cb0, Y0 Cr0, Y1 Cb1, Y2, etc. VIDEO TIMING DESCRIPTION The ADV7175/ADV7176 is intended to interface to off the shelf MPEG1 and MPEG2 Decoders consequence the ADV7175/ADV7176 accepts 4:2:2 YCrCb pixel data via a CCIR-656 pixel port and has several video timing modes of ...
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... Mode 0 (CCIR-656): Slave Option. (Timing Register 0 TR0 = The ADV7175/ADV7176 is controlled by the SAV (Start Active Video) and EAV (End Active Video) time codes in the pixel data. All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before and after each line during active picture and retrace ...
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... ADV7175/ADV7176 DISPLAY 622 623 624 625 H V EVEN FIELD F DISPLAY 309 310 311 312 ODD FIELD ANALOG VIDEO Figure 16. Timing Mode 0 Data Transitions (Master Mode) VERTICAL BLANK ODD FIELD VERTICAL BLANK 313 314 315 316 317 ...
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... In this mode the ADV7175/ADV7176 accepts horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input when HSYNC is low indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled the ADV7175/ADV7176 automatically blanks all normally blank lines as per CCIR-624. Mode 1 is illustrated in Figure 17 (NTSC) and Figure 18 (PAL). ...
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... HSYNC is low indicates a new frame i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled the ADV7175/ADV7176 automatically blanks all normally blank lines as per CCIR-624. Pixel data is latched on the rising clock edge following the timing signal transitions. Mode 1 is illustrated in Figure 17 (NTSC) and Figure 18 (PAL). Figure 19 illus- trates the HSYNC, BLANK and FIELD for an odd or even field transition relative to the pixel data ...
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... HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The BLANK signal is optional. When the BLANK input is disabled the ADV7175/ADV7176 automatically blanks all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 20 (NTSC) and Figure 21 (PAL). Figure 22 illustrates the HSYNC, BLANK and VSYNC for an even to odd field transition relative to the pixel data ...
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... In this mode the ADV7175/ADV7176 accepts or generates Horizontal SYNC and odd/even FIELD signals. A transition of the FIELD input when HSYNC is high indicates a new frame i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled the ADV7175/ADV7176 automatically blanks all normally blank lines as per CCIR-624. Mode 3 is illustrated in Figure 24 (NTSC) and Figure 25 (PAL). ...
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... BLANK FIELD EVEN FIELD (Continued from page 8) In addition the ADV7175/ADV7176 supports a PAL or NTSC square pixel operation in slave mode. The part requires an in- put pixel clock of 24.54 MHz for NTSC and an input pixel clock of 29.5 MHz for PAL. The internal horizontal line counters place the various video waveform sections in the cor- rect location for the new clock frequencies ...
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... Figure 27. The LSB sets either a read or write operation. Logic Level “1” corresponds to a read operation while Logic Level “0” corresponds to a write operation set by setting the ALSB pin of the ADV7175/ADV7176 to Logic Level “0” or Logic Level “1.” 1 ...
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... THESE BITS REGISTER ACCESSES The MPU can write to or read from all of the registers of the ADV7175/ADV7176 except the subaddress register which is a write only register. The subaddress register determines which register the next read or write operation accesses. All communi- cations with the part through the bus start with an access to the subaddress register ...
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... MODE REGISTER 0 (MR07–MR00) BIT DESCRIPTION Encode Mode Control (MR01–MR00): These bits are used to set up the encode mode. The ADV7175/ ADV7176 can be set up to output NTSC, PAL ( I), PAL (M) and PAL (N) standard video. Pedestal Control (MR02) This bit specifies whether a pedestal generated on the NTSC composite video signal ...
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... SCF TIMING REGISTER 0 (TR07–TR00) BIT DESCRIPTION = 3.5796 MHz Master/Slave Control (TR00) This bit controls whether the ADV7175/ADV7176 is in master 6 * 3.579545 10 or slave mode. Timing Mode Control (TR02–TR01) These bits control the timing mode of the ADV7175/ADV7176 These modes are described in the Timing and Control section of the data sheet ...
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... HSYNC output relative to the FIELD output rising edge. CED10 CED9 CED8 VSYNC Width (TR15–TR14) When the ADV7175/ADV7176 is in Timing Mode 2, these bits CED2 CED1 CED0 adjust the VSYNC pulse width. HSYNC to Pixel Data Adjust (TR17–TR16) This enables the HSYNC to be adjusted with respect to the pixel data ...
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... ZERO SHOULD BE WRITTEN TO THESE BITS DAC OUTPUT SWITCHING DAC A DAC B DAC C DAC D BLUE/COMP/U RED/CHROMA/V GREEN/LUMA/Y BLUE/COMP/U RED/CHROMA/V COMPOSITE Figure 40. Mode Register 3 –21– ADV7175/ADV7176 MR22 MR21 MR20 GENLOCK SELECTION 0 DISABLE GENLOCK 1 ENABLE SUBCARRIER RESET PIN 1 ENABLE RTC PIN SQUARE PIXEL CONTROL MR20 0 ...
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... For best performance, the outputs should each have a 75 load resistor connected to GND. These resistors should be placed as close as possible to the ADV7175/ADV7176 minimize reflections. The ADV7175/ADV7176 should have no inputs left floating. Any inputs that are not required should be tied to ground. ...
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... The circuit below can be used to generate a 13.5 MHz waveform using the 27 MHz clock and the HSYNC pulse. This waveform is guaranteed to produce the 13.5 MHz clock in synchronization with the 27 MHz clock. This 13.5 MHz clock can be used if 13.5 MHz clock is required by the MPEG decoder. This will guarantee that the Cr and Cb pixel information is input to the ADV7175/ADV7176 in the correct sequence. CLOCK HSYNC REV ...
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... These consist of two 8-bit bytes. The data for these bytes is stored in closed captioning data registers 0 and 1. The ADV7175/ADV7176 also supports the extended closed captioning operation which is active during even fields and is encoded on scan line 284. The data for this operation is stored in closed captioning extended data registers 0 and 1. ...
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... APPENDIX 3 NTSC WAVEFORMS (With Pedestal) Figure 44. NTSC Composite Video Levels Figure 45. NTSC Luma Video Levels 835mV (pk-pk) Figure 46. NTSC Chroma Video Levels Figure 47. NTSC RGB Video Levels –25– ADV7175/ADV7176 1268.1mV PEAK COMPOSITE 1048.4mV REF WHITE 714.2mV 387.6mV BLACK LEVEL BLANK LEVEL 334 ...
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... ADV7175/ADV7176 130.8 IRE 100 IRE 0 IRE –40 IRE 100 IRE 0 IRE –40 IRE 1101.6mV 307mV (pk-pk) 650mV 198.4mV 0mV 100 IRE 0 IRE –40 IRE NTSC WAVEFORMS (Without Pedestal) Figure 48. NTSC Composite Video Levels 714.2mV Figure 49. NTSC Luma Video Levels 903.2mV (pk-pk) Figure 50. NTSC Chroma Video Levels 715 ...
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... REV. A PAL WAVEFORMS Figure 52. PAL Composite Video Levels Figure 53. PAL Luma Video Levels 885mV (pk-pk) Figure 54. PAL Chroma Video Levels Figure 55. PAL RGB Video Levels –27– ADV7175/ADV7176 PEAK COMPOSITE REF WHITE 696.4mV BLANK/BLACK LEVEL SYNC LEVEL REF WHITE 696.4mV BLANK/BLACK LEVEL ...
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... ADV7175/ADV7176 The ADV7175/ADV7176 registers can be set depending on the user standard required. The following examples give the various register formats for several video standards. In each case the output is set to composite o/p with all DACs powered up and with the BLANK input control disabled. Ad- ditionally, the burst and color information are enabled on the output and the internal color bar generator is switched off ...
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... If an output filter is required for the composite output of the ADV7175/ADV7176. The following filter can be used. Plots of the filter characteristics can be produced on request. IN REV. A APPENDIX 5 OUTPUT FILTER 2.7µH 1µH 0.7µ 470pF 330pF Figure 56. Output Filter –29– ADV7175/ADV7176 OUT C 56pF ...
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... ADV7175/ADV7176 Figure 58. 100/75% Color Bars NTSC (Chrominance Only) APPENDIX 6 OUTPUT WAVEFORMS Figure 57. 100/75% Color Bars NTSC –30– REV. A ...
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... Figure 59. 100/75% Color Bars NTSC (Luminance Only) REV. A Figure 60. 100/75% Color Bars PAL –31– ADV7175/ADV7176 ...
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... ADV7175/ADV7176 Figure 61. Differential Phase and Gain Measurements (PAL) Figure 62. Vectorscope Measurements (PAL) –32– REV. A ...
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... REV. A Figure 63. Modulated Ramp Measurements (PAL) –33– ADV7175/ADV7176 ...
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... ADV7175/ADV7176 INDEX Contents GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 1 ADV7175/ADV7176 SPECIFICATIONS . . . . . . . . . . . . . . 2 TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . 3 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 4 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 PIN DESCRIPTION/PIN CONFIGURATION . . . . . . . . . 5 DATA PATH DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . 6 INTERNAL FILTER RESPONSE . . . . . . . . . . . . . . . . . . . 6 COLOR BAR GENERATION . . . . . . . . . . . . . . . . . . . . . . 8 SQUARE PIXEL MODE . . . . . . . . . . . . . . . . . . . . . . . . . . 8 COLOR SIGNAL CONTROL . . . . . . . . . . . . . . . . . . . . . . 8 BURST SIGNAL CONTROL . . . . . . . . . . . . . . . . . . . . . . 8 NTSC PEDESTAL CONTROL . . . . . . . . . . . . . . . . . . . . . 8 SUBCARRIER RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 REAL TIME CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . 8 PIXEL TIMING DESCRIPTION ...
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... OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Plastic Quad Flatpack (S-44) 0.548 (13.925) 0.546 (13.875) 0.096 (2.44) 0.398 (10.11) MAX 0.390 (9.91) 0.037 (0.94) 8 0.025 (0.64) 33 0.8 34 SEATING PLANE TOP VIEW (PINS DOWN 0.040 (1.02) 0.040 (1.02) 0.032 (0.81) 0.032 (0.81) 0.033 (0.84) 0.083 (2.11) 0.029 (0.74) 0.077 (1.96) –35– ADV7175/ADV7176 0.016 (0.41) 0.012 (0.30) ...
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