AD9883 Analog Devices, AD9883 Datasheet
AD9883
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AD9883 Summary of contents
Page 1
... GENERAL DESCRIPTION The AD9883 is a complete 8-bit, 110 MSPS monolithic analog interface optimized for capturing RGB graphics signals from personal computers and workstations. Its 110 MSPS encode rate capability and full-power analog bandwidth of 300 MHz supports resolutions up to SXGA (1280 × 1024 at 60 Hz). ...
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... Full IV 15 Full VI 110 Full IV 25°C IV Full IV Full IV Full VI 2.5 Full VI Full V Full V 25°C V Full Full VI Full IV 45 AD9883KST-110 Typ Max 8 ± 0.5 +1.25/–1.0 +1.35/–1.0 ± 0.5 ± 1.85 ± 2.0 Guaranteed 0.5 100 6 1.25 1.32 ± +2.0 110 12 1 400 700 1 1000 15 0.8 – ...
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... Min Full IV 3.0 Full IV 2.2 Full IV 3.0 25°C V 25°C V 25°C V Full VI Full VI Full VI 25°C V 25°C V 25°C V 25°C V Full V Full AD9883 Typ Max Unit 3.3 3.6 V 3.3 3.6 V 3.3 3.6 V 132 525 650 16 300 MHz ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9883 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... AD9883 10 TOP VIEW 11 (Not to Scale Table I. Complete Pinout List AD9883 GND REF BYPASS 57 SDA 56 SCL AIN 53 GND ...
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... Hsync input. See the Sync Block Diagram (Figure 11) to view how this pin is connected. (Note: Besides slicing off SOG, the output from this pin gets no other additional processing on the AD9883. Vsync separation is performed via the sync separator.) Serial Port (Two-Wire) SDA ...
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... V to 1.0 V p-p. Signals are typically brought onto the interface board via a DVI-I connector, a 15-pin D connector, or via BNC connectors. The AD9883 should be located as close as practical to the input connector. Signals should be routed via matched-impedance traces (normally 75 Ω) to the IC input pins. AD9883 ...
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... G AIN B AIN A simpler method of clamp timing employs the AD9883 internal clamp timing generator. The Clamp Placement register is pro- grammed with the number of pixel times that should pass after the trailing edge of HSYNC before clamping starts. A second register (Clamp Duration) sets the duration of the clamp. ...
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... Considerable care has been taken in the design of the AD9883’s clock generation circuit to minimize jitter. As indicated in Fig- ure 5, the clock jitter of the AD9883 is less than 5% of the total pixel time in all operating modes, making the reduction in the valid sampling time due to jitter negligible. ...
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... Register. For both HSYNC and COAST, a value of “1” is active high. Power Management The AD9883 uses the activity detect circuits, the active inter- face bits in the serial bus, the active interface override bits, and the power-down bit to determine the correct power state. There are three power states, full-power, seek mode, and power-down ...
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... The Output Data Clock signal is created so that its rising edge always occurs between data transitions, and can be used to latch the output data externally. There is a pipeline in the AD9883, which must be flushed before valid data becomes available. This means four data sets are presented before valid data is available. ...
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... AD9883 Coast Timing In most computer systems, the Hsync signal is provided con- tinuously on a dedicated wire. In these systems, the COAST input and function are unnecessary, and should not be used and the pin should be permanently connected to the inactive state. In some systems, however, Hsync is disturbed during the Vertical Sync period (Vsync) ...
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... Serial Register Map The AD9883 is initialized and controlled by a set of registers, which determine the operating modes. An external controller is employed to write and read the Control Registers through the 2-line serial interface port. Write and Hex Read or Default Address Read Only Bits ...
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... RO 7:0 NOTE 1 The AD9883 only updates the PLL divide ratio when the LSBs are written to (register 02h). Table VI. Control Register Map (Continued) Register Name Function Bit 7 – Clamp Function. Chooses between HSYNC for Clamp signal or another external signal to be used for clamping. ...
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... The greater the error, the greater the number of bars produced. The power-up default value of PLLDIV is 1693 (PLLDIVM = 69h, PLLDIVL = Dxh). The AD9883 updates the full divide ratio only when the LSBs are changed. Writing to the MSB by itself will not trigger an update. 02 7– ...
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... The leading edge of the Hsync output is triggered by the internally generated, phase-adjusted PLL feedback clock. The AD9883 then counts a number of pixel clocks equal to the value in this register. This triggers the trailing edge of the Hsync output, which is also phase-adjusted. INPUT GAIN 08 7– ...
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... Active HIGH means that the clock generator will ignore Hsync inputs when COAST is HIGH, and continue operating at the same nominal frequency until COAST goes LOW. This function needs to be used along with the COAST polarity override bit, (Bit 4). The power-up default value is 1. AD9883 ...
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... AD9883 0F 2 Seek Mode Override This bit is used to either allow or disallow the low-power mode. The low-power mode (seek mode) occurs when there are no signals on any of the Sync inputs. Table XXI. Seek Mode Override Settings Select Result 1 Allow Seek Mode 0 Disallow Seek Mode The default for this register is 1 ...
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... This bit reports the status of the coast input polarity detection circuit. It can be used to determine the polarity of the coast input. The detection circuit’s location is shown in the Sync Processing Block Diagram. Table XXXIII. Detected Coast Input Polarity Status Hsync Polarity Status 0 1 AD9883 Override AVS ...
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... Any base address higher than 14h will not produce an acknowledge signal. Data is read from the control registers of the AD9883 in a similar manner. Reading requires two data transfer operations: The base address must be written with the R/W bit of the slave address byte LOW to set up a sequential read operation ...
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... Stop Signal BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 ACTIVITY DETECT COMP SYNC MUX 1 PLL POLARITY DETECT HSYNC CLOCK MUX 2 GENERATOR POLARITY DETECT MUX 4 AD9883 BIT 0 ACK SYNC SEPARATOR INTEGRATOR VSYNC 1/S SOG OUT HSYNC OUT HSYNC OUT PIXEL CLOCK AD9883 VSYNC OUT ...
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... The fundamental idea is to have a bypass capacitor within about 0 each power pin. Also, avoid placing the capacitor on the opposite side of the PC board from the AD9883, as that interposes resistive vias in the path. The bypass capacitors should be physically located between the power plane and the power pin. Current should flow from the power plane => ...
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... EMI, and reduce the current spikes inside of the AD9883. If series resistors are used, place them as close to the AD9883 pins as possible, (although try not to add vias or extra length to the output trace in order to get the resistors closer). If possible, limit the capacitance that each of the digital outputs drives to less than 10 pF ...
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... AD9883 0.030 (0.75) 0.024 (0.60) 0.018 (0.45) COPLANARITY 0.004 (0.10) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 80-Lead LQFP (ST-80) 0.063 (1.60) 0.630 (16.00) BSC SQ MAX 0.551 (14.00) BSC SEATING PIN 1 PLANE TOP VIEW (PINS DOWN) 20 MAX 21 0.006 (0.15) 0.002 (0.05) 0.008 (0.20) 0.0256 (0.65) 0.015 (0.38) BSC 0.013 (0.32) 0.004 (0.09) 0.009 (0.22) CONTROLLING DIMENSIONS IN MILLIMETERS. ...