AD9200 Analog Devices, AD9200 Datasheet
AD9200
Specifications of AD9200
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AD9200 Summary of contents
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... The AD9200 can operate with supply range from 2 5.5 V, ideally suiting it for low power operation in high speed portable applications. The AD9200 is specified over the industrial (– +85 C) and commercial ( +70 C) temperature ranges. PRODUCT HIGHLIGHTS Low Power The AD9200 consumes supply (excluding the reference power) ...
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... AD9200–SPECIFICATIONS Parameter RESOLUTION CONVERSION RATE DC ACCURACY Differential Nonlinearity Integral Nonlinearity Offset Error Gain Error REFERENCE VOLTAGES Top Reference Voltage Bottom Reference Voltage Differential Reference Voltage 1 Reference Input Resistance ANALOG INPUT Input Voltage Range Input Capacitance Aperture Delay Aperture Uncertainty (Jitter) Input Bandwidth (– ...
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... A) OL CLOCKING Clock Pulsewidth High Clock Pulsewidth Low Pipeline Latency 2 CLAMP Clamp Error Voltage Clamp Pulsewidth NOTES 1 See Figures 1a and 1b. 2 Available only in AD9200ARS and AD9200KST. Specifications subject to change without notice. REFTS REFBS MODE AV DD REV. E Symbol Min Typ Max V 2.4 ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9200 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... AVDD Analog Supply –5– AD9200 PIN 1 2 IDENTIFIER 35 REFBS 3 34 REFBF MODE AD9200 TOP VIEW 7 30 REFTF (Not to Scale REFTS 9 28 CLAMPIN 10 27 CLAMP 11 REFSENSE ...
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... AD9200 DEFINITIONS OF SPECIFICATIONS Integral Nonlinearity (INL) Integral nonlinearity refers to the deviation of each individual code from a line drawn from “zero” through “full scale”. The point used as “zero” occurs 1/2 LSB before the first code transi- tion. “Full scale” is defined as a level 1 1/2 LSB beyond the last code transition ...
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... CLOCK FREQUENCY – MHz 1M 900k 800k 700k 600k 499856 500k 400k 300k 200k 100k 54383 54160 0 N–1 N CODE Figure 11. Grounded Input Histogram 20 0 CLOCK = 20MHz –20 –40 –60 –80 0E+0 1E+6 2E+6 3E+6 4E+6 5E+6 6E+6 7E+6 8E+6 9E+6 SINGLE TONE FREQUENCY DOMAIN Figure 12. Single-Tone Frequency Domain AD9200 N+1 10E+6 ...
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... OPERATIONAL MODES 1.0E+9 The AD9200 is designed to allow optimal performance in a wide variety of imaging, communications and instrumentation applications, including pin compatibility with the AD876 A/D. To realize this flexibility, internal switches on the AD9200 are used to reconfigure the circuit into different modes ...
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... VREF is determined by the internal reference or brought in externally by the user. The best noise performance may be obtained by operating the AD9200 with input range. The best distortion perfor- mance may be obtained by operating the AD9200 with input range. REFERENCE OPERATION The AD9200 can be configured in a variety of reference topolo- gies. The simplest configuration is to use the AD9200’ ...
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... REFTS A2 A/D 4.2k REFBS CORE TOTAL 10k INTERNAL 10k REF c. Differential Mode 0 0.1 F 1.0 F Figure 16. –10– AD9200 AIN SHA 10k 10k REFTS A2 A/D 4.2k REFBS CORE TOTAL 10k INTERNAL 10k REF * MAXIMUM MAGNITUDE DETERMINED BY INTERNAL REFERENCE b. Center Span Mode MODE AVDD/2 0.1 F REFTF 0 ...
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... REFTS = reference top, sense REFBS = reference bottom, sense INTERNAL REFERENCE OPERATION Figures 18, 19 and 20 show example hookups of the AD9200 internal reference in its most common configurations. (Figures 18 and 19 illustrate top/bottom mode while Figure 20 illustrates center span mode). Figure 29 shows how to connect the AD9200 for 1 V p-p differential operation ...
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... EXTERNAL REFERENCE OPERATION Using an external reference may provide more flexibility and improve drift and accuracy. Figures 21 through 23 show ex- amples of how to use an external reference with the AD9200. To use an external reference, the user must disable the internal reference amplifier by connecting the REFSENSE pin to VDD. ...
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... The video signal must be dc restored from 3-volt range down 2-volt range. Configuring the AD9200 for a one volt input span with an input range from volts (see Figure 24), the CLAMPIN voltage can be set to 1 volt with an external voltage or by direct connection to REFBS ...
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... AD9200’s internal clamp. See Clamp Operation. There are additional considerations when choosing the resistor values. The ac-coupling capacitors integrate the switching tran- sients present at the input of the AD9200 and cause a net dc or less. For applica- bias current, I bias current increases as the signal magnitude deviates from V midscale and the clock frequency increases ...
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... AD9200 in the external reference mode. The external reference input for the AD876 will now be placed on the reference pins of the AD9200. The clamp controls will be grounded by the AD876 socket. The AD9200 has a 3 clock cycle delay compared to a 3.5 cycle delay of the AD876 ...
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... SNR degradation at higher IF frequencies. In fact, the AD9200 is capable of still maintaining SNR 135 MHz with (i.e., 4 dBm) input span. Note, although the AD9200 will typically yield improvement in SNR when con- figured for the 2 V span, the 1 V span provides the optimum full-scale distortion performance ...
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... The performance characteristics in these figures are representative of the AD9200 without the AD8009. The AD9200 was operated in the differential mode (via trans- former) with span at 20 MSPS. The analog supply (AVDD) and the digital supply (DRVDD) were set and 3 ...
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... J7 JP5 R37 1k R53 49.9 JP17 R38 1k GND JP18 R39 1k AVDD C16 C19 0.1 F 0.1 F C18 C17 10/10V 10/10V 28 2 OTR AVDD DRVDD TP19 U1 WHITE AD9200 13 OTR DUTCLK CLK THREE-STATE THREE-STATE STBY STBY REFSENSE REFSENSE CLAMP ...
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... C31 10/10V 14 L1 74AHC14 PWR DRVDD U6 C23 GND 10/10V 7 L2 AVDD C25 33/16V L3 +3–5A C27 10/10V Figure 39b. Evaluation Board Schematic –19– AD9200 JP14 AVDD R5 10k JP15 R6 10k JP16 AVDDCLK GND R35 4.99k R34 2k CW R36 4.99k ...
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... AD9200 Figure 40a. Evaluation Board, Component Signal (Not to Scale) Figure 40b. Evaluation Board, Solder Signal (Not to Scale) –20– REV. E ...
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... Figure 40c. Evaluation Board Power Plane (Not to Scale) Figure 40d. Evaluation Board Ground Plane (Not to Scale) REV. E –21– AD9200 ...
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... AD9200 Figure 40e. Evaluation Board Component Silk (Not to Scale) Figure 40f. Evaluation Board Solder Silk (Not to Scale) –22– REV. E ...
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... DRVDD = all cases, check your logic family data sheets for compatibility with the AD9200 Digital Specification table. THREE-STATE OUTPUTS The digital outputs of the AD9200 can be placed in a high impedance state by setting the THREE-STATE pin to HIGH. This feature is provided to facilitate in-circuit testing or evaluation. ...
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... AD9200 0.078 (1.98) 0.068 (1.73) 0.008 (0.203) 0.002 (0.050) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 48-Lead Plastic Thin Quad Flatpack (LQFP) (ST-48) 0.063 (1.60) MAX 0.354 (9.00) BSC 0.030 (0.75) 0.057 (1.45) 0.276 (7.0) BSC 0.030 (0.75) 0.053 (1.35) 0.018 (0.45) 0.018 (0.45 SEATING PLANE TOP VIEW (PINS DOWN) 0.006 (0.15 0.002 (0.05) 0 MIN 0 – ...