AD9887 Analog Devices, AD9887 Datasheet
AD9887
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AD9887 Summary of contents
Page 1
... SXGA (1280 × 1024 at 75 Hz). Either the analog or the digital interface can be selected by the user. Analog Interface For ease of design and to minimize cost, the AD9887 is a fully integrated interface solution for FPDs. The AD9887 includes an analog interface with a 140 MHz triple ADC with internal 1.25 V reference, PLL to generate a pixel clock from HSYNC, program- mable gain, offset, and clamp control ...
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... VI 100 400 700 2 IV 1000 2.6 VI 0.8 IV –1 2 Binary AD9887KS-140 Min Typ Max Unit 8 Bits ± 0.5 +1.25/–1.0 LSB +1.25/–1.0 LSB ± 0.5 ± 1.4 LSB ± 2.5 LSB Guaranteed 0.5 V p-p 1.0 V p-p 150 ppm/°C 1 µA 1 µ 8 ...
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... Level Min Typ Max IV 3.0 3.3 3.6 IV 2.2 3.3 3.6 IV 3.0 3.3 3.6 V 140 170 258 330 1 AD9887 AD9887KS-140 Min Typ Max Unit 3.0 3.3 3.6 V 2.2 3.3 3.6 V 3.0 3.3 3.6 V 155 215 258 330 MHz dBc 30 °C/W ...
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... Output Drive = High LHT L Output Drive = Med Output Drive = Low Output Drive = High Output Drive = Med Output Drive = Low Test AD9887KS Level Min Typ Max Unit 8 Bits GND – ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9887 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... BLUE A<2> BLUE A<1> 29 BLUE A<0> GND 32 BLUE B<7> 33 BLUE B<6> 34 BLUE B<5> 35 BLUE B<4> 36 BLUE B<3> 37 BLUE B<2> 38 BLUE B<1> 39 BLUE B<0> CONNECT PIN CONFIGURATION AD9887 TOP VIEW (Not to Scale 120 MIDSC 119 R AIN R V 118 CLAMP V 117 D GND 116 115 V D 114 V D 113 GND 112 ...
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... Digital Data Clock Complement xc Data Enable DE Data Enable Control Bits CTL[0:3] Decoded Control Bits R R Sets Internal Termination Resistance TERM TERM Table I. Complete Pinout List or Ground DD AD9887 Pin Value Number Interface 0 1.0 V 119 Analog 0 1.0 V 110 Analog 0 1.0 V 100 Analog 3.3 V CMOS 82 Analog 3 ...
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... AD9887 DESCRIPTIONS OF PINS SHARED BETWEEN ANALOG AND DIGITAL INTERFACES HSOUT Horizontal Sync Output A reconstructed and phase-aligned version of the video HSYNC. The polarity of this output can be controlled via a serial bus bit. In analog interface mode the placement and duration are variable. In digital interface mode the placement and duration are set by the graphics transmitter ...
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... SOGOUT. When not used, this input should be left unconnected. For more details on this func- tion and how it should be configured, refer to the Sync-on-Green section. AD9887 Value Pin No. 0 1.0 V 119 0 1.0 V 110 0 ...
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... COAST Polarity defaults power-up. CKEXT External Clock Input (Optional) This pin may be used to provide an external clock to the AD9887, in place of the clock internally generated from HSYNC enabled by programming EXTCLK to 1. When an external clock is used, all other internal functions operate normally. When unused, this pin should be tied to V EXTCLK programmed to 0 ...
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... THEORY OF OPERATION (INTERFACE DETECTION) Active Interface Detection and Selection The AD9887 includes circuitry to detect whether or not an interface is active. For detecting the analog interface, the circuitry monitors the presence of HSYNC, VSYNC, and Sync-on-Green. The result of the detection circuitry can be read from the 2-wire serial inter- face bus at address 11H Bits 7, 6, and 5 respectively ...
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... This helps to minimize the AD9887 total power dissipation. In addition, if neither inter- face has activity on it, the chip powers down both interfaces. The AD9887 uses the activity detect circuits, the active inter- face bits in the serial registers, the active interface override bits, Analog ...
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... RGB INPUT 75 HSYNC, VSYNC Inputs The AD9887 receives a horizontal sync signal and uses it to generate the pixel clock and clamp timing possible to operate the AD9887 without applying HSYNC (using an external clock, external clamp) but a number of features of the chip will be unavailable recommended that HSYNC be provided. ...
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... EXTCLMP = 1). The polarity of this signal is set by the Clamp Polarity bit. An easier method of clamp timing employs the AD9887 internal clamp timing generator. The Clamp Placement register is pro- grammed with the number of pixel clocks that should pass after the trailing edge of HSYNC before clamping starts ...
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... Considerable care has been taken in the design of the AD9887’s clock generation circuit to minimize jitter. As indicated in Fig- ure 6, the clock jitter of the AD9887 is less than 6% of the total pixel time in all operating modes, making the reduction in the valid sampling time due to jitter negligible. ...
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... AD9887 Table V. VCO Frequency Ranges Pixel Clock PV1 PV0 Range (MHz 12– 35– 70–110 1 1 110–140 Table VI. Charge Pump Current/Control Bits Ip2 Ip1 Ip0 Table VII. Recommended VCO Range and Charge Pump Current Settings for Standard Display Formats ...
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... SCAN Function The SCAN function is intended as a pseudo JTAG function for manufacturing test of the board. The ordinary operation of the AD9887 is disabled during SCAN. To enable the SCAN function, set register 14h, bit SCAN in data to all 48 digital outputs, apply 48 serial bits of ...
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... Timing (Analog Interface) The following timing diagrams show the operation of the AD9887 analog interface in all clock modes. The part estab- lishes timing by having the sample that corresponds to the pixel digitized when the leading edge of HSYNC occurs sent to the “ ...
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... DELAY ADCCK DATACK D OUTA HSOUT RGB HSYNC PxCK HS 5-PIPE DELAY ADCCK DATACK D OUTA HSOUT RGB IN HSYNC PxCK HS 5.5-PIPE DELAY ADCCK DATACK D OUTA HSOUT AD9887 ...
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... AD9887 RGB HSYNC PxCK HS 3-PIPE DELAY ADCCK DATACK D OUTA D OUTB HSOUT RGB HSYNC PxCK HS ADCCK DATACK D OUTA D OUTB HSOUT RGB IN HSYNC PxCK HS 3-PIPE DELAY ADCCK DATACK D OUTA D OUTB HSOUT ...
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... DELAY ADCCK DATACK D OUTA D OUTB HSOUT RGB IN HSYNC PxCK HS 7-PIPE DELAY ADCCK DATACK D OUTA D OUTB HSOUT RGB IN HSYNC PxCK HS 7.5-PIPE DELAY ADCCK DATACK D OUTA D OUTB HSOUT AD9887 ...
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... AD9887 RGBIN HSYNC PXCK HS 6-PIPE DELAY ADCCK DATACK GOUTA ROUTA HSOUT Pin Type Pin Name Digital Video Data Inputs Rx0+ Rx0– Rx1+ Rx1– Rx2+ Rx2– Digital Video Clock Inputs RxC+ RxC– Termination Control R TERM Outputs DE HSYNC ...
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... During periods of horizontal or vertical blanking time (when DE is low), the digital transmitter will transmit special characters. The AD9887 will receive these characters and use them to set the video frame boundaries and the phase recovery loop for each channel. There are four special characters that can be received. ...
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... AD9887 GENERAL TIMING DIAGRAMS (DIGITAL INTERFACE) 80% 20% D LHT CIP CIP CIH CIH T CIL DIFF DIFF T CCS R X2 DATACK (INTERNAL) DATA OUT DATACK (PIN) t SKEW TIMING MODE DIAGRAMS (DIGITAL INTERFACE) 80% INTERNAL ODCLK 20% DATACK D LHT DE QE[23:0] QO[23: INTERNAL ...
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... Serial Register Map The AD9887 is initialized and controlled by a set of registers, which determine the operating modes. An external controller is employed to write and read the Control Registers through the 2-line serial interface port. Read and Hex Write or Default Address Read Only Bits ...
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... AD9887 Read and Hex Write or Default Address Read Only Bits Value 0FH R/W 7 10H R/W 7 11H RO 7:1 Table IX. Control Register Map (continued) Register Name Function PLL and Bit 7—HSYNC Polarity. Indicates the polarity of incoming HSYNC Clamp Control signal to the PLL. (Logic 0 = Active Low, Logic 1 = Active High.) Bit 6— ...
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... Bit 1—Must be set to 0 for proper operation. Pre-Coast Sets the number of Hsyncs that coast goes active prior to Vsync. Post-Coast Sets the number of Hsyncs that coast goes active following Vsync. Test Register Must be set to default for proper operation. Test Register Must be set to 01000001 for proper operation. AD9887 ...
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... RO 7:0 1FH RO 7:0 NOTE 1 The AD9887 only updates the PLL divide ratio when the LSBs are written to (Register 02h). Table IX. Control Register Map (continued) Register Name Function Test Register Must be set to 00010000 for proper operation. 4:2:2 Control Bits [7:2]—Must be set to 011011** for proper operation. ...
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... The greater the error, the greater the number of bars produced. The power-up default value of PLLDIV is 1693 (PLLDIVM = 69h, PLLDIVL = Dxh). The AD9887 updates the full divide ratio only when the LSBs are changed. Writing to this register by itself will not trigger an update. 02 7– ...
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... The leading edge of the Hsync output is triggered by the internally generated, phase-adjusted PLL feedback clock. The AD9887 then counts a number of pixel clocks equal to the value in this register. This triggers the trailing edge of the Hsync output, which is also phase-adjusted. INPUT GAIN 08 7– ...
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... External Clock Select A bit that determines the source of the pixel clock. Table XXI. External Clock Select Settings EXTCLK Function 0 Internally Generated Clock 1 Externally Provided Clock Signal A Logic 0 enables the internal PLL that generates the pixel clock from an externally provided Hsync. AD9887 ...
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... AD9887 A Logic 1 enables the external CKEXT input pin. In this mode, the PLL Divide Ratio (PLLDIV) is ignored. The clock phase adjust (PHASE) is still functional. The power-up default value is EXTCLK = Red Clamp Select A bit that determines whether the red channel is clamped to ground or to midscale. For RGB video, all three chan- nels are referenced to ground ...
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... If both VSYNC and composite SOG are detected, VSYNC will be selected. The user can override this function via Bit 3 in Register 12H. If the override bit is set to Logic 1, this bit will be forced to what- ever the state of Bit 2 in Register 12H is set to. AD9887 AI Soft Power-Down (Seek Mode) ...
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... AD9887 Table XXXVI. Active VSYNC Results Bit 5 (VSYNC Detect) Override AVS Bit 2 in 12H AVS = 1 means Sync separator. AVS = 0 means VSYNC input. The override bit is in Register 12H, Bit AIO—Active Interface Override This bit is used to override the automatic interface selec- tion (Bit 3 in Register 11H) ...
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... The default for this register is 32. CONTROL BITS 14 2 Scan Enable This register is used to enable the scan function. When enabled, data can be loaded into the AD9887 outputs serially with the scan function. The scan function utilizes three pins (SCAN , SCAN , and SCAN ...
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... Any base address higher than 1Dh will not produce an acknowledge signal. Data is read from the control registers of the AD9887 in a similar manner. Reading requires two data transfer operations: The base address must be written with the R/W bit of the slave address byte LOW to set up a sequential read operation ...
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... Hsync signal rejects any signal shorter than a threshold value, which is somewhere between an Hsync pulsewidth and a Vsync pulsewidth. The sync separator on the AD9887 is simply an 8-bit digital counter with a 5 MHz clock. It works independently of the polarity of the composite sync signal. (Polarities are determined elsewhere on the chip ...
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... The fundamental idea is to have a bypass capacitor within about 0 each power pin. Also, avoid placing the capacitor on the opposite side of the PC board from the AD9887, as that interposes resistive vias in the path. The bypass capacitors should be physically located between the power plane and the power pin ...
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... EMI, and reduce the current spikes inside of the AD9887. If series resistors are used, place them as close to the AD9887 pins as possible (try not to add vias or extra length to the output trace in order to get the resistors closer). If possible, limit the capacitance that each of the digital outputs drives to less than 10 pF ...
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... AD9887 0.041 (1.03) 0.035 (0.88) 0.029 (0.73) SEATING 0.004 (0.10) 0.010 (0.25) CONTROLLING DIMENSIONS ARE IN MILLIMETERS. INCH DIMENSIONS ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 160-Lead MQFP (S-160) 1.238 (31.45) 1.228 (31.20) SQ 1.219 (30.95) 1.106 (28.10) 0.160 (4.07) 1 ...