ZL30106 Zarlink Semiconductor, ZL30106 Datasheet
ZL30106
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ZL30106 Summary of contents
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... MODE_SEL1:0 Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004-2005, Zarlink Semiconductor Inc. All Rights Reserved. ZL30106QDG 64 pin TQFP Trays, Bake & Drypack ZL30106QDG1 64 pin TQFP* Trays, Bake & Drypack • Provides lock, holdover and accurate reference fail indication • ...
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... The ZL30106 SONET/SDH/PDH network interface Digital Phase-Locked Loop (DPLL) provides timing and synchronization for SONET/SDH and PDH network interface cards. The ZL30106 generates SONET/SDH, PDH, ST-BUS and other TDM clock and framing signals that are phase locked to one of three network references. It helps ensure system reliability by monitoring its references for frequency accuracy and stability and by maintaining tight phase alignment between the input reference clock and clock outputs ...
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... Time Interval Error (TIE 5.11 Maximum Time Interval Error (MTIE 5.12 Phase Continuity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.13 Lock Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.0 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.1 Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2.1 Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2.2 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.3 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.4 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.0 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.1 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.2 Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 ZL30106 Table of Contents 3 Zarlink Semiconductor Inc. Data Sheet ...
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... References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 ZL30106 Table of Contents 4 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 23 - REF0/1/2 Input Timing and Input to Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 24 - REF_SYNC0/1 Timing Figure Output Timing Referenced to F8/F32o Figure 26 - DS1 Output Timing Referenced to F8/F32o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 27 - SDH Output Timing Referenced to F8/F32o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 28 - DS3, E3, E2 and DS2 Output Timing Referenced to F8/F32o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 ZL30106 List of Figures 5 Zarlink Semiconductor Inc. Data Sheet ...
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... Input to output timing for REF0, REF1 and REF2 references when TIE_CLR = 0 (see Figure 23).“ 38 Section 7.1 42 Section 7.2 ZL30106 Change Changed description for hitless reference switching. Removed power supply decoupling circuit and included reference to synchronizer power supply decoupling application note. Change Specified clock and frame pulse outputs forced to high ...
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... REF2 APP_SEL0 TIE_CLR BW_SEL 64 Figure 2 - Pin Connections (64 pin TQFP, please see Note 1) Note 1: The ZL30106 uses the TQFP shown in the package outline designated with the suffix QD, the ZL30106 does not use the e-Pad TQFP. ZL30106 ZL30106 ...
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... Hitless Mode Switching (Input). The HMS input controls phase accumulation during the transition from Holdover or Freerun mode to Normal mode on the same reference. A logic low at this pin will cause the ZL30106 to maintain the delay stored in the TIE corrector circuit when it transitions from Holdover or Freerun mode to Normal mode. A logic high ...
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... Internal Connection. Leave unconnected. 23 GND Ground APP_SEL1 Application Selection 1 (Input). This input combined with APP_SEL0 selects the application that the ZL30106 is optimized for, see Table 1 on page 20 Positive Supply Voltage. +3 OUT_SEL2 Output Selection 2 (Input). This input selects the signals on the combined output clock and frame pulse pins, see Table 3 on page 21 ...
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... Table 5 on page 23. In the Automatic mode of operation, REFSEL0 is an output indicating which of the input references is the being selected, see Table 6 on page 25. This pin is internally pulled down to GND. 54 REF_SEL1 Reference Select 1 (Input/Output). See REF_SEL0 pin description. ZL30106 Description nominal DC nominal DC 10 Zarlink Semiconductor Inc ...
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... Reference Select Multiplexer (MUX) The ZL30106 accepts three simultaneous reference input signals and operates on their rising edges. One of them, the primary reference (REF0), the secondary reference (REF1) or the tertiary reference (REF2) signal, is selected as input to the TIE Corrector Circuit based on the reference selection (REF_SEL1:0) inputs. REF0 and REF1 can be accompanied kHz or 8 kHz frame pulse on the REF_SYNC0 and REF_SYNC1 inputs ...
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... Multiple failures of less than 50 ms each have an accumulative effect and will disqualify the reference eventually. This is illustrated in Figure 4 where REF0 experiences disruptions while REF1 is stable. ZL30106 OR REF_OOR ...
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... If there no other reference available, it stays in Holdover mode. The precise frequency monitor’s failure thresholds are selected with the APP_SEL pins based on the ZL30106 applications. Figure 5, Figure 6 and Figure 7 show the out of range limits for various master clock accuracies. It will take the precise frequency monitor qualify or disqualify the input reference ...
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... REF_SYNC frame pulse period to validate the REF_SYNC signal. If the REF and REF_SYNC inputs are selected for synchronization and the Sync Ratio Monitor detects a failure, the DPLL will abandon the mechanism of aligning the output frame pulse to the REF_SYNC pulse. Instead only the REF reference will be used for synchronization. ZL30106 C20 -12 -9 ...
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... Figure 23. The speed of the phase alignment correction is limited by the loop filter bandwidth. Convergence is always in the direction of least phase travel. TIE_CLR can be kept low continuously. In that case the output clocks will always align with the selected input reference. This is illustrated in Figure 9. ZL30106 REF_SYNC Ratio ...
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... Normal mode. This causes accumulation of phase in network elements. In both cases the PLL’s output can be aligned with the input reference by setting TIE_CLR low. Regardless of the HMS pin state, reference switching in the ZL30106 is always hitless unless TIE_CLR is kept low continuously. ...
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... Phase = 0.01 ppm holdover_drift - Phase = mode_change - Phase = ns) = 330 ns 10 changes ZL30106 REF Output Clock REF Output Clock REF Output Clock TIE_CLR=0 REF Output ...
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... Digital Phase Lock Loop (DPLL) The DPLL of the ZL30106 consists of a phase detector, a limiter, a loop filter and a digitally controlled oscillator as shown in Figure 11. The data path from the phase detector to the limiter is tapped and routed to the lock detector that provides a lock indication which is output at the LOCK pin. ...
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... As shown in Figure 1, the state machine controls the TIE Corrector Circuit and the DPLL. The control of the ZL30106 is based on the inputs MODE_SEL1:0, REF_SEL1:0 and HMS. 3.7 Master Clock The ZL30106 can use either a clock or crystal as the master timing source. For recommended master timing circuits, see the Applications - Master Clock section. ZL30106 19 Zarlink Semiconductor Inc ...
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... Control and Modes of Operation 4.1 Application Selection Table 1 lists the applications that are supported by the ZL30106 with the corresponding frequency out of range limits. APP_SEL Application 00 DS1/E1 01 Derived DS1 10 DS2/E2/DS3/E3 11 SONET/SDH Table 1 - Application Selection and the Out of Range Limits 4.2 Loop Filter and Limiter Selection The loop filter and limiter settings are selected through the APP_SEL and BW_SEL pins, see Table 2 ...
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... MODE_SEL1 and MODE_SEL0 as is shown in Table 4. Transitioning from one mode to the other is controlled by an external controller. The ZL30106 can be configured to automatically select a valid input reference under control of its internal state machine by setting MODE_SEL1:0 = 11. In this mode of operation, a state machine controls selection of references (REF0 or REF1) used for synchronization ...
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... DPLL to recover from Holdover via one of two paths depending on the logic level at the HMS pin (see Figure 12). If HMS=0 then the ZL30106 will transition directly to Normal mode and it will align its output signals with its input reference (see Figure 10). If HMS=1 then the ZL30106 will transition to Normal mode via the TIE correction state and the phase difference between the output signals and the input reference will be maintained ...
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... In the manual modes of operation (MODE_SEL1:0 ≠ 11) the active reference input (REF0, REF1 or REF2) is selected by the REF_SEL1 and REF_SEL0 pins as shown in Table 5. When the logic value of the REF_SEL pins is changed when the DPLL is in Normal mode, the ZL30106 will perform a hitless reference switch. REF_SEL1 ...
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... If both references fail then the ZL30106 enters the Holdover mode without switching to another reference. When the ZL30106 comes out of reset or when REF2 is the current reference when the ZL30106 is put in the Automatic mode, then REF0 has priority over REF1. Otherwise there is no preference for REF0 or REF1 which is referred to as non-revertive reference selection ...
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... If the reference corrects itself within the reference-disqualify duration (< 50 milliseconds) the HOLDOVER pin is de- asserted, the REF_FAIL pin is de-asserted, and the REF_SEL outputs indicate that the device has remained locked to the old reference. The LOCK pin remains asserted. ZL30106 REF_SEL0 (output pin) ...
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... Where the new reference has enough frequency offset and/or TIE-corrected phase offset to force the output outside the phase-lock-window, the LOCK output will de- assert, the lock-qualify timer is reset, and LOCK will stay de-asserted for the full lock-time duration. Figure 17 illustrates this process. ZL30106 10 s REF1 Lock Time 26 Zarlink Semiconductor Inc ...
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... The clock-and-sync pair synchronization technique enables the ZL30106 to align its output 2 kHz and 8 kHz frame pulses with 2 kHz and 8 kHz references without restricting the loop filter. Therefore the output clocks and frame pulses will track the input clock and frame pulse pair closely even in the presence of jitter on the reference input ...
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... TIE_CLR pin is kept low REF - REF_SYNC pair is used as the reference then if the ZL30106 transitions from Holdover to Normal mode, the TIE correction circuit will not be activated and the PLL will align its output clock and frame pulse with the input REF and REF_SYNC pair ...
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... Holdover accuracy is defined as the absolute accuracy of an output clock signal, when it is not locked to an external reference signal, but is operating using storage techniques. For the ZL30106, the storage value is determined while the device is in Normal Mode and locked to an external reference signal. ...
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... Although a short lock time is desirable not always possible to achieve due to other synchronizer requirements. For instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock time. And better (smaller) phase slope performance (limiter) results in longer lock times. ZL30106 30 Zarlink Semiconductor Inc. ...
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... When selecting a clock oscillator, numerous parameters must be considered. This includes absolute frequency, frequency change over temperature, output rise and fall times, output levels, duty cycle and phase noise. The output clock should be connected directly (not AC coupled) to the OSCi input of the ZL30106, and the OSCo output should be left open as shown in Figure 19. ...
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... Table 8 - Typical Crystal Oscillator Specification ZL30106 6.3 Power Up Sequence The ZL30106 requires that the 3.3 V supply is not powered up after the 1.8 V supply. This is to prevent the risk of latch-up due to the presence of parasitic diodes in the IO pads. Two options are given: 1. Power-up the 3.3 V supply fully first, then power up the 1.8 V supply 2 ...
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... A simple power up reset circuit with about a 60 µs reset low time is shown in Figure 21. Resistor R only and limits current into the RST pin during power down conditions. The reset low time is not critical but should be greater than 300 ns. ZL30106 ZL30106 +3 kΩ ...
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... OSCi = Clock, OUT_SEL=000 3 OSCi = Clock, OUT_SEL=111 4 Core supply current with: OSCi = OSCi = Clock 6 Schmitt trigger Low to High threshold point 7 Schmitt trigger High to Low threshold point 8 Input leakage current 9 High-level output voltage ZL30106 Symbol Min. V -0.5 DD_R V -0.5 CORE_R V -0.5 PIN V -0.3 OSC I PIN T -55 ...
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... MHz reference period 8 reference pulse width high or low * Supply voltage and operating temperature are as per Recommended Operating Conditions. * Period Min/Max values are the limits to avoid a single-cycle fault detection. Short-term and long-term average periods must be within Out-of- Range limits. ZL30106 Sym. Min. Max. Units V ...
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... Supply voltage and operating temperature are as per Recommended Operating Conditions. * See Figure 18, “Examples of REF & REF_SYNC to Output Alignment” on page 28 for further explanation. REF0/1 REF_SYNC0/1 Note: REF0/1 can be 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz. REF_SYNC0/1 can be 2 kHz or 8 kHz. ZL30106 t REF<xx> REFW REFW ...
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... MHz reference input to F8/F32o delay 10 16.384 MHz reference input to C16o delay 11 16.384 MHz reference input to F8/F32o delay 12 19.44 MHz reference input to C19o delay 13 19.44 MHz reference input to F8/F32o delay * Supply voltage and operating temperature are as per Recommended Operating Conditions. ZL30106 Symbol t REF2kD t REF2k_F8D t REF8kD t REF1.5D t REF1 ...
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... F65o pulse with low 18 F65o delay 19 C65o pulse width low 20 C65o delay 21 Output clock and frame pulse rise time 22 Output clock and frame pulse fall time * Supply voltage and operating temperature are as per Recommended Operating Conditions. ZL30106 Sym. Min. Max. t -0.4 0.3 C2D t 243.0 244.1 C2L t 243 ...
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... F8o C2o F4o C4o C8o F16o C16o F32o C32o F65o C65o F32o, C32o, F65o and C65o are drawn on a larger scale than the other waveforms in this diagram. Figure Output Timing Referenced to F8/F32o ZL30106 t C2L t F4L t C4L t C8L t C16L t C32L t C65L 39 Zarlink Semiconductor Inc ...
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... F2ko pulse width high 5 Output clock and frame pulse rise time 6 Output clock and frame pulse fall time * Supply voltage and operating temperature are as per Recommended Operating Conditions. F8_32o C19o F2ko Figure 27 - SDH Output Timing Referenced to F8/F32o ZL30106 Sym. Min. Max. t -0.6 0.6 C1.5D t 323.1 324 ...
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... Output clock and frame pulse rise time 10 Output clock and frame pulse fall time * Supply voltage and operating temperature are as per Recommended Operating Conditions. F8_32o C44o C34o C8.4o C6o Figure 28 - DS3, E3, E2 and DS2 Output Timing Referenced to F8/F32o ZL30106 Sym. Min. Max. t -0.70 0.70 C6D t 78.5 79 ...
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... DS2/DS3/E2/E3 (APP_SEL=10), SONET/SDH (APP_SEL=11) Lock Time 8 All Application modes, 2 kHz reference (14 Hz filter) 9 DS1/E1 (APP_SEL=00) 8 kHz and greater reference frequencies (29 Hz filter) 10 Derived DS1 (APP_SEL=01) 8 kHz and greater reference frequencies (29 Hz filter) ZL30106 Min. Max. Units -32 +32 ppm -4.6 +4.6 ppm -20 +20 ppm 40 ...
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... Supply voltage and operating temperature are as per Recommended Operating Conditions. Performance Characteristics*: Input Wander and Jitter Tolerance Conformance Input reference frequency 1 1.544 MHz 2 2.048 MHz 3 19.44 MHz * Supply voltage and operating temperature are as per Recommended Operating Conditions. ZL30106 Min. Max. Units ...
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... UI pp G.812 ITU-T Jitter Generation Requirements Jitter Equivalent Limit in limit in the UI filter time domain 0. Zarlink Semiconductor Inc. Data Sheet ZL30106 maximum jitter Units generation 45.3 0. 324 0. ZL30106 maximum jitter Units generation 7.92 0. ZL30106 maximum jitter Units generation 24.4 0. ...
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... Option 2) ITU-T G.813 Limit in Equivalent limit UI in time domain ( 6.4 ns) 0.1 UI 0.64 pp 0.5 UI 3.22 pp 0 Zarlink Semiconductor Inc. Data Sheet T1.105.03 and conformance ZL30106 maximum jitter Units generation 0. 0. rms 0. ZL30106 maximum jitter generation Units ...
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... F2ko (2 kHz) 15 F4o (8 kHz) 16 F8o (8 kHz) 17 F16o (8 kHz) 18 F32o (8 kHz) 19 F65o (8 kHz) * Supply voltage and operating temperature are as per Recommended Operating Conditions. 8.0 References AdvancedTCA, ATCA and the AdvancedTCA and ATCA logos are trademarks of the PCI Industrial Computer Manufacturers Group. ZL30106 Max. [ 0.45 0.47 0.53 0.42 0.58 0.42 0.55 0.56 0.42 0.46 0.56 0.60 ...
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... Zarlink Semiconductor 2002 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...