TMP93CS41DF TOSHIBA Semiconductor CORPORATION, TMP93CS41DF Datasheet
TMP93CS41DF
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TMP93CS41DF Summary of contents
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TOSHIBA Original CMOS 16-Bit Microcontroller TLCS-900/L Series TMP93CS40/41 Semiconductor Company ...
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Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, “Points of Note and Restrictions”. Especially, take care below cautions. **CAUTION** How to release the HALT mode Usually, ...
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... Low Voltage/Low Power CMOS 16-Bit Microcontrollers TMP93CS40F/TMP93CS41F TMP93CS40DF/TMP93CS41DF 1. Outline and Device Characteristics The TMP93CS40/S41 are high-speed advanced 16-bit microcontrollers developed for controlling medium to large-scale equipment. The TMP93CS41 does not have a ROM; the TMP93CS40 has a built-in ROM. Otherwise, the devices function in the same way. ...
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... Standby function: 4 HALT modes (RUN, IDLE2, IDLE1, STOP) (16) Clock gear function Dual clock operation N Clock gear: High-frequency clock can be varied from fc to fc/16. N (17) Wide operating voltage Vcc 2 (18) Package Type No. TMP93CS40F P-QFP100-1414-0.50 TMP93CS41F TMP93CS40DF P-LQFP100-1414-0.50F TMP93CS41DF 7-level priority can be set. Package 93CS40-2 TMP93CS40/TMP93CS41 2004-02-10 ...
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PA0 to PA6 Port A PA7 (SCOUT) P50 to P57 (AN0 to AN7) 10-bit 8-ch AVCC AD AVSS converter VREFH VREFL (TXD0) P90 Serial I/O (RXD0) P91 (Channel 0) (SCLK0/ ) P92 CTS0 (TXD1) P93 Serial I/O (RXD1) P94 (Channel ...
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Pin Assignment and Functions The assignment of input/output pins on the TMP93CS40/TMP93CS41, their names and outline functions are described below. 2.1 Pin Assignment Figure 2.1.1 shows the pin assignment for the TMP93CS40F/S41F and TMP93CS40DF/S41DF. Program- mable Pin TMP93CS40 Pull ...
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Pin Names and Functions The names of the input/output pins and their functions are described below. Table 2.2.1 to Table 2.2.4 show pin names and functions. Table 2.2.1 Pin Names and Functions (1/4) Number Pin Names I/O of Pins ...
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Table 2.2.2 Pin Names and Functions (2/4) Number Pin Names I/O of Pins P41 1 I/O Port 41: I/O port (with pull-up resistor) CS1 Output Chip select 1: Outputs 0 if address is within specified address area. Column address strobe ...
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Table 2.2.3 Pin Names and Functions (3/4) Number Pin Names I/O of Pins P84 1 I/O Port 84: I/O port (with pull-up resistor) TI6 Input Timer input 6: Timer 5 count/capture trigger signal input INT6 Input Interrupt request pin 6: ...
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Table 2.2.4 Pin Names and Functions (4/4) Number Pin Names I/O of Pins AM8/ 1 Input AM16 ALE 1 Output RESET 1 Input X1/X2 2 I/O P96 1 I/O XT1 Input P97 1 I/O XT2 Output TEST1/TEST2 2 Output/Input ...
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Operation This section describes in blocks the functions and basic operations of TMP93CS40 and TMP93CS41 devices. Please also refer to section 7. Precautions in use, which describes some points requiring careful attention. 3.1 CPU TMP93CS40 and TMP93CS41 devices have ...
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Figure 3.1.1 TMP93CS41 Reset Timing Chart 93CS40-10 TMP93CS40/TMP93CS41 2004-02-10 ...
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Figure 3.1.2 TMP93CS40 Reset Timing Chart 93CS40-11 TMP93CS40/TMP93CS41 2004-02-10 ...
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AM8/ Pin AM16 (1) TMP93CS40 Set this pin to 1. Resetting accesses a built-in ROM via the internal 16-bit bus. When accessing externally, the bus width is set by the chip select/wait control register described in 3.6.3, and the ...
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Memory Map Figure 3.2 memory map of the TMP93CS40 and TMP93CS41. 000000H Internal I/O (128 bytes) 000080H 000100H Internal RAM (2 Kbytes) 000880H External memory 008000H Interrupt vector table area (64 entries u 4 bytes) 008100H 010000H ...
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Dual Clock, Standby Function Dual clock, standby control circuits are comprised of a system clock controller, prescaler clock controller, internal clock pin output function and standby controller. The oscillator operating modes are classified as either (a) Single clock mode ...
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Table 3.3.1 Relations between System Clock States and Other Internal Operations Oscillator Operating High Low Mode Frequency (fc) Frequency (fs) RESET NORMAL Oscillation RUN Stop IDLE2 IDLE1 STOP Stop RESET Stop Oscillation NORMAL Programmable SLOW Programmable Oscillation RUN Oscillator being ...
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Figure 3.3.2 Block Diagram of Dual Clock and Standby Circuits 93CS40-16 TMP93CS40/TMP93CS41 2004-02-10 ...
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SYSCR0 Bit symbol XEN XTEN (006EH) Read/Write After reset 1 0 High- Low- Function frequency frequency oscillator (fc) oscillator (fs) 0: Stop 0: Stop 1: Oscillation 1: Oscillation SYSCR1 Bit symbol (006FH) Read/Write After reset Function WDMOD Bit ...
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System Clock Controller The system clock controller generates the system clock signal (f internal I/O. It contains two oscillation circuits and a clock gear circuit for high frequency (fc). The register SYSCR1<SYSCK> changes the system clock to either fc ...
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Switching from NORMAL to SLOW mode When the resonator is connected to the X1 and X2 the XT1 and XT2 pins, the warm-up timer is used to change the operation frequency after stable oscillation is attained. The ...
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Clock setting example 1: Changing from high frequency (fc) to low frequency (fs). SYSCR0 EQU SYSCR1 EQU WDCR EQU WDMOD EQU RES LD SET SET SET WUP: BIT JR SET RES SET <XEN> X1 and X2 pins <XTEN> XT1 and ...
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Clock setting example 2: Changing from low frequency (fs) to high frequency (fc). SYSCR0 EQU SYSCR1 EQU WDCR EQU WDMOD EQU RES LD RES SET SET WUP: BIT JR RES RES SET <XEN> X1 and X2 pins <XTEN> XT1 and ...
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Clock gear controller When the high-frequency clock fc is selected at SYSCR1<SYSCK> “0”, the clock gear select register SYSCR1<GEAR2:0> sets f Switching f with the clock gear reduces the power consumption. FPH Clock setting example 3: Changing gear value ...
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Prescaler Clock Controller The 9-bit prescaler provides a clock signal to the 8-bit timer 0 and timer 1, 16-bit timer 4 and timer 5, and serial interface 0 and serial interface 1. The 5-bit prescaler provides a clock signal ...
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CLK pin The CLK pin outputs the internal clock signal f The type of output is determined by one bit in the clock output control register, CKOCR<CLKEN>. Writing 1 sets the clock output, and writing “0” sets the CLK ...
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Standby Controller (1) HALT mode When the HALT instruction is executed, the operating mode changes to RUN, IDLE2, IDLE1 or STOP mode depending on the contents of the HALT mode setting register WDMOD<HALTM1:0>. Figure 3.3.5 shows the alternative states ...
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Table 3.3.5 I/O Operation during HALT Mode HALT mode RUN WDMOD<HALTM1:0> 00 CPU I/O port Maintain the state when the HALT instruction was executed. 8-bit timer 8-bit PWM timer 16-bit timer Pattern generator Serial interface AD converter Watchdog timer Interrupt ...
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When releasing the HALT mode by resetting, the internal RAM data keeps the state before the “HALT” instruction is executed. However the other setting contents are initialized (Releasing due to interrupts keep the state before the “HALT” instruction is executed.) ...
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Operation 1. RUN mode In the RUN mode, the system clock in the MCU continues to operate even after a HALT instruction is executed. Only the CPU stops executing further instructions. In the halt state, an interrupt request is ...
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IDLE1 mode In the IDLE1 mode, only the internal oscillator operates. The system clock in the MCU stops, and the CLK pin is fixed at the level H in the output enabled state. (CKOCR<CLKEN> the halt state, ...
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STOP mode The STOP mode is selected to stop all internal circuits including the internal oscillator. The pin status in the STOP mode depends on the setting of a bit in the watchdog timer mode register WDMOD<DRVE>.) Table 3.3.8 ...
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How to calculate the warm-up time WDMOD<WARM> WDMOD<WARM> The selection of NORMAL versus SLOW modes is possible after the STOP mode is released. This selection is mode according to the contents of the SYSCR0<RSYSCK> register. Therefore, setting <RSYSCK>, <RXEN>, and ...
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Table 3.3.8 Pin States in STOP Mode Pin name I/O P00 to P07 Input mode Output mode AD8 to AD15 P10 to P17 Input mode Output mode AD0 to AD7 P20 to P27 Input mode Output mode A7/A16 ...
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Note: Port registers are used for controlling programmable pull up/pull down pin can be used for an output function (e.g., P71/TO1) and the output function is specified, whether pull up or pull down is selected depends on the ...
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Interrupts Interrupts are controlled by the CPU interrupt mask register SR<IFF2:0> and the built-in interrupt controller. Altogether the TMP93CS40 and TMP93CS41 have the following 29 interrupt sources: Interrupts from the CPU, 9 sources (Software interrupts, and illegal (Undefined) instruction ...
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Interrupt processing Read interrupt vector V. Clear interrupt request flag. Internal operation PUSH General-purpose PUSH interrupt processing SR<IFF2:0> INTNEST PC Interrupt processing User program INTNEST Figure 3.4.1 Interrupt Processing Flowchart Vector V Yes Micro DMA start vector? Data transfer by ...
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General-purpose Interrupt Processing When accepting an interrupt, the CPU operates as follows. In the cases of software interrupts or interrupts generated by the CPU because of attempts to execute illegal instructions, the following steps (1) and (3) are not ...
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Maskable interrupt (main) (INTT0 interrupt routine IFF 2 [1] [2] INTT0 (Level 1) [4] [5] IFF 1 During execution of the main program, the CPU accepts an interrupt request. The CPU then increments IFF so that no ...
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The addresses 008000H to 0080FFH (256 bytes) of the TMP93CS40 and TMP93CS41 are assigned as interrupt vector areas. Table 3.4.1 TMP93CS40/TMP93CS41 Interrupt Table Default Type Interrupt Source Priority 1 Reset, or SWI0 instruction 2 SWI 1 instruction 3 Illegal instruction, ...
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Setting to reset and interrupt vectors 1. Reset vector 8000H 8001H 8002H 8003H The vector base addresses are dependent on the products. Type No. Vector Base Address PC Setting Sequence after Reset TMP93CS40/CS41 TMP93CM40 TMP93PS40 008000H TMP93CW40/CW41 TMP93PW40 2. Interrupt ...
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Setting example: Set the reset vector to 8100H, NMI vector to 9ABCH and INTAD vector to 123456H. ORG 8000H DL 008100H ORG 8020H DL 009ABCH ORG 8070H DL 123456H ORG 8100H ORG 9ABCH ORG ...
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Micro DMA In addition to the conventional interrupt processing, the TMP93CS40 and TMP93CS41 also have a micro DMA function. When an interrupt is accepted, in addition to an interrupt vector, the CPU receives data indicating whether ...
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Figure 3.4.2 Micro DMA Cycle (Count 93CS40-42 TMP93CS40/TMP93CS41 0) 2004-02-10 ...
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Figure 3.4.3 Micro DMA Cycle (Count 93CS40-43 TMP93CS40/TMP93CS41 0) 2004-02-10 ...
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Register configuration (CPU control registers) Channel0 DMAS0 Transfer source address register 0 DMAD0 Transfer destination address register 0 DMAC0 Transfer counter register 0 DMAM0 Transfer mode register 0 Channel1 DMAS1 Transfer source address register 1 DMAD1 Transfer destination address ...
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Transfer mode register details Mode Z: 0 byte transfer, 1 word transfer Transfer destination address INC mode .................................... for I/O to memory (DMADn ) (DMASn) DMACn DMACn 1 if DMACn 0 ...
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Clock condition System clock: fc Clock gear: When the hardware configuration is as follows: DRAM mapping size: DRAM data bus size: DRAM mapping address range: Set the following registers first; refresh ...
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Interrupt Controller Figure 3.4 block diagram of the interrupt circuits. The left half of the diagram shows the interrupt controller; the right half includes the CPU interrupt request signal circuit and the halt release signal circuit. Each ...
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Figure 3.4.4 Block Diagram of Interrupt Controller 93CS40-48 TMP93CS40/TMP93CS41 2004-02-10 ...
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Interrupt priority setting register Symbol Address 7 6 INTAD IADC IADM2 INTE0AD 0070H R INT5 I5C I5M2 INTE45 0071H R INT7 I7C I7M2 INTE67 0072H R INTT1 (Timer1) IT1C IT1M2 INTET10 0073H R/W ...
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External interrupt control Interrupt Input Mode Control Register 7 6 IIMC Bit symbol (007BH) Read/Write After reset Function INT0 input enable (Note 1) 0 INT0 disable (P87 function only) 1 Input enable Note 1: The INT0 pin can also ...
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Micro DMA start vector When the CPU reads the interrupt vector after accepting an interrupt, it simultaneously compares the bits the interrupt vector with each channel’s micro DMA start vector. When the two match, the ...
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Notes The instruction execution unit and the bus interface unit of this CPU operate independently of each other. Therefore, if the instruction used to clear the interrupt request flag of an interrupt is fetched before the interrupt is generated, ...
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Functions of Ports The TMP93CS40 has 79 bits for I/O ports. The TMP93CS41 has 61 bits for I/O ports because port 0, port 1, P30, and P31 are dedicated pins for AD0 to AD7, AD8 to AD15 or A8 ...
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Table 3.5.2 I/O Registers and Specifications (1/2) Port No. Pin No. Port 0 P00 to P07 Input port (Note 1) Output port (Note 1) AD0 to AD7 bus Port 1 P10 to P17 Input port (Note 1) Output port (Note ...
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Table 3.5.3 I/O Registers and Specifications (2/2) Port No. Pin No. Port 7 P70 to P73 Input port (without PU) Input port (with PU) Output port P70 TI0 input (without PU) TI0 input (with PU) P71 TO1 output P72 TO2 ...
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Resetting makes the port pins listed below function as general-purpose I/O ports. I/O pins programmable for input or output are then set to function as input ports, except for P96/XT1 and P97/XT2. A program is needed to set port pins ...
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Figure 3.5.1 shows an example of an interface circuit using some of the pins described in Table 3.5. case when the bus releasing function is used. When the bus is released, neither internal memory nor internal I/O can ...
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Port 0 (P00 to P07) Port 8-bit general-purpose I/O port. I/O can be set on a bit basis using the control register P0CR. Resetting resets all bits of P0CR to “0”, and sets port 0 to ...
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Port 1 (P10 to P17) Port 8-bit general-purpose I/O port. I/O can be set on a bit basis using control register P1CR and function register P1FC. Resetting resets all bits of output latch P1, control register ...
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P0 Bit symbol P07 P06 (0000H) Read/Write After reset 7 P0CR Bit symbol P07C P06C (0002H) Read/Write After reset 0 Function 0: Input 1: Output (when externally accessed, port 0 becomes AD7 to AD0 and P0CR is cleared to ...
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Port 2 (P20 to P27) Port 8-bit general-purpose I/O port. I/O can be set on a bit basis using the control register P2CR and function register P2FC. Resetting resets all bits of output latch P2, control ...
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P2 Bit symbol P27 P26 (0006H) Read/Write After reset 7 P2CR Bit symbol P27C P26C (0008H) Read/Write After reset 0 Function 7 P2FC Bit symbol P27F P26F (0009H) Read/Write After reset 0 Function Note 1: Read-modify-write is prohibited for ...
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Port 3 (P30 to P37) Port 8-bit general-purpose I/O port. I/O can be set on a bit basis, but note that P30 and P31 are used for output only. I/O is set using control register P3CR ...
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Reset For TMP93CS41 Function control (on bit basis) P3FC write S Output A latch Selector P3 write read Reset Direction control (on bit basis) P3CR write Function control (on bit basis) P3FC write S S ...
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Reset Direction control (on bit basis) P3CR write S Output latch P3 write S B Selector A P3 read Internal WAIT Reset Direction control (on bit basis) P3CR write Function control (on bit basis) P3FC write S Output latch P3 ...
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P3 Bit symbol P37 P36 (0007H) Read/Write After reset 1 Function 7 P3CR Bit symbol P37C P36C (000AH) Read/Write After reset 0 Function 7 P3FC Bit symbol P37F P36F (000BH) Read/Write After reset 0 Function 0: Port 0: Port ...
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Port 4 (P40 to P42) Port 3-bit general-purpose I/O port. I/O can be set on a bit basis using control register P4CR and function register P4FC. Resetting does the following: - Sets the P40 and P41 ...
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Reset Direction control (on bit basis) P4CR write Function control (on bit basis) P4FC write S Output S A latch Selector P4 write CS0 CAS 0 CS1 S B Selector A P4 read Reset Direction control (on ...
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P4 Bit symbol (000CH) Read/Write After reset Function 7 P4CR Bit symbol (000EH) Read/Write After reset Function 7 P4FC Bit symbol (0010H) Read/Write After reset Function Note 1: Read-modify-write is prohibited for registers P4CR and P4FC. Note 2: When ...
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Port 5 (P50 to P57) Port 8-bit input port, also used as an analog input pin for the internal AD converter. Port 5 read Conversion AD read 7 P5 Bit symbol P57 P56 (000DH) Read/Write After ...
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Port 6 (P60 to P67) Port 8-bit general-purpose I/O port. I/O can be set on a bit basis. Resetting sets port input port and connects a pull-up resistor. It also sets all bits ...
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P6 Bit symbol P67 (0012H) Read/Write After reset 1 Function 7 P6CR Bit symbol P67C P66C (0014H) Read/Write After reset 0 Function 7 P6FC Bit symbol P67F P66F (0016H) Read/Write After reset 0 Function 0: Port Note 1: Read-modify-write ...
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Port 7 (P70 to P73) Port 4-bit general-purpose I/O port. I/O can be set on a bit basis. Resetting sets port input port and connects a pull-up resistor. In addition to functioning as ...
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P7 Bit symbol (0013H) Read/Write After reset Function 7 P7CR Bit symbol (0015H) Read/Write After reset Function 7 P7FC Bit symbol (0017H) Read/Write After reset Function Note 1: Read-modify-write is prohibited for registers P7CR and P7FC. Note 2: When ...
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Port 8 (P80 to P87) Port 8-bit general-purpose I/O port. I/O can be set on a bit basis. Resetting sets port input port and connects a pull-up resistor. It also sets all bits ...
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P87 (INT0) Port general-purpose I/O port, and is also used as an INT0 pin for external interrupt request input. Reset Direction control (on bit basis) P8CR write S Output latch P8 write S Selector P8 read ...
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P8 Bit symbol P87 P86 (0018H) Read/Write After reset 1 Function 7 P8CR Bit symbol P87C P86C (001AH) Read/Write After reset 0 Function 7 P8FC Bit symbol P86F (001CH) Read/Write W After reset Function 0: Port 1: TO6 Note ...
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Port 9 (P90 to P97) x Ports Ports constitute a 6-bit general-purpose I/O ports. I/Os can be set on a bit basis. Resetting sets P90 to P95 to an input port and connects ...
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Reset Direction control (on bit basis) P9CR write Function control (on bit basis) P9FC write S A Output latch P9 write B TXD0, TXD1 P9 read Figure 3.5.21 Ports 90 and 93 (2) Port 91, 94 (RXD0, RXD1) Ports 91 ...
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Port 92 ( /SCLK0) CTS0 Port I/O port, and is also used as a for serial channels. Reset Direction control (on bit basis) P9CR write Function control (on bit basis) P9FC write S Output latch S ...
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Port 95 (SCLK1) Port general-purpose I/O port also used as a SCLK1 I/O pin for serial channel 1. Reset Direction control (on bit basis) P9CR write Function control (on bit basis) P9FC write S ...
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Port 96 (XT1), 97 (XT2) Ports 96 and 97 are general purpose I/O ports. They are also used as low-frequency oscillator connecting pins. Reset S Bus 6 Direction control (on bit basis) P9CR write S Bus 6 Output latch ...
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P9 Bit symbol P97 P96 (0019H) Read/Write After reset Output mode Function 1 7 P9CR Bit symbol P97C P96C (001BH) Read/Write After reset 1 Function Note: Port 96 and 97’s output buffer is an open-drain output type. 7 P9FC ...
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Port A (PA0 to PA7) Port 8-bit general-purpose I/O port. I/Os can be set on a bit basis by control register PACR. Resetting sets port input port by resetting PACR. It also sets ...
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Reset R BUS 7 Direction control (on bit basis) PACR write R BUS 2 Function control (on bit basis) CKOCR write S BUS 7 Output latch PA write S Selector BUS 7 PA read f A FPH Selector f B ...
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PA Bit symbol PA7 PA6 (001EH) Read/Write After reset 1 Function 7 PACR Bit symbol PA7C PA6C (001FH) Read/Write After reset 0 Function 7 CKOCR Bit symbol (006DH) Read/Write After reset Function Note 1: Read-modify-write is prohibited for registers ...
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Chip Select/Wait Controller, AM8/ The TMP93CS40 and TMP93CS41 have a built-in chip select/wait controller used to control chip select ( to pins), wait ( CS0 CS2 three block address areas. In addition, the AM8/ AM16 3.6.1 AM8/ pin AM16 ...
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Address/Data Bus Pins Port 0, port 1 and port 2 function as an address and data bus for connecting the microcontroller to the external memories and I/O peripherals. 1. Products TMP93CS41F (Note 4) Number of Address max24 (to 16 ...
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Control Registers Table 3.6.1 shows control registers. One block of the address areas is controlled by each of the 1-byte CS/WAIT control registers B0CS, B1CS, and B2CS. (1) Master enable bits Bit7 of the control registers (B0E, B1E, and ...
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Address area specification Control register bits 1 and 0 <B0C1:0, B1C1:0, and B2C1:0> are used to specify the target address area. Setting these bits to 00 enables settings (e.g., state, and bus size) as follows: * The CS0 setting ...
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Table 3.6.2 Dynamic Bus Sizing Operand Data Operand Start Memory Data Size Address bits (Even number) 16 bits 2n 1 (Odd number) 16 bits 16 bits 2n 0 (Even number) 16 bits 2n 1 (Odd number) 16 ...
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Chip Select Addresses Image An image of the actual addresses which can be specified by chip select is shown below. Out of the whole memory area, address areas that can be specified are divided into four parts. Addresses from ...
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Example of Usage (1) Example of usage -1 Figure 3.6 example in which an external memory is connected to the TMP93CS41. In this example, a ROM is connected using a 16-bit bus; a RAM is connected using ...
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Example of usage -2 Figure 3.6 example in which an external memory is connected to the TMP93CS41. In this example, a ROM, RAM, and I/O are each connected using an 8-bit bus. TMP93CS41 74HC573 CS0 CS1 D ...
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Example of usage -3 Figure 3.6 example in which an external memory is connected to the TMP93CS40. In this example, a 128-Kbyte ROM is connected using a 16-bit bus, and a 256-Kbyte RAM is connected using a ...
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Timers The TMP93CS40 and S41 contain two 8-bit timers (Timers 0 and 1), each of which can be operated independently. The cascade connection also allows these timers to be used together as a 16-bit timer. The following four ...
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Figure 3.7.1 Block Diagram of 8-Bit Timers (Timers 0 and 1) 93CS40-97 TMP93CS40/TMP93CS41 20004-02-10 ...
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Prescaler There are 9-bit prescaler and prescaler clock selection registers to generate input clock signals for the 8-bit timers 0 and 1, the 16-bit timers 4 and 5, and the serial interfaces 0 and 1. Figure 3.7.2 shows the ...
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The timer clock selected among f prescaler. The selection is made by system clock control register SYSCR0<PRCK1:0>. Resetting sets <PRCK1:0> to 00, which selects the f The 8-bit timers 0 and 1 select among 4 clock inputs: T1, T4, T16, ...
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Timer registers These are 8-bit registers for setting a time interval. When the values of the timer registers match the values of the corresponding up counters, the comparator match detect signal becomes active. If the set value is 00H, ...
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Comparator A comparator compares the value in the up counter with the values to which the timer register is set. When they match, the up counter is cleared to zero and an interrupt signal (INTT0 and INTT1) is generated. ...
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Bit symbol PRRUN TRUN (0020H) Read/Write R/W After reset 0 Function Note: TRUN<bit6> is read as “1” SYSCR0 Bit symbol XEN XTEN (006EH) Read/Write After reset 1 0 Function High- Low- frequency frequency oscillator oscillator (fc) ...
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TMOD Bit symbol T10M1 T10M0 (0024H) Read/Write After reset 0 0 Function Operation mode Prohibit read- 00: 8-bit timer modify- 01: 16-bit timer write 10: 8-bit PPG 11: 8-bit PWM Figure 3.7.5 Timer Mode Control Register (TMOD) 5 ...
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TFFCR Bit symbol (0025H) Read/Write After reset Function Note: TFFCR<bit7:5>, <bit3:2> are read as “1”. Figure 3.7.6 Timer Flip-Flop Control Register (TFFCR DBEN TFF1C1 TFF1C0 R Double 00: Invert TFF1 buffer 01: ...
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The operation of 8-bit timers will be described below: (1) 8-bit timer mode Two interval timers, designated “0” and “1”, can be used independently as 8-bit interval timers. All interval timers operate in the same manner, and thus only the ...
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Generating a 50% duty, square-wave pulse The timer flip-flop (TFF1) is inverted at constant intervals, and its status is output to timer output pin (TO1). Example: To output a 2.4 s square wave pulse from the TO1 pin at ...
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Making timer 1 count up by matching the signal from the timer 0 comparator Set the 8-bit timer mode, and set the comparator output of timer 0 as the input clock to timer 1. Comparator output (Timer 0 match) ...
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The comparator signal is output from timer 0 each time the up counter UC0 matches TREG0, when the up counter UC0 is not to be cleared. With the timer 1 comparator, the match detect signal is output at each comparator ...
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In this mode, a programmable square wave is generated by inverting the timer output each time the 8-bit up counter (UC0) matches the timer registers TREG0 and TREG1. However necessary for the set value of TREG0 to be ...
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Example: Generating 1/4 duty 62.5 kHz pulse ( Clock condition System clock: Clock gear: Prescaler clock: Calculate the value to be set in the timer register. To obtain a frequency of 62.5 kHz, the pulse cycle time ...
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PWM output mode This mode is valid only for timer 0. In this mode, the maximum 8-bit resolution of the PWM pulse can be output. The PWM pulse is output to the TO1 pin (also used as P71) ...
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In this mode, the value of the register buffer will be shifted into TREG0 overflow is detected while the double buffer of TREG0 is enabled. Use of the double buffer makes easy the handling of small-duty waves. ...
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Select System Select Gear Value Clock Prescaler Clock <GEAR2:0> <SYSCK> <PRCK1:0> 1 (fs) XXX 000 (fc) 00 001 (fc/ (fc) 010 (fc/4) FPH 011 (fc/8) 100 (fc/16) 01 XXX (Low-frequency XXX clock) 10 XXX XXX (fc/16 clock) ...
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PWM Timers The TMP93CS40 and TMP93CS41 have two built-in 8-bit PWM timers (Timers 2 and 3). Each of these timers has two operating modes. x 8-bit PWM output mode x 8-bit interval timer mode Figure 3.8.1, Figure 3.8.2 ...
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TRUN<P0RUN> Run IP1 Clock IP4 8-bit up counter control (UC2) IP16 P0MOD<T2CLK1:0> 8-bit comparator (CP2) 8-bit timer register TREG2 Register buffer Internal data bus Figure 3.8.1 Block Diagram of 8-Bit PWM Timer 0 (Timer 2) P0MOD<PWM0M> Clear Overflow n ...
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TRUN<P1RUN> Run IP1 Clock IP4 8-bit up counter control IP16 (UC3) P1MOD<T3CLK1:0> 8-bit comparator (CP3) 8-bit timer register TREG3 Register buffer Internal data bus Figure 3.8.2 Block Diagram of 8-Bit PWM Timer 1 (Timer 3) P1MOD<PWM1M> Clear Overflow n ...
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Prescaler There are 5-bit prescaler and prescaler clock selection registers to generate clock inputs for 8-bit PWM timers 0 and 1. Figure 3.8.3 shows the block diagram. Table 3.8.1 shows prescaler clock resolution into 8-bit PWM timers 0 and ...
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The clock selected among f FPH The selection is made by the system clock control register SYSCR0<PRCK1:0>. Resetting sets <PRCK1:0> to 00, selecting the f TRUN<PRRUN> register which controls this prescaler, is also used for the other timers. So, this ...
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Up counter Comparator Timer register (TREG2) Register buffer Write Internal data bus Figure 3.8.4 Structure of Timer Registers 2 Memory addresses of the timer registers are as follows: TREG2: 000026H (PWM timer 0) TREG3: 000027H (PWM timer 1) The timer ...
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Bit symbol FF2RD DB2EN P0MOD (0028H) Read/Write R After reset 0 Function Flip-flop 1: Double (Flip-flop buffer 2 2) output enable data Read-modify-write is prohibited. Figure 3.8.5 8-bit PWM0 Mode Control Register PWM0INT ...
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Bit symbol FF3RD DB3EN P1MOD (0029H) Read/Write R After reset 0 Function Flip-flop 1: Double (Flip-flop buffer 3 3) output enable data Read-modify-write is prohibited. Figure 3.8.6 8-Bit PWM 1 Mode Control Register ...
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Bit symbol FF3C1 FF3C0 PFFCR (002AH) Read/Write W After reset 1 1 Function 00: Don’t care 01: Set TFF3 10: Clear TFF3 11: Don’t care Figure 3.8.7 8-Bit PWM Flip-flop Control Register FF3TRG1 FF3TRG0 ...
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Bit symbol PRRUN TRUN (0020H) Read/Write R/W After reset 0 Function Note: TRUN<bit6> is read as “1” SYSCR0 Bit symbol XEN XTEN (006EH) Read/Write After reset 1 0 Function High- Low- frequency frequency oscillator oscillator (fc) ...
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The following explains PWM timer operations. (1) PWM timer mode PWM output changes under the following two conditions. Condition 1: x TFF2 is cleared when the value in the up counter (UC2) matches the value set in the TREG2. x ...
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Figure 3.8. block diagram of this mode. IP1 IP4 IP16 8-bit up counter Clock control P0MOD<T2CLK1:0> comparator timer register (TREG2) B Shift trigger Selector A S TREG2 WR Register buffer P0MOD<DB2EN> Internal data bus Figure 3.8.10 Block Diagram ...
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Example: To output the following PWM waves to the TO2 pin using PWM0 MHz Clock condition System clock: Clock gear: Prescaler clock implement 25 the PWM cycle regulated by IP1 ...
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Select System Select Gear Value Clock Prescaler Clock <GEAR2:0> <SYSCK> <PRCK1:0> 1 (fs) XXX 000 (fc) 00 001 (fc/ (fc) 010 (fc/4) FPH 011 (fc/8) 100 (fc/16) 01 XXX XXX (Low frequency) 10 XXX XXX (fc/16 clock) ...
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Generating a 50% square wave To generate a 50% square wave, invert the timer flip-flop at a fixed interval and output the timer flip-flop value to the timer output pin (TO2). Example: To output a 2.4 Ps square wave ...
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This mode is as shown in Figure 3.8.13 below. IP1 IP4 IP16 Clock control P0MOD<T2CLK1:0> B Shift trigger Selector A S TREG2 WR P0MOD<DB2EN> Register write Figure 3.8.13 Block Diagram of 8-Bit Timer Mode TMP93CS40/TMP93CS41 8-bit up counter Clear (UC2) ...
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Timers The TMP93CS40 and TMP93CS41 contain two multifunctional 16-bit timer/event counters (Timer 4 and timer 5) which support the following operation modes. x 16-bit interval timer mode x 16-bit event counter mode x 16-bit programmable pulse generation (PPG) ...
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INT4 INT5 Figure 3.9.1 Block Diagram of 16-Bit Timer (Timer 4) 93CS40-131 TMP93CS40/TMP93CS41 2004-02-10 ...
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INT6 INT7 Figure 3.9.2 Block Diagram of 16-Bit Timer (Timer 5) 93CS40-132 TMP93CS40/TMP93CS41 2004-02-10 ...
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Bit symbol CAP2T5 EQ5T5 T4MOD (0038H) Read/Write R/W After reset 0 0 Function TFF5 invert trigger 0: Disable trigger 1: Enable trigger Inverted Inverted when the when the UC value is up counter latched to matches CAP2 TREG5 ...
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Bit symbol CAP2T5 EQ5T5 T4MOD (0038H) Read/Write R/W After reset 0 0 Function TFF5 invert trigger 0: Disable trigger 1: Enable trigger Inverted Inverted when the when the UC value is up counter latched to matches CAP2 TREG5 ...
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Bit symbol TFF5C1 TFF5C0 T4FFCR (0039H) Read/Write W After reset 1 1 Function 00: Invert TFF5 01: Set TFF5 10: Clear TFF5 11: Don’t care * Always read as “11” Figure 3.9.5 16-Bit Timer 4 F/F Control (T4FFCR) ...
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Bit symbol T5MOD (0048H) Read/Write After reset Function Figure 3.9.6 16-Bit Timer Mode Control Register (T5MOD) (1/ CAP3IN CAP34M1 CAP34M0 CLE W R/W R Software Capture timing 1: UC5 ...
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Bit symbol T5MOD (0048H) Read/Write After reset Function Figure 3.9.7 16-Bit Timer Control Register (T5MOD) (2/ CAP3IN CAP34M1 CAP34M0 CLE W R/W R Software Capture timing 1: UC5 capture ...
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Bit symbol T5FFCR (0049H) Read/Write After reset Function Figure 3.9.8 16-Bit Timer 5 F/F Control (T5FFCR CAP4T6 CAP3T6 EQ7T6 EQ6T6 R/W R/W R/W R TFF6 invert trigger 0: Disable trigger ...
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Bit symbol QCU T45CR (003AH) Read/Write R/W After reset 0 Function Warm-up timer control Note 1: In case of not using the 7 stage binary counter as a warm-up timer, a stable clock signal must be input from ...
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Bit symbol PRRUN TRUN (0020H) Read/Write R/W After reset 0 Function Note: TRUN<bit6> is always read as “1” SYSCR0 Bit symbol XEN XTEN (006EH) Read/Write After reset 1 0 Function High- Low- frequency frequency oscillator (fc) ...
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Prescaler There are 9-bit prescaler and prescaler clock-selection registers to generate input clock signals for 8-bit timers 0 and 1, 16-bit timers 4 and 5, and serial interfaces 0 and 1. Figure 3.9.11 shows the block diagram. Table 3.9.1 ...
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The clock selected from among f prescaler. This selection is made by prescaler clock selection register SYSCR0<PRCK1:0>. Resetting sets <PRCK1:0> to 00, selecting the f The 16-bit timers 4 and 5 select among 3 clock inputs: IT1, IT4, and IT16 ...
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TREG4 Upper 8 bits Lower 8 bits (TREG4H) (TREG4L) 000031H 000030H TREG6 Upper 8 bits Lower 8 bits (TREG6H) (TREG6L) 000041H 000040H The TREG4 timer register is a double buffer structure, which is paired with a register buffer. The timer ...
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Capture input control This circuit controls the timing of latching the value of up counter UC4 into CAP1 and CAP2. The latch timing T4MOD<CAP12M1:0>. There are four possible settings: x When T4MOD<CAP12M1:0> Capture function is disabled. Disable is the ...
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Generating interrupts at fixed intervals: In this example, the interval time is set in the timer register TREG5 to generate the interrupt INTTR5 TRUN 0 m ...
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T45CR TRUN TREG4 * * * * * * * * * * * m * TREG5 ...
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Figure 3.9.14 shows the block diagram of this mode. TI4 IT1 Selector IT4 IT16 16-bit comparator TREG4 Selector TREG4-WR Register buffer 4 T45CR<DB4EN> Figure 3.9.14 Block Diagram of 16-Bit PPG Mode (4) Application examples of the capture function It is ...
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One-shot pulse output from external trigger pulse To program this application, set the up counter UC4 in free-running mode with the internal input clock, input the external trigger pulse from the TI4 pin, and load the value of the ...
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Setting example: To output one-shot pulse to the external trigger pulse to TI4 pin, with 3 ms delay Clock condition System clock: Clock gear: Prescaler clock: f Main setting T4MOD ...
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Count clock (Internal clock) c TI4 pin input INT4 occurrence. Load the up counter (External trigger pulse) value into capture register 1 (CAP1). Match with TREG5 Enable inversion Timer output pin TO4 Pulse width Enable inversion caused by loading of ...
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Pulse width measurement This mode allows measurement of the H level width of an external pulse. While keeping the 16-bit timer/event counter counting (Free running) with the internal clock input, the external pulse is input via the TI4 pin. ...
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Count clock (Internal clock TI4 pin input TI5 pin input Loading UC4 into CAP1 Loading UC4 into CAP2 INT4 INT5 Time difference Figure 3.9.19 Time Difference Measurement (5) Different phased pulses output mode (This mode can be used ...
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Table 3.9.2 Timer Output Periods in Different Phased Pulse Output Mode (Expressed as counter overflow time) System Clock Prescaler Clock Selected Selected <SYSCK> <PRCK1:0> 1 (fs (fc) FPH 01 XXX (Low-frequency clock) 10 XXX (fc/16 clock) ...
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Stepping Motor Control/Pattern Generation Port The TMP93CS40/TMP93CS41 contains two 4-bit hardware stepping motor control/pattern generation channels, PG0 and PG1, (hereinafter called PG) which actuate in synchronization with the (8-bit/16-bit) timers. PG (PG0 and PG1) shares the 8-bit input/output port ...
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Bit symbol PAT1 CCW1 PG01CR (004EH) Read/Write After reset 0 0 Function PG1 write PG1 rotation mode direction 0: 8-bit write 0: Normal 1: 4-bit write rotation 1: Reverse rotation Figure 3.10.2 Pattern Generation Control Register (PG01CR) (1/2) ...
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Bit symbol PAT1 CCW1 PG01CR (004EH) Read/Write After reset 0 0 Function PG1 write PG1 rotation mode direction 0: 8-bit write 0: Normal 1: 4-bit write rotation 1: Reverse rotation Figure 3.10.3 Pattern Generation Control Register (PG01CR) (2/2) ...
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PG0REG Bit symbol PG03 PG02 (004CH) Read/Write After reset 0 0 Prohibit Function Pattern generation 0 (PG0) output latch register read- PG0 can be read by reading the modify- port (P6) that is assigned to PG write Figure ...
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Bit symbol QCU T45CR (003AH) Read/Write R/W After reset 0 Function Watchdog/ warm-up timer control Note 1: When the 7-stage binary counter is not used as a warm-up timer, a stable clock must be input from an external ...
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Figure 3.10.7 Connection between Timer and Pattern Generator (1) Pattern generation mode When PG01CR<PAT0> written from the CPU to the shift alternate register only. The pattern data is ...
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Shift alternate register SA03 BUS3 SA02 BUS2 SA01 BUS1 SA00 BUS0 Shift performed on shift trigger from timer Figure 3.10.8 Pattern Generation Mode Block Diagram (PG0) In pattern generation mode, only writing to the output latch can be disabled by ...
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Stepping motor control mode 1. 4-phase 1-step/2-step excitation Figure 3.10.9 and Figure 3.10.10 show the output waveforms for 4-phase 1 excitation and 4-phase 2 excitation respectively when channel 0 (PG0) is selected. a. Normal rotation Trigger signal from timer ...
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Trigger signal from timer PG00 (P60 PG01 (P61 PG02 (P62) PG03 (P63 Initial value of PG0REG 1100uuuu Figure 3.10.10 Output Waveforms for 4-phase 2-step Excitation (Normal rotation) The ...
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Figure 3.10.12 shows the output waveforms for 4-phase 1-2 step excitation when channel 0 is selected. a. Normal rotation Trigger signal from timer PG00 (P60 PG01 (P61) ...
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The initialization sequence for 4-phase 1-2 step excitation is as follows. By rearranging the initial value b0, three consecutive bits are set to 1 ...
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Setting example: To drive channel 0 (PG0) using 4-phase 1-2 step excitation (Normal rotation) when timer 0 is selected, set each register as follows TRUN TMOD ...
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When using a trigger signal from timer 4, set either T4FFCR<EQ5T4> or T4MOD<EQ5T5> to “1”; a trigger is generated when the value in UC4 and the value in TREG5 match. When using a trigger signal from timer 5, set T5FFCR<EQ7T6> ...
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Serial Channel The TMP93CS40/TMP93CS41 includes two serial I/O channels. Channel 0 and channel 1 select UART mode (Asynchronous transmission) or I/O interface mode (Synchronous transmission). The serial channel has the following operation modes: I/O interface mode (Channel 0 and ...
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Mode 0 (I/O interface mode) Bit0 1 2 Transfer direction Mode 1 (7-bit UART mode) Start Bit0 1 No parity Parity Start Bit0 1 Mode 2 (8-bit UART mode) Start Bit0 1 No parity Parity Start Bit0 1 Mode 3 ...
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The serial channel has buffer registers for temporarily storing transmitted or received data during transmitting and receiving operations. This is so that transmitting and receiving operations can be performed independently (Full duplex). However, in I/O interface mode, the SCLK (Serial ...
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Bit symbol TB8 CTSE SC0MOD Read/Write (0052H) After reset Undefind 0 Function Transfer Handshake data 0: CTS bit8 disable 1: CTS enable Note: SC1MOD (56H channel 1. Figure 3.11.2 Serial Mode Control Register (Channel 0, SC0MOD) ...
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Bit symbol RB8 EVEN SC0CR (0051H) Read/Write R After reset Undefined 0 Function Received Parity data 0: Odd bit8 1: Even Note 1: Serial control register for channel 1 is SC1CR (55H). Note 2: As all error flags ...
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BR0CR (0053H) Bit symbol Read/Write R/W After reset 0 Function Always fixed to 0 Note 1: Serial control register for channel 1 is BR1CR (57H). Note 2: Set TRUN<PRRUN> when the baud rate generator is used. ...
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Bit symbol TB8 SC1MOD (0056H) Read/Write After reset Undefined 0 Function Transferred Always data bit8 fixed to 0 Figure 3.11.6 Serial Mode Control Register (Channel 1, SC1MOD RXE WU SM1 SM0 R ...
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SC1CR Bit symbol RB8 EVEN (0055H) Read/Write R After reset Undefined 0 Function Received Parity data bit8 0: Odd 1: Even Note: As all error flags are cleared after reading, do not test a single bit only with ...
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Bit symbol BR1CR (0057H) Read/Write R/W After reset 0 Function Always fixed to 0 Note 1: To use baud rate generator, set TRUN<PRRUN> to “1”, putting the prescaler in RUN. Note 2: BR1CR<bit6> is always “1”. Note 3: ...
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P9FC Bit symbol (001DH) Read/Write After reset Function Read-modify-write is prohibited Figure 3.11.10 Port 9 Function Register (P9FC Bit symbol ODE (0058H) Read/Write After reset Function Note: ODE<bit7:2> is always “1”. Figure 3.11.11 Port 9 Open-drain ...
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Configuration Figure 3.11.12 shows the block diagram for serial channel 0. Serial clock generation circuit BR0CR<BR0CK1:0> <BR0S3:0> T32 Baud rate generator System clock SYS 2 SCLK0 (Shared by P92) SCLK0 (Shared by P92) Receive ...
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Figure 3.11.13 shows the block diagram for serial channel 1. Serial clock generation circuit BR1CR<BR1CK1:0> <BR1S3:0> T32 Baud rate generator System clock SYS 2 SCLK1 input (Shared by P95) SCLK1 output (Shared by P95) Receive ...
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Prescaler 9-bit prescaler and prescaler clock selection registers generate input clocks for 8-bit timer 0, 1, 16-bit timer 4, 5, and serial interface 0, 1. Figure 3.11.15 shows the block diagram. Table 3.11.1 shows how the prescaler clock is ...
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The selected clock (f clock, fc/16 clock or fs clock) is divided by 4 and input to the FPH prescaler. This selection is made by the prescaler clock selection register SYSCR0<PRCK1:0>. Resetting sets <PRCK1:0> to “00” and selects the f ...
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Baud rate generator The baud rate generator is a circuit that generates transmission and receiving clocks to determine the transfer rate of the serial channel. The input clock to the baud rate generator, T0, T2, T8, or T32, is ...
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Table 3.11.2 Selection of Transfer Rate (1) (when baud rate generator is used) Input clock fc [MHz] Frequency divisor 2 4 9.830400 12.288000 A 3 14.745600 6 C Note 1: Transfer rates in I/O interface mode are ...
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Serial clock generation circuit This circuit generates the basic clock for transmitting and receiving data. I/O interface mode In SCLK output mode with a setting of SC0CR<IOC> generated by dividing the output of the baud rate generator by 2, ...
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Receiving buffer To prevent overrun errors, the receiving buffer has a double buffer structure. Received data is stored bit by bit in receiving buffer 1 (Shift register type). When 7 bits or 8 bits of data are stored in ...
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Handshake function Serial channel 0 has a frame; thus, overrun errors can be avoided. The handshake function is enabled/disabled by SC0MOD<CTSE>. When the CTS0 data transmission is halted until the interrupt is generated, it requests the next data transmission to ...
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Transmission buffer The transmission buffer (SC0BUF) shifts out and sends the transmission data written from the CPU in order starting with the least significant bit (LSB). When all bits have been shifted out, the transmission buffer becomes empty and ...
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Signal generating timing 1) In UART mode Receive Mode 9 Bits Timing for interrupt Around center of bit8 generation Timing for framing Around center of generation stop bit Timing for parity error generation Timing for overrun Around center of ...
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Operational Description (1) Mode 0 (I/O interface mode) This mode is used to increase the number of I/O pins available for transmitting data to or receiving data from an external shift register. This mode encompasses the SCLK output mode ...
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Transmission In SCLK output mode, 8-bit data and the synchronous clock are output from the TXD0 pin and SCLK0 pin respectively, each time the CPU writes data to the transmission buffer. When all data has been output, INTES0<ITX0C> will ...
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Receiving In SCLK output mode, the synchronous clock is output from the SCLK0 pin and data are shifted into the receiving buffer 1 whenever the receive interrupt flag INTES0<IRX0C> is cleared by a read of the received data. When ...
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Mode 1 (7-bit UART mode) 7-bit mode can be selected by setting the serial channel mode register SC0MOD<SM1:0> to 01. In this mode, a parity bit can be added. The parity bit is enabled or disabled by serial channel ...
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Main setting P9CR X X SC0MOD SC0CR BR0CR TRUN 1 X INTES0 Interrupt processing Acc SC0CR AND 00011100 if Acc 0 then ERROR Acc SC0BUF ...
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Protocol 1. Select 9-bit UART mode for the master and slave controllers. 2. Set the SC0MOD<WU> bit of each slave controller enable data receiving. 3. The master controller transmits one-frame data including the 8-bit select code for ...
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Setting example: To link two slave controllers serially with the master controller, and use the internal clock 1 as the transfer clock. TXD RXD Master Since serial channels 0 and 1 operate in exactly the same way, channel 0 only ...
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Analog/Digital Converter The TMP93CS40/S41 contains an analog/digital converter (AD converter) with 8-channel analog input that features 10-bit successive approximation. Figure 3.12.1 shows the block diagram for the AD converter. 8-channel analog input pins (AN7 to AN0) are shared by ...
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ADMOD1 Bit symbol EOCF ADBF (005EH) Read/Write R After reset Function conversion conversion END flag BUSY flag 1: End 1: Busy Figure 3.12.2 AD Control Register (1/2) TMP93CS40/TMP93CS41 REPET SCAN ...
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Bit symbol ADMOD2 VREFON Read/Write (005FH) R/W After reset 1 Function String resistance ON/OFF Figure 3.12.3 AD Control Register (2/2) TMP93CS40/TMP93CS41 SPEED1 SPEED0 ADCH2 R Conversion speed Analog input channel selection ...
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ADREG04L Bit symbol ADR01 ADR00 (0060H) Read/Write R After reset Undefined Function Lower 2 bits of AD result for AN0 or AN4 are stored. 7 ADREG04H Bit symbol ADR09 ADR08 (0061H) Read/Write After reset Function Upper 8 bits of ...