ZL30407 Zarlink Semiconductor, ZL30407 Datasheet
ZL30407
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ZL30407 Summary of contents
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... Synchronization for SDH and SONET Network Elements • Clock generation for ST-BUS and GCI backplanes Description The ZL30407 is a Network Element Phase-Locked Loop designed to synchronize SDH and SONET systems. In addition, it generates multiple clocks for legacy PDH equipment and provides timing for ST- BUS and GCI backplanes. ...
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... The filtering characteristics of the PLL are hardware or software selectable and they do not require any external adjustable components. The ZL30407 uses an external 20 MHz Master Clock Oscillator to provide a stable timing source for the HOLDOVER operation. The ZL30407 operates from a single 3.3 V power supply and offers tolerant microprocessor interface. ZL30407 2 Zarlink Semiconductor Inc ...
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... Status Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.2 Software Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.2.1 Control Bits 4.2.2 ZL30407 Register Map 5.0 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1 ZL30407 Mode Switching - Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1.1 System Start-up Sequence: FREE-RUN --> HOLDOVER --> NORMAL . . . . . . . . . . . . . . . . . . . . . 34 5.1.2 Single Reference Operation: NORMAL --> AUTO HOLDOVER --> NORMAL . . . . . . . . . . . . . . . . 35 5.1.3 Single 8 kHz Reference Operation: NORMAL --> AUTO HOLDOVER--> HOLDOVER --> NORMAL 36 5.1.4 Dual Reference Operation: NORMAL --> AUTO HOLDOVER--> HOLDOVER --> NORMAL ...
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... Figure 3 - Core PLL Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 4 - C34/C44, C155o Clock Generation Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 5 - ZL30407 State Machine in Software Control configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 6 - ZL30407 State Machine in Hardware Control configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 7 - Hardware and Software Control Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 8 - Primary and Secondary Reference Out of Range Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 9 - Transition From Free-run to Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 10 - Automatic Entry into Auto Holdover State and Recovery into Normal Mode ...
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... Table 1 - Loop Filter Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 2 - Operating Modes and States Table 3 - Filter Characteristic Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 4 - Reference Source Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 5 - ZL30407 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 6 - Control Register 1 (R/ Table 7 - Status Register 1 ( Table 8 - Control Register 2 (R/ Table 9 - Phase Offset Register 2 (R/ Table 10 - Phase Offset Register 1 (R/ Table 11 - Device ID Register (R) ...
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... Changes from March 2006 Issue to November 2006 Issue. Page, section, figure and table numbers refer to this current issue. Page Item 47 Figure 21 Changes from November 2004 Issue to March 2006 Issue. Page, section, figure and table numbers refer to this current issue. Page Item 2.0 ZL30407 Pinout 2.1 Pin Connections SECOR OE CS RESET ...
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... The logic level at this input is sampled by the rising edge of the F8o frame pulse. Connect to ground in Software Control. Mode Select 2 (Input). The MS2 and MS1 pins select the ZL30407 mode of operation (Normal, Holdover or Free-run), see Table 2 on page 22 for details. The logic level at this input is sampled by the rising edge of the F8o frame pulse ...
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... RefSel control input. This pin is internally pulled up to VDD. Primary Reference (Input). This input is used as a primary reference source for synchronization. The ZL30407 can synchronize to the falling edge of the 8 kHz, 1.544 MHz or 2.048 MHz clocks and the rising edge of the 19.44 MHz clock ...
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... C19o 47 RefSel 48 RefAlign ZL30407 Description IEEE1149.1a Test Data Output (CMOS output). JTAG serial data is output on this pin on the falling edge of Tclk clock. If not used, this pin should be left unconnected. IEEE1149.1a Test Mode Selection (3.3 V input). JTAG signal that controls the state transition on the TAP controller. This pin is internally pulled up to VDD. If not used, this pin should be left unconnected ...
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... Holdover mode. No internal bonding Connection. Leave unconnected. Lock Indicator (CMOS output). Logic high at this output indicates that ZL30407 is locked to the input reference. See LOCK bit description in Status Register 1 and Section 3.2.4, Lock Indicator (LOCK) for details. No internal bonding Connection. Leave unconnected. ...
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... RESET state for a duration of 625 Ps. Hardware/Software Control (Input). If this pin it tied low, the ZL30407 is controlled via the microport tied high, the ZL30407 is controlled via the control pins MS1, MS2, FCS, RefSel, RefAlign, E3/DS3 and E3DS3/OC3. Data 0 to Data tolerant three-state I/O). These ports combined with ports form the bi-directional data bus of the microprocessor interface (D0 is the least significant bit) ...
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... Core PLLs without altering the transfer function of the Core PLL. 3.2 Core PLL The most critical element of the ZL30407 is its Core PLL, which generates a phase-locked clock, filters jitter and wander and suppresses input phase transients. All of these features are in agreement with international standards: • ...
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... In Normal mode, the clock generated by the DCO is phase-locked to the input reference signal and band-limited to meet network synchronization standards. The ZL30407 provides four software programmable (FCS bit in Control Reg 1 and FCS2 bit in Control Reg 3) and two hardware selectable (FCS pin) filtering options. The filtering ...
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... Using RefAlign with 1.544 MHz, 2.048 MHz or 19.44 MHz Reference If the ZL30407 is locked to a 1.544 MHz, 2.048 MHz or 19.44 MHz reference, then the output clocks can be brought into phase alignment with the PLL reference by using the RefAlign control bit/pin according to one of the procedures below: 1 ...
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... Using RefAlign with an 8 kHz Reference If the ZL30407 is locked kHz reference, then the output clocks can be brought into phase alignment with the PLL reference by using the RefAlign control bit/pin according to one of the procedures below: 1. For 0.1 Hz filtering applications (FCS = 1, FCS2 = 0) ...
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... C155 : 155.52 MHz clock with nominal 50% duty cycle. The ZL30407 provides the following frame pulses (see Figure 18 "ST-BUS and GCI Output Timing" for details). All frame pulses have the same 125 Ps period (8kHz frequency): - F0o : 244 ns wide, logic low frame pulse ...
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... Requirements for Clock Modes are defined in the international standards e.g.: G.813, GR-1244-CORE and GR-253-CORE and they are enforced by network operators. The ZL30407 supports all clock modes and each of these modes have a corresponding state in the Control State Machine. ...
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... Network Element operates as a master node in an isolated network. In the Free-run state, the accuracy of the generated clocks is determined by the accuracy and stability of the ZL30407 Master Crystal Oscillator. When equipment is installed for the first time (or periodically maintained) the accuracy of the Free-run clocks can be adjusted to within 1x10 Calibration Register ...
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... Auto Holdover State The Auto Holdover state is a transitional state that the ZL30407 enters automatically when the active reference fails unexpectedly. When the ZL30407 detects loss of reference it sets the HOLDOVER status bit and waits in Auto Holdover state until the failed reference recovers. Recovery from Auto Holdover for 8 kHz, 1.544 MHz, 2.048 MHz and 19 ...
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... Care should be taken to ensure that changes to the Master Clock Calibration Register are made in small increments so the frequency steps can be tolerated by downstream equipment. A rate of frequency change below 2.9 ppm/sec is suggested. All memory in the ZL30407 is volatile; so any settings of the Master Clock Calibration Register need to be reloaded after each RESET. ZL30407 ...
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... Microprocessor Interface The ZL30407 can be controlled by a microprocessor ASIC type of device that is connected directly to the hardware control pins. If the HW pin is tied low (see Figure 7 "Hardware and Software Control Options"), an 8-bit Motorola type microprocessor may be used to control PLL operation and check its status. Under software control, the control pins MS2, MS1, FCS, RefSel, RefAlign are disabled and they are replaced by the equivalent control bits ...
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... Software control programmable registers. 4.1.1 Control Pins The ZL30407 has five dedicated control pins for selecting modes of operation and activating different functions. These pins are listed below: MS2 and MS1 pins: Mode Select: The MS2 (pin 19) and MS1 (pin 18) inputs select the PLL mode of operation. ...
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... Software control is enabled by setting the HW pin to logic zero (HW = 0). In this mode all hardware control pins (inputs) are disabled and all status pins remain enabled. The ZL30407 has a number of registers that provide all the functionality available in Hardware control and in addition they offer advanced control and monitoring that is only available in Software control (see Figure 7 " ...
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... Master Clock Frequency Calibration Register - Byte 2 43 Master Clock Frequency Calibration Register - Byte 1 Note: The ZL30407 uses address space from 00h to 6Fh. Registers at address locations not listed above must not be written or read. ZL30407 Read Write R/W RefSel MS2, MS1, FCS, 0, RefAlign ...
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... Reference Alignment. A high-to-low transition aligns the generated RefAlign output clocks to the input reference signal (see Section 3.2.5, Reference Alignment (RefAlign) for details). This bit should never be held low permanently. ZL30407 Functional Description MS2 = 0 MS1 = 0 Normal Mode (Locked Mode) MS2 = 0 MS1 = 1 Holdover Mode ...
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... Lock. This bit goes high when the Core PLL completes the phase locking process to the input reference clock (see Section 3.2.4, Lock Indicator (LOCK) for details). After achieving lock, this bit will go low if the ZL30407 enters Holdover mode, Automatic Holdover mode or Free-run mode the Core PLL phase detector accumulates more than phase error the RefAlign control bit/pin is taken low ...
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... E3/DS3 bit selects a 44.736 MHz clock on the C34/C44 output and logic high selects a 34.368 MHz clock. When the E3DS3/OC3 bit is set low, a logic low on the E3/DS3 bit selects an 11.184 MHz clock on the C34/C44 output and a logic high selects an 8.592 MHz clock. 5-0 RSV Reserved ZL30407 C20 0 -12 -9.2 9.2 12 C20 -7 ...
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... Note that phase offset adjustment is a process of shifting clocks in a time domain which may cause momentary distortion of the generated clocks. Therefore it is not recommended to perform phase offset adjustments on an active ZL30407 (at the time when it generates network clocks). Address Bit ...
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... Note that phase offset adjustment is a process of shifting clocks in a time domain which may cause momentary distortion of the generated clocks. Therefore it is not recommended to perform phase offset adjustments on an active ZL30407 (at the time when it generates network clocks). 2-1 RSV Reserved ...
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... Holdover state to preserve “hit-less” recovery. To guarantee this transitioning, the AHDR bit should be set high permanently to prevent automatic return to Normal mode. 0 RSV Reserved Table 15 - Core PLL Control Register (R/W) ZL30407 Functional Description Table 14 - Clock Disable Register 2 (R/W) Functional Description 30 Zarlink Semiconductor Inc. Data Sheet ...
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... PAFL This status bit is intended to provide software compatibility with the ZL30402 not required for new designs. Table 17 - Primary Acquisition PLL Status Register (R) ZL30407 Functional Description Functional Description 31 Zarlink Semiconductor Inc. Data Sheet Default ...
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... Address Bit Name 7-0 MCFC15 - 8 Master Clock Frequency Calibration. This byte contains the 15th to 8th bit of the Master Clock Frequency Calibration Register. Table 21 - Master Clock Frequency Calibration Register 2 (R/W) ZL30407 Functional Description Functional Description Functional Description Functional Description 32 Zarlink Semiconductor Inc. Data Sheet ...
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... ZL30407 Mode Switching - Examples The ZL30407 is designed to transition from one mode to the other driven by the internal State Machine or by manual control. The following examples present a couple of typical scenarios of how the ZL30407 can be employed in network synchronization equipment (e.g. timing modules, line cards or stand alone synchronizers). ...
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... Free-run mode where the system (card) is being initialized. At the end of this process the ZL30407 should be switched into Normal mode (with MS2, MS1 set to 00) instead of Holdover mode. If the reference clock is available, the ZL30407 will transition briefly into Holdover to acquire synchronization and switch automatically to Normal mode ...
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... The NORMAL to AUTO-HOLDOVER to NORMAL transition will usually happen when the Network Element loses its single reference clock unexpectedly. The sequence starts with the reference clock transitioning from OK --> FAIL at a time when ZL30407 operates in Normal mode (as is shown in Figure 10). This failure is detected by the active Acquisition PLL based on the following FAIL criteria: • ...
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... RESET = 1 OR MS2,MS1 = 01 FREE- RESET RUN 10 MS2,MS1 = 10 forces unconditional return from any state to Free-run Figure 11 - Recovery Procedure From a Single 8 kHz Reference Failure by Transitioning Through ZL30407 RefSel change NORMAL 00 Ref: OK AND Ref: OK-->FAIL AND MS2,MS1 = 00 MS2,MS1 = 00 {AUTO} HOLD- OVER When HOLDOVER 0-->1 ...
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... The failure conditions triggering this transition were described in section 4.1.2. When in the Auto Holdover state, the ZL30407 can return to Normal mode automatically if the lost reference is restored and the ADHR bit is set to 0. This transition from Auto Holdover to Normal mode is performed as “hit-less” recovery for 1.544 MHz, 2.048 MHz and 19.44 MHz references. For the 8 kHz input reference, the recovery from Auto Holdover state must transition through the Holdover state to preserve “ ...
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... Semi-automatic transition, which involves changing RefSel input to select a secondary reference clock without changing the mode select inputs MS2, MS1 = 00 (Normal mode). This forces the ZL30407 to momentarily transition through the Holdover state and automatically return to Normal mode after synchronizing to a secondary reference clock. ...
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... When the Master Timing card fails unexpectedly (this failure is not related to reference failure) then all Line Cards will detect this failure and they will switch to the timing supplied by the Slave Timing Card. At this moment the ZL30407 on the Slave Timing Card must be switched from the same loop filter characteristic (e.g. 1.5 Hz filter for SDH networks) as the Master Timing Card. ...
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... VDD ZL30407 ZL30407 Figure 15 - Power Supply Filtering 40 Zarlink Semiconductor Inc. Data Sheet C1, C2, C3, C4 0.1 µF (ceramic) C6 µF (ceramic Ferrite Bead = BLM21A601R (Murrata) GND ...
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... LVDS: Output short circuit current 13 LVDS: Output rise and fall times * Voltages are with respect to ground (GND) unless otherwise stated. Note 1: VOS is defined Note 2: Rise and fall times are measured at 20% and 80% levels. ZL30407 Symbol V DDR V PIN I PIN ...
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... Voltages are with respect to ground (GND) unless otherwise stated. * Supply voltage and operating temperature are as per Recommended Operating Conditions. * Timing for input and output signals is based on the worst case conditions (over T ALL SIGNALS t IF, Figure 16 - Timing Parameters Measurement Voltage Levels ZL30407 and V A Timing Reference Points Zarlink Semiconductor Inc ...
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... Address Hold 9 Data Read Delay 10 Data Read Hold 11 Data Write Setup 12 Data Write Hold * Supply voltage and operating temperature are as per Recommended Operating Conditions. t DSH DS CS R/W A0-A6 D0-D7 READ D0-D7 WRITE ZL30407 Symbol Min DSL t 100 DSH t 0 CSS t 0 CSH t 20 RWS t 5 ...
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... C2o pulse width low 13 F8o to C2o delay * Supply voltage and operating temperature are as per Recommended Operating Conditions. F16o tc = 125 Ps C16o tc = 61.04 ns F8o tc = 125 Ps C8o tc = 122.07 ns F0o tc = 125Ps C4o tc = 244.14 ns C2o tc = 488.28 ns ZL30407 Symbol Min F16L t 27 F16D t 26 C16L t -3 C16D t 119 F8H ...
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... AC Electrical Characteristics - DS1 and DS2 Clock Timing* Characteristics 1 C6o pulse width low 2 F8o to C6o delay 3 C1.5o pulse width low 4 F8o to C1.5o delay * Supply voltage and operating temperature are as per Recommended Operating Conditions. F8o tc = 125 Ps C6o tc = 158.43 ns C1. 647.67 ns ZL30407 Symbol Min C6L t -4 C6D t 320 C1. C1. ...
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... Supply voltage and operating temperature are as per Recommended Operating Conditions. t C155L C155oP C19DLH C19o tc = 51.44 ns Note: Delay is measured from the rising edge of C155P clock (single ended) at 1.25 V threshold to the rising and falling edges of C19o clock at V ZL30407 Symbol Min. t 2.6 C155L t -1 C19DLH t -2 ...
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... MHz tc = 647.67 ns PRI/SEC 2.048 MHz tc = 488.28 ns PRI/SEC 19.44 MHz tc = 51.44 ns C19o tc = 51.44 ns F8o tc = 125 Ps Note: Delay time measurements are done with jitter free input reference signals. Figure 21 - Input Reference to Output Clock Phase Offset ZL30407 Symbol Min. Max. t 100 R8W R8D t 100 R1.5W ...
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... C11o clock pulse width high 3 C34o clock pulse width high 4 C8.5o clock pulse width high * Supply voltage and operating temperature are as per Recommended Operating Conditions. C44o tc = 22.35 ns C11o tc = 89.41 ns C34o tc = 29.10 ns C8. 116.39 ns ZL30407 Symbol Min. t 100 S t 100 Symbol Min. ...
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... Reference switching: PRI Ÿ SEC, SEC Ÿ PRI 14 Switching from Normal mode to Holdover mode 15 Switching from Holdover mode to Normal mode Output Phase Slope 16 0.1 Hz Filter 17 1.5 Hz Filter ZL30407 Min. Typ. Max. -12 -12 4x10 7x10 -12 -12 24x10 32x10 -12 -12 70x10 160x10 ...
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... Data Sheet Units Notes ns G.813 Option 1 1.326 ms Ps sec ZL30407 Jitter Generation Performance Typ. Units Notes C155 Clock Output 0.325 ns P-P 0.408 ns P-P 0.038 ns RMS 0.448 ns P-P C19 Clock Output 0.390 ns P-P 0.458 ns P-P 0.040 ns RMS 0.512 ns P-P ZL30407 Jitter Generation Performance Typ. Units Notes C1.5 Clock Output 0.63 ns P-P 0.93 ns P-P ...
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... Equivalent Limit in limit in Typ. UI time domain C16, C8, C4 and C2 Clock Outputs 0.05 UIpp 24.4 0.56 51 Zarlink Semiconductor Inc. Data Sheet ZL30407 Jitter Generation Performance Units Notes C6 Clock Output ns P-P ZL30407 Jitter Generation Performance Units Notes C44 Clock Output ns P-P ns P-P ZL30407 Jitter Generation Performance Units Notes ns P-P ...
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... C16, C8, C4 and C2 Clock Outputs 0.05 UIpp 24.4 0.56 0.05 UIpp 32.4 0.93 52 Zarlink Semiconductor Inc. Data Sheet ZL30407 Jitter Generation Performance Units Notes C34 Clock Output ns P-P ZL30407 Jitter Generation Performance Units Notes C155 Clock Output ns P-P ns P-P C155 Clock Output ns P-P ns P-P C19 Clock Output ns P-P ns P-P ...
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... UIpp 0.643 0.390 0.5 UIpp 3.215 0.512 C16, C8, C4 and C2 Clock Outputs 0.05 UIpp 24.4 0.56 0.1 UIpp 0.643 0.408 0.1 UIpp 0.643 0.458 53 Zarlink Semiconductor Inc. Data Sheet ZL30407 Jitter Generation Performance Units Notes C155 Clock Output ns P-P ns P-P C19 Clock Output ns P-P ns P-P ns P-P C155 Clock Output ns P-P C19 Clock Output ...
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... UIpp 3.215 0.448 0.1 UIpp 0.643 0.390 0.5 UIpp 3.215 0.512 0.075 UIpp 0.482 0.390 0.5 UIpp 3.215 0.512 54 Zarlink Semiconductor Inc. Data Sheet ZL30407 Jitter Generation Performance Units Notes C155 Clock Output ns P-P ns P-P C155 Clock Output ns P-P ns P-P C19 Clock Output ns P-P ns P-P C19 Clock Output ...
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... C6o (6.312 MHz) 5 C8o (8.192 MHz) 6 C8.5o (8.592 MHz) 7 C11o (11.184 MHz) 8 C16o (16.384 MHz) 9 C19o (19.44 MHz) 10 C34o (34.368 MHz) 11 C44o (44.736 MHz) 12 C155o (155.52 MHz) 13 F0o (8 kHz) 14 F8o (8 kHz) 15 F16o (8 kHz) ZL30407 Typ. Typ. ( 0.0042 2.71 0.0019 0.95 0.0037 0.92 0.0179 2.84 0.0081 0.99 0.0222 2.58 0.0295 2.64 ...
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