EP910ILI-12

Manufacturer Part NumberEP910ILI-12
ManufacturerAltera Corporation
EP910ILI-12 datasheet
 


Specifications of EP910ILI-12

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Functional
Description
Altera Corporation
For more information, see the
Development System & Software Data
The Classic architecture includes the following elements:
Macrocells
Programmable registers
Output enable/clock select
Feedback select
Macrocells
Classic macrocells, shown in
both sequential and combinatorial logic operation. Eight product terms
form a programmable-AND array that feeds an OR gate for combinatorial
logic implementation. An additional product term is used for
asynchronous clear control of the internal register; another product term
implements either an output enable or a logic-array-generated clock.
Inputs to the programmable-AND array come from both the true and
complement signals of the dedicated inputs, feedbacks from I/O pins that
are configured as inputs, and feedbacks from macrocell outputs. Signals
from dedicated inputs are globally routed and can feed the inputs of all
device macrocells. The feedback multiplexer controls the routing of
feedback signals from macrocells and from I/O pins. For additional
information on feedback select configurations, see
Figure 1. Classic Device Macrocell
Logic Array
To Logic Array
Input, I/O, and
Macrocell
Feedbacks
Asynchronous Clear
Classic EPLD Family Data Sheet
MAX+PLUS II Programmable Logic
Sheet.
Figure
1, can be individually configured for
Figure 3 on page
VCC
Output Enable/Clock Select
Global
Clock
OE
CLK
Q
CLR
Programmable
Register
Feedback
Select
749.
747