MT9075BP Zarlink Semiconductor, MT9075BP Datasheet
MT9075BP
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... Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2002-2005, Zarlink Semiconductor Inc. All Rights Reserved. E1 Single Chip Transceiver MT9075BPR MT9075BL MT9075BP MT9075BPR1 MT9075BP1 MT9075BL1 Applications • E1 add/drop multiplexers and channel banks • CO and PBX equipment interfaces • ...
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... The MT9075B meets or supports the latest ITU-T Recommendations including G.703, G.704, G.706, G.732, G.775, G.796, G.823 for PCM 30, and I.431 for ISDN primary rate. It also meets or supports ETSI ETS 300 011, ETS 300 166 and ETS 300 233 as well as BS 6450. MT9075B 2 Zarlink Semiconductor Inc. Data Sheet ...
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... VDD 49 VSS 48 IC RxFP/Rx64KCK 47 46 F0b 45 C4b 44 E2o Zarlink Semiconductor Inc. Data Sheet TAIS 48 Trst 46 Tclk Tms 44 Tdo Tdi GNDATx 42 TRING TTIP 40 VDDATx VDD 38 VSS IC 36 RxFP/Rx64KCK 34 F0b C4b 32 E2o ...
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... RESET (Input). This active low input puts the MT9075B in a reset condition. RESET should be set to high for normal operation. The MT9075B should be reset after power- up. The RESET pin must be held low for a minimum of 1µsec. to reset the device properly. MT9075B Description 4 Zarlink Semiconductor Inc. Data Sheet ...
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... Transmit Multiframe Boundary (Input). An active low input used to set the transmit multiframe boundary (CAS or CRC multiframe). The MT9075B will generate its own multiframe if this pin is held high. This input is usually pulled high for most applications. MT9075B Description (Ground) for normal operation Zarlink Semiconductor Inc. Data Sheet through a pull- DD ...
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... IEEE 1149.1 Test Mode Selection (Input). If not used, this pin should be pulled high Tclk IEEE 1149.1 Test Clock Signal (Input). If not used, this pin should be pulled high Trst IEEE 1149.1 Reset Signal (Input). If not used, this pin should be held low. MT9075B Description 6 Zarlink Semiconductor Inc. Data Sheet ...
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... The LIU also contains a Jitter Attenuator (JA), which can be configured to either the transmit or receive path. The JA will attenuate jitter from 2.5 Hz and roll-off at a rate of 20 dB/decade. Its intrinsic jitter is less than 0.02 UI. MT9075B Description (Ground) for normal operation. SS (Ground) for normal operation Zarlink Semiconductor Inc. Data Sheet ...
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... The LOS output pin (pin 61 in PLCC, pin 57 in MQFP) is user selectable, by setting control bit LOS/LOF (page 02H, register 13H, bit 2), to indicate a loss of signal or loss of basic frame synchronization condition. In addition, a status MT9075B 8 Zarlink Semiconductor Inc. Data Sheet ...
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... Jitter Amplitude (log scale) 18UI 1.5UI 0.2UI 1.667Hz MT9075B may be optimized for 120 Ω lines, 75 Ω lines or set MT9075B Tolerance 20Hz 2.4kHz 18kHz 100kHz Figure 3 - Typical Jitter Tolerance 9 Zarlink Semiconductor Inc. Data Sheet (as shown in Figure 4) are for T Jitter Frequency (log scale) ...
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... Nominal Peak 120 110 100 -10 -20 MT9075B 0.68uF R 1:2 T TTIP TRING R T MT9075B 1:1 RTIP 120Ω/ 75Ω RRING Figure 4 - Analog Line Interface 269nS 244nS 194nS Nominal Pulse 219nS 488nS Figure 5 - Pulse Template (G.703) 10 Zarlink Semiconductor Inc. Data Sheet Tx Rx ...
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... Approximate Drive Level: MT9075B Manufacturer For Tx Filtran 5721-1 PE-65351 Midcom 50027 OSEC 02934 Vdd 20MHz OSC1 OUT .1µF GND OSC2 ( ) open Figure 6 - Clock Oscillator Circuit 20 MHz 50 ppm Fundamental Parallel Ω Zarlink Semiconductor Inc. Data Sheet For Rx 5721-2 PE-64934 50026 02935/A ...
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... MT9075B has three basic jitter attenuation modes of operation, selected by the BS/LS and BL/FR control pins. • System Bus Synchronous Mode • Line Synchronous Mode • Free-run mode MT9075B MT9075B 20MHz OSC1 56pF 39pF 1MΩ 100Ω OSC2 Note: the 1µH inductor is optional Figure 7 - Crystal Oscillator Circuit 12 Zarlink Semiconductor Inc. Data Sheet 1µH* ...
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... Frequency (Hz) 13 Zarlink Semiconductor Inc. Data Sheet -20 dB/decade 400 10K Note side side side side side By default the receive side. Controls bits need not be selected. In free-run mode JA will be automatically ...
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... G.761). • S may be used as a message-based data link for operations, maintenance and performance monitoring. a4 MT9075B 3... 19... 3... 18... are additional spare bits which may be used as follows Zarlink Semiconductor Inc. Data Sheet ...
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... T G.704. Table 4 outlines the operation of the AUTC, ARAI and TALM control bits of the MT9075B. MT9075B bits is provided by the MT9075B to a bits including S are collectively called national bits CRC-4 error was discovered in a submultiframe Zarlink Semiconductor Inc. Data Sheet 4 4 then divided ...
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... E-bits are the same state as the TE control bit. When CRCSYN = 0, the CRC MFAS search is terminated and the transmit RAI goes low. Automatic CRC-interworking is de-activated. Transmit RAI is low continuously upon loss of synchronization. Automatic CRC-interworking is de-activated. Transmit RAI is high continuously upon loss of synchronization. 16 Zarlink Semiconductor Inc. Data Sheet ...
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... CSTi is used to control the transmit channel associated signalling. The DSTi and DSTo streams contain the transmit and receive voice and digital data. MT9075B Register Description Table 5 - Register Summary 17 Zarlink Semiconductor Inc. Data Sheet Processor ST-BUS Access Access ...
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... Deactivated Interrupts Interrupt Mask Word Zero unmasked, all others masked; interrupts not suspended RxMF Output Signalling Multiframe Error Insertion Deactivated HDLCs Deactivated Counters Cleared All locations set to 54H All locations cleared Buffer Table 6 - Reset Status 18 Zarlink Semiconductor Inc. Data Sheet 1111111 ...
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... 14/FAS 15/NFA Table 7 - FAS and NFAS Structure 19 Zarlink Semiconductor Inc. Data Sheet ...
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... Table 8 - MT9075B National Bit Buffers bits or change of state through S . See the description of page 01H, address 19H for more details bit position is clocked in from the TxDL pad (pin 65 in PLCC, pin Zarlink Semiconductor Inc. Data Sheet ...
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... Each HDLC controller has a 128 byte deep FIFO associated with it. The status and interrupt flags are programmable for FIFO depths that can vary from 16 to 128 bytes in steps of 16 bytes. These and other features are enabled through the HDLC control registers on page 0BH and 0CH. MT9075B a 21 Zarlink Semiconductor Inc. Data Sheet bits and channel 16 respectively. ...
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... Data FCS Field n Bytes Two n ≥ 2 Bytes Table 9 - HDLC Frame Format +1” produces the 16-bit FCS. In the transmitter the FCS is calculated on 22 Zarlink Semiconductor Inc. Data Sheet ” (7EH). The transmitter generates these 2 Closing Flag (7EH) One Byte 01111110 ...
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... TxEN changed from 0 to 1). A missing opening flag will cause the packet to be lost at the receiving end. This problem only affects the first packet transmitted after the HDLC transmitter is enabled. Subsequent packets are unaffected. MT9075B 23 Zarlink Semiconductor Inc. Data Sheet 1 . The ...
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... Address Registers is used as an enable bit for that byte, thus allowing either or both of the first two bytes to be compared to the expected values. In addition, seven bits of address comparison can be realized on the first byte if this is a single byte address by setting the Seven bit of Control Register 2 (address 15H). MT9075B 24 Zarlink Semiconductor Inc. Data Sheet When . ...
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... The remaining trunks will use the system timing derived from the synchronizer to clock data out of their slip buffers. Even though the PCM 30 signals from the network are synchronous to each other, due to multiplexing, transmission impairments and route diversity, these MT9075B 25 Zarlink Semiconductor Inc. Data Sheet ...
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... Once the FAS is detected, the corresponding bit 2 of the non-frame alignment signal (NFAS) is checked. If bit 2 of the NFAS is zero a new search for basic frame alignment is initiated. If bit 2 of the NFAS is one MT9075B Read Pointer -13 CH Read Pointer 26 Zarlink Semiconductor Inc. Data Sheet Wander Tolerance ...
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... When CRC-4 multiframing has been achieved, the primary basic frame alignment and resulting multiframe alignment will be adjusted to the basic frame alignment determined during CRC-4 synchronization. Therefore, the primary basic frame alignment will not be updated during the CRC-4 multiframing search, but will be updated when the CRC-4 multiframing search is complete. MT9075B 27 Zarlink Semiconductor Inc. Data Sheet ...
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... Notes 6 & 7. CRC-to-non-CRC interworking. Maintain primary basic frame alignment. Continue to send CRC-4 data, but stop CRC processing. E-bits set to ‘0’. Indicate CRC-to-non-CRC operation. Note 7. Figure 10 - Synchronization State Diagram 28 Zarlink Semiconductor Inc. Data Sheet NO 3 consecutive incorrect frame alignment signals ...
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... Remote Loopback (RM Loop) - RTIP and RRING to TTIP and TRING respectively at the PCM 30 side. Bit RLBK = 0 normal; RLBK = 1 activate. System c) ST-BUS Loopback (ST Loop) - DSTi to DSTo at the system side. Bit SLBK = 0 normal; SLBK = 1 activate. MT9075B MT9075B DSTi Tx PCM30 DSTo MT9075B Tx PCM30 DSTo Rx 29 Zarlink Semiconductor Inc. Data Sheet ...
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... Counter overflows set bits in the counter overflow latch (page 04H, address 16H); this latch is cleared when read. MT9075B MT9075B DSTi System DSTo MT9075B DSTi System DSTo MT9075B DSTi DSTo MT9075B DSTi System DSTo 30 Zarlink Semiconductor Inc. Data Sheet Tx PCM30 Tx PCM30 Rx Tx PCM30 Rx Tx PCM30 Rx ...
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... There are two maskable interrupts associated with the frame alignment signal error measurement. FERI (page 01H, address 1BH) is initiated when the least significant bit of the errored frame alignment signal counter toggles, and FERO (page 01H, address 1DH) is initiated when the counter changes from FFH to 00H. MT9075B 31 Zarlink Semiconductor Inc. Data Sheet ...
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... Per Time Slot Control Word. If the PRBS testing is performed in a metallic or external looparound the Per Time Slot Control Words with TTST (transmit test, bit 3) set should have RRST (receive test, bit 2) set at the same time. MT9075B 32 Zarlink Semiconductor Inc. Data Sheet ...
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... Table 10 - A-Law Digital Milliwatt Pattern 33 Zarlink Semiconductor Inc. Data Sheet Bit Bit ...
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... EBI CRCI CEFI BPVI Interrupt Mask Word Two (address 1DH) Bit 7 EBO CRCO CALNI FERO MT9075B Bit 0 SabitI Sa6I Sa5I C8Sa6I Bit 0 LOSI FERI BPVO SLPI Bit 0 RCR1 RCR0 BERI SIGI Bit 0 JAI BERO AUXPI CMFO 34 Zarlink Semiconductor Inc. Data Sheet ...
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... BERI - Bit Error. EBO - Receive E-bit Error. CRCO - CRC-4 Error. D0 FERO - Frame Alignment Signal. BPVO - Bipolar Violation. BERO - Bit Error. CMFO - CRC-4 Multiframe. 1SECI - One Second Timer. CALNI - CRC-4 Multiframe Alignment. D0 T1I - Timer T1 expires. T2I - Timer T2 expires. 35 Zarlink Semiconductor Inc. Data Sheet ...
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... SanibI - Changed S 00000010 SabitI - Changed S C8SA6I- Sequence SA6I - Changed S SA5I - Changed S HDLC0 - Status Signal- SIGI-Receive Signalling Bit Change. ling/HDLC1 HDLC1 - Status 00000001 Table 11 - MT9075B Interrupt Vectors (IV7 - IV0) 36 Zarlink Semiconductor Inc. Nibble a5,6 Bits a5,6 nibbles. a6 nibbles. a6 bits. a5 Data Sheet ...
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... EBI, CRCI, CEFI, BPVI, RCR0I, RCR1I, BERI & SIGI EBOI, CRCOI, CALNI, FEROI, JAI, BEROI, AUXPI & CMFOI MFSYI, CSYNI, YI, 1SECI, T1I, T2I CTXP, LL0, LL1, LL2 Table 12 - Master Control 1 (Page 01H) 37 Zarlink Semiconductor Inc. Data Sheet Names - nibI,S bitI,C8S ...
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... If one, the Y-bit is under the manual control of the Transmit Multiframe Alignment Control Word. Table 14 - Mode Selection Control Word MT9075B Functional Description bits of the NFA signal for automatically selected - see TxTRSP a4 Functional Description (Page 01H, Address 11H) 38 Zarlink Semiconductor Inc. Data Sheet ...
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... PCM 30 2048 kbit/sec. link in bit positions four to eight of time slot zero of the NFA (11111) frame, if selected by S address 10H). MT9075B (Page 01H, Address 11H) Functional Description - S ). These bits are transmitted on the control bits of the DL selection word (page 01H Table 15 - NFA Control Word (page 01H, Address 12H) 39 Zarlink Semiconductor Inc. Data Sheet ...
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... Data coming from the receive (0) line passes through the slip buffer and drives DSTo with an arbitrary alignment. When zero, the receive framing function operates normally. 4-0 --- Unused. Table 17 - HDLC Selection Word (Page 01H, Address 14H) Zarlink Semiconductor Inc. MT9075B Functional Description Functional Description 40 Data Sheet ...
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... Payload Loopback. If one, then all time slots received on RTIP/RRING are connected to TTIP/TRING on the ST-BUS side of the MT9075B (this (0) excludes time slot zero). If zero, then this feature is disabled. Table 18 - Coding and Loopback Control Word (Page 01H, Address 15H) MT9075B Functional Description 41 Zarlink Semiconductor Inc. Data Sheet ...
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... CRC4 sync (CRCSYN=1) or AIS. 0 CSToDE CSTo Data Enable. If zero, CSTo is enabled. If one, CSTo will be tristated if one of the following conditions exists: loss of multiframe sync (MFSYNC=1), or AIS16 =1 (0) Table 19 - Transmit Alarm Control Word MT9075B Functional Description (Page 01H, Address 16H) 42 Zarlink Semiconductor Inc. Data Sheet ...
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... Interrupt vector = 00000010 Nibble Interrupt. When unmasked (C8S a6 Nibble Interrupt. When unmasked (S a6 Bit Interrupt. When unmasked (S a5 (Page 01H, Address 19H) 43 Zarlink Semiconductor Inc. Data Sheet nibI = 1), an interrupt is a nibbles a ). Interrupt vector = 00000010. a8 bitI = 1), an interrupt is a bits (S ...
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... Rx64KCK (pin 47 in PLCC MQFP) when this bit is set. If zero CSTi and CSTo have 2.048 mb/s bit rates and operate as per Tables 66 to 71. Table 21 - Interrupt, Signalling and BERT Control Word (Page 01H, Address 1AH MT9075B Functional Description 44 Zarlink Semiconductor Inc. Data Sheet ...
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... FFFFH to 0H. Interrupt vector = 00010000. 0 SLPI SLIP Interrupt. When unmasked (SLPI = 0), an interrupt is initiated when a controlled frame slip occurs. Interrupt vector = 00000100. (0) Table 22 - Interrupt Mask Word Zero MT9075B Functional Description (Page 01H, Address 1BH) 45 Zarlink Semiconductor Inc. Data Sheet ...
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... SIGI Signalling (CAS) Interrupt. When unmasked and any of the receive ABCD bits of any channel changes state an interrupt is initiated unmasked (0) masked. Interrupt vector = 00000001 Table 23 - Interrupt Mask Word One MT9075B Functional Description (Page 01H, Address 1CH) 46 Zarlink Semiconductor Inc. Data Sheet ...
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... Interrupt vector = 01000000. 0 CMFOI Receive CRC-4 Multiframe Counter Overflow Interrupt. When unmasked (CMFO = 1), an interrupt is initiated when the CRC-4 multiframe counter (0) overflows. Interrupt vector = 00010000. Table 24 - Interrupt Mask Word Two MT9075B Functional Description (Page 01H, Address 1DH) 47 Zarlink Semiconductor Inc. Data Sheet ...
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... T2 Timer Interrupt. When unmasked (T2I = 1), an interrupt is initiated when the T2 timer bit (page 03H, address 12H, bit 4) changes from zero to one. (0) Interrupt vector = 00001000 Unused Table 25 - Interrupt Mask Work Three MT9075B Functional Description (Page 01H, Address 1EH) 48 Zarlink Semiconductor Inc. Data Sheet ...
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... Table 26 - Transmit Pulse Control Word MT9075B Functional Description ), and transformer turns ratio used T (Ω) Xfmr T 0 120 0 1:2 1 120 0 1:1 0 120 15 1:2 1 120/75 12 9.1 1:2 1 75/120 12.1 1:2 (Page 01H, Address 1FH) 49 Zarlink Semiconductor Inc. Data Sheet ...
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... JAS, JAT/JAR, JFC, JFD2, JFD1, JFD0, JACL REDBL, REMID, REMAX Set all bits to zero for normal operation. Set all bits to zero for normal operation. CPLA6 - CPLA0 CPLB6 - CPLB0 CPLC6 - CPLC0 CPLD6 - CPLD0 Table 27 - Master Control 2 (Page 02H) 50 Zarlink Semiconductor Inc. Data Sheet Names ...
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... Note: there may be as much as 2 msec. added to this (0) duration because the state change of the signalling equipment is not synchronous with the PCM 30 signalling multiframe. Table 28 - Error and Debounce Selection Word MT9075B Functional Description (Page 02H, Address 10H) 51 Zarlink Semiconductor Inc. Data Sheet ...
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... GCI or ST-BUS Frame Pulse. If one, the MT9075B will transmit or receive a GCI frame pulse on pin F0b (pin 46 in PLCC MQFP). If zero, the (0) MT9075B will transmit or receive an ST-BUS frame pulse on F0b. MT9075B Functional Description Table 29 - Access Control Word (Page 02H, Address 13H) 52 Zarlink Semiconductor Inc. Data Sheet 15 -1 bit error ...
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... However, the actual bit values of the data in the JA FIFO will not be reset. 0 --- Unused. Table 30 - Jitter Attenuator Control Word MT9075B Functional Description JFD2 JFD1 (Page 02H, Address 18H) 53 Zarlink Semiconductor Inc. Data Sheet JFD0 Depth (words 112 1 128 ...
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... Pulse shape coefficient for the second time slot (within one bit cell). CPLB5 is the MSB (000000) MT9075B Functional Description the two-stage equalization (Page 02H, Address 19H) Functional Description Table 32 - Custom Pulse Level 1 (Page 2, Address 1CH) Functional Description Table 33 - Custom Pulse Level 2 (Page 2, Address 1DH) 54 Zarlink Semiconductor Inc. Data Sheet is enabled, which provides ...
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... CPLD5-CPLD0 Pulse shape coefficient for the fourth time slot (within one bit cell) (000000) Table 35 - Custom Pulse Level 4 MT9075B Functional Description (Page 2, Address 1CH) Functional Description (Page 2, Address 1FH) 55 Zarlink Semiconductor Inc. Data Sheet ...
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... RSLIP, RSLPD, AUXP, CEFS, RxEBC11-8 RxEBC7-0 JACS, JACF, JAE, JAF4, JAFC, JAE4, JAF LL, ML, SL, LLOS CRCS1, CRCS2, RFAIL, LOSS, AIS16S, AISS, RAIS & RCRS nibble,C8S a5 a6 Unused. Set to 10101010 Table 36 - Master Status 1 (Page 03H) 56 Zarlink Semiconductor Inc. Data Sheet , ...
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... PCM 30 2048 kbit/sec. link in bit positions two to eight of frame alignment signal. These bits form the frame alignment signal and should be 0011011. Table 38 - Receive Frame Alignment Signal MT9075B Functional Description (Page 03H, Address 10H) Functional Description (Page 03H, Address 11H) 57 Zarlink Semiconductor Inc. Data Sheet ...
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... PCM 30 2048 kbit/sec. link in bit positions four to eight (the S non-frame alignment signal. Table 40 - Receive Non-Frame Alignment Signal MT9075B Functional Description Table 39 - Timer Status Word (Page 03H, Address 12H) Functional Description (Page 03H, Address 13H) 58 Zarlink Semiconductor Inc. Data Sheet bits) of the a ...
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... ST- 11-8 BUS frame pulse and receive frame pulse (RxFP). Table 42 - Most Significant Phase Status Word MT9075B Functional Description (Page 03H, Address 14H) Functional Description (Page 03H, Address 15H) 59 Zarlink Semiconductor Inc. Data Sheet -3 . ...
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... ST- BUS frame pulse and receive frame pulse (RxFP).The accuracy of the this measurement is approximately + 1/16 (one sixteenth bit. (Page 03H, Address 16H) Functional Description (Page 03H, Address 17H) 60 Zarlink Semiconductor Inc. Data Sheet ...
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... RAI and Continuous CRC Error Status. If one, there is currently an RAI and continuous CRC error condition. If zero, normal operation. Updated on a multiframe basis. MT9075B Functional Description (Page 03H, Address 18H) Functional Description Table 46 - Alarm Status Word One (Page 03H, Address 19H) 61 Zarlink Semiconductor Inc. Data Sheet ...
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... Register PS7-0 PSM7-0 IV7 - IV0 EC9-EC8 EC7-EC0 JFC7-JFC0 PRBSO, FEBEO, JFO, LBO, BERO, EFO, BPVO, CCO LBF7-LBF0 BR7 - BR0 RCRC1 - RCRC0 EFAS7 - EFAS0 RAI, AIS, AIS16, LOS, AUXP, MFALM, RSLIP Table 49 - Master Status (Page 04H) 62 Zarlink Semiconductor Inc. Data Sheet Names ...
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... CRC submultiframe cleared when the PRBS Error Counter is written to. (Page 04H, Address 11H) Functional Description (Page 04H, Address 12H) Functional Description Unused E Bit Error Counter. The most significant 2 bits of the E bit error counter. Table bit Error Counter (Page 04H, Address 13H) 63 Zarlink Semiconductor Inc. Data Sheet ...
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... Counter (page 04H, address 1EH & 1FH) overflows cleared when this register is read. Table 56 - Overflow Reporting Latch MT9075B Functional Description Table bit Error Counter (Page 04H, Address 14H) Functional Description Table 55 - Jitter FIFO Counter (Page 04H, Address 15H) Functional Description (Page 04H, Address 16H) 64 Zarlink Semiconductor Inc. Data Sheet ...
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... EFAS0 Table 60 - Errored Frame Alignment Signal Counter (Page 04H, Address 1AH) MT9075B Functional Description (Page 04H, Address 17H) Functional Description (Page 04H, Address 18H) Functional Description (Page 04H, Address 19H) Functional Description 65 Zarlink Semiconductor Inc. Data Sheet ...
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... BPV Counter. The least significant eight bits bit counter that is incremented once for every bipolar violation error received. - BPV0 Table 63 - Least Significant Bits of the PBV Counter (Page 04H, Address 1DH) MT9075B Functional Description (Page 04H, Address 1BH) Functional Description Functional Description 66 Zarlink Semiconductor Inc. Data Sheet ...
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... Transmit Signalling Bits for Channel n + 15. These bits are transmitted on the PCM 30 2048 kbit/sec. link in bit positions five to eight of time slot 16 in frame n (where 15), and are the signalling bits associated with channel n + 15. (Page 05H) 67 Zarlink Semiconductor Inc. Data Sheet ...
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... Receive Signalling Bits for Channel n. These bits are received on the PCM 30 2048 kbit/sec. link in bit positions one to four of time slot 16 in frame n (where 15), and are the signalling bits associated with channel n. Unused - High impedance state. 68 Zarlink Semiconductor Inc. Data Sheet ...
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... Remote Time Slot Loopback. If one, the corresponding PCM 30 receive time slot is looped to the corresponding PCM 30 transmit time slot. This received time slot will also be present on DSTo. If zero, the loopback is disabled. Table 73 - Per Time Slot Control Word (Page 07H and 08H) 69 Zarlink Semiconductor Inc. Data Sheet ...
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... Unused. Unused. Table 73 - Per Time Slot Control Word (Page 07H and 08H) Register LEC9-LEC8 LEC7-LEC0 LEFAS7-LEFAS0 LBPV15-LBPV8 LBPV7-LBPV0 LCC9-LCC8 LCC7-LCC0 Unused. Table 74 - One Second Status (Page 09H) 70 Zarlink Semiconductor Inc. Data Sheet Names ...
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... LBPV0 internal one second timer. Table 79 - Least Significant Bits of the Latched BPV Counter (Page 09H, Address 14H) MT9075B Functional Description (Page 09H, Address 10H) Functional Description (Page 09H, Address 11H) Functional Description Functional Description Functional Description 71 Zarlink Semiconductor Inc. Data Sheet ...
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... CRC-4 error counter. These bits are sampled every second - by the internal one second timer. LCC0 Table 81 - Latched CRC-4 Error Counter MT9075B Functional Description (Page 09H, Address 15H) Functional Description (Page 09H, Address 16H) 72 Zarlink Semiconductor Inc. Data Sheet ...
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... Ga, FA:Txunder, RxFf, RxOvfl Rx CRC MSB Rx CRC LSB --- Cnt7-Cnt0 --- Hloop Test Status --- --- RFFS2-0, TFLS2-0 73 Zarlink Semiconductor Inc. Data Sheet Name Adrec, RxEN, TxEN, EOP, FA, Mark-idle, Intgen, Idle-Chan, RQ9, RQ8, Txstat2, EOPD, TEOP, EOPR, EOPD, TEOP, EOPR, Crc15-Crc8 Crc7-Crc0 HRST, RTloop, RSV, RSV, RSV, Ftst, RSV, ...
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... FIFO. The FIFO status is not changed immediately after a write or read Bit0 occurs updated after the data and the read/write pointers have settled. Table FIFO Write Register MT9075B Functional Description Functional Description Functional Description (Pages 0BH & 0CH, Address 12H) 74 Zarlink Semiconductor Inc. Data Sheet ...
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... These two states will only occur when the TX FIFO (0) is empty. 1-0 RSV Reserved: Must be set to 0 for normal operation. (00) Table 87 - HDLC Control Register 1 (Page 0BH &0CH, Address 13H) MT9075B Functional Description Functional Description 75 Zarlink Semiconductor Inc. Data Sheet ...
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... The number of bytes in the TX FIFO has 0 1 reached or exceeded the selected interrupt threshold level. See Table 94 FIFO empty The number of bytes in the TX FIFO is less than the selected interrupt threshold level. See Table 94. 76 Zarlink Semiconductor Inc. Data Sheet Byte Status TX FIFO Status ...
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... See Table 94 FIFO full up to the selected status level or more. See Table 93. The number of bytes in the RX FIFO has 1 1 reached or exceeded the selected interrupt threshold level. See Table 94. 77 Zarlink Semiconductor Inc. Data Sheet RX FIFO Status ...
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... RxOvfl Interrupt Register. An interrupt is disabled when the microprocessor writes bit in this register. This register is cleared on power reset. (000000) Table 90 - HDLC Interrupt Mask Register (Pages 0BH & 0CH, Address 16H) MT9075B Functional Description Functional Description 78 Zarlink Semiconductor Inc. Data Sheet ...
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... This register is updated at the end of each received packet and therefore should be read when end of packet is detected. Table 92 - Receive CRC MSB Register (Pages 0BH & 0CH, Address 18H) MT9075B Functional Description Functional Description 79 Zarlink Semiconductor Inc. Data Sheet ...
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... The counter decrements at the end of the write to the Tx FIFO. If the Cycle bit of Control Register 2 is set high, the counter will cycle through the programmed value continuously. Table 94 - Transmit Byte Count Register MT9075B Functional Description Functional Description (Pages B & C, Address 1AH) 80 Zarlink Semiconductor Inc. Data Sheet ...
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... RX write causes EOP/ fifo input; TX read looks at output of TX FIFO through RQ8/RQ9 bits). 1 RSV Reserved; must be set to 0 for normal operation. (0) 0 --- Unused. Table 95 - HDLC Test Control Register (Pages 0BH & 0CH, Address 1BH) MT9075B Functional Description 81 Zarlink Semiconductor Inc. Data Sheet ...
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... This is the address recognition status bit for the receiver. Data is clocked into the Address Recognition Register and then this bit is monitored to see if comparison was successful (bit will be one). Table 96 - HDLC Test Status Register (Page 0BH & 0CH, Address 1CH) MT9075B Functional Description 82 Zarlink Semiconductor Inc. Data Sheet ...
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... TFD2 TFD1 TFD0 Zarlink Semiconductor Inc. Data Sheet Full Status Level 112 128 Full Status Level 112 128 ...
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... TFLS1 TFLS0 Table 98 - HDLC Control Register 4 (Pages 0BH & 0CH, Address 1EH) 84 Zarlink Semiconductor Inc. Data Sheet RX FIFO Full Interrupt threshold Level 104 0 112 1 120 TX FIFO Low Interrupt threshold Level ...
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... Bits Frames 1 to 15. This byte contains the bits received in bit an Zarlink Semiconductor Inc. Data Sheet ...
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... MT9075B Functional Description Functional Description Functional Description 86 Zarlink Semiconductor Inc. Data Sheet ...
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... Zarlink Semiconductor Inc. Data Sheet Min. Max. Units - -55 125 °C ) unless otherwise stated. Units Test Conditions °C V Units Test Conditions mA Outputs unloaded. ...
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... RWH t 15 ADH t 80 DDR t 80 DHR t 80 DAZ t 10 DSW t 10 DHW t 120 CYC 88 Zarlink Semiconductor Inc. Data Sheet Conditions/Notes See Note 1 See Note 1 TTL CMOS TTL CMOS Test Conditions =50pF, R =1kΩ ...
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... RDH t 0 CSS t 0 CSH t 10 ADS t 15 ADH t DDR t DAZ t 10 DSW t 10 DHW t 110 CYC 89 Zarlink Semiconductor Inc. Data Sheet t CSH t RWH t ADH t DAZ DHR DHW DSW Max. Units Test Conditions =50pF, R =1kΩ. ...
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... RDL t RDH t CSS t ADS t DDR VALID DATA VALID DATA Figure 12 - Intel Microprocessor Timing Sym. Min. Typ. t TDC t 10 DLS t 10 DLH 90 Zarlink Semiconductor Inc. Data Sheet t CSH t CSH t ADH t ADH t DAZ t t DSW DHW Max. Units Test Conditions 35 ns 50pF ns ns ...
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... F0b TIME SLOT 0 Bits 4,3,2,1,0 TxDLCLK TxDL TxDLCLK TxDL Figure 13 - Transmit Data Link Functional Timing C4b TxDLCLK TxDL Figure 14 - Transmit Data Link Timing Diagram MT9075B Example kb/s Example kb/s t TDC t t DLH DLS 91 Zarlink Semiconductor Inc. Data Sheet TT ...
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... Figure 15 - Receive Data Link Functional Timing E2o t RDC RxDLCLK t RDD RxDL Figure 16 - Receive Data Link Timing Diagram MT9075B Sym. Min. Typ. Max. Units t 150 RDC t 45 RDD Example kb/s Example kb/s t RDC 92 Zarlink Semiconductor Inc. Data Sheet Test Conditions ns 50pF ns 50pF TT TT, CT ...
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... Figure 17 - Transmit 64 k Common Channel Functional Timing C4b Internal Clock CSTi Figure 18 - Transmit 64 k Common Channel Timing Diagram MT9075B Sym. Min. Typ. Max TCS t 15 TCH t t TCH TCS 93 Zarlink Semiconductor Inc. Data Sheet Units Test Conditions ...
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... Rx64KCK CSTo Figure 19 - Receive 64 k Common Channel Functional Timing Rx64KCK CSTo Figure 20 - Receive 64 k Common Channel Timing Diagram MT9075B Sym. Min. Typ. Max RCD Receive Frame Boundary t RCD 94 Zarlink Semiconductor Inc. Data Sheet Units Test Conditions TT, CT ...
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... Channel 0 Channel 0 Bit 7 Bit 6 Bit Cell Bit Cell t FPH t FPS t 4WI t SIH t SIS t SOD Figure 22 - ST-BUS Timing Diagram 95 Zarlink Semiconductor Inc. Data Sheet Units Test Conditions ns C4b as input ns C4b as output ns F0b as input ns F0b as input ns F0b as output 50pF Channel 0 Bit 5 ...
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... Bit Cells Bit 0 F0b C4b Figure 24 - GCI Functional Timing Diagram MT9075B Bit Cell Bit Cell t t 4WO FPD t t 4WO SIH t t SIS SOD Channel 0 Channel 0 Bit 7 Bit 6 96 Zarlink Semiconductor Inc. Data Sheet TT, CT Channel 0 Bit 5 ...
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... Figure 26 - GCI Timing Diagram (Output Clocks) MT9075B Bit Cell Bit Cell t FPH t t FPS 4WI t 4WI t SIH t SIS t SOD Bit Cell Bit Cell t FPD t 4WO t 4WO t SIH t t SIS SOD 97 Zarlink Semiconductor Inc. Data Sheet TT TT, CT ...
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... Sym. Min. Typ. t MOD Bit 4 Bit 0 Bit 7 Bit 6 Frame N Bit 4 Bit 0 Bit 7 Bit 6 98 Zarlink Semiconductor Inc. Data Sheet Max. Units Test Conditions 256 C2 periods - 100nsec Frame 0 Bit 5 Bit 4 Bit 0 Bit 7 Frame 0 Bit 5 Bit 4 Bit 0 ...
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... Figure 30 - PCM 30 Format 125µs CHANNEL • • • 30 BIT BIT BIT BIT (8/2.048)µs Figure 31 - ST-BUS Stream Format 99 Zarlink Semiconductor Inc. Data Sheet t MH2 FRAME FRAME TIME SLOT TIME SLOT 30 31 Least BIT BIT Significant 7 ...
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