ISPLSI5256VE-100LF256 Lattice Semiconductor Corp., ISPLSI5256VE-100LF256 Datasheet
ISPLSI5256VE-100LF256
Specifications of ISPLSI5256VE-100LF256
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ISPLSI5256VE-100LF256 Summary of contents
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... Global OE Pins and One Product Term OE per Macrocell Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. ...
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Functional Block Diagram Figure 1. ispLSI 5256VE Functional Block Diagram (144-I/O Option) VCCIO 1 TOE I/O 1 I/O 2 I/O 3 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 32 I/O ...
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Description (Continued) The 32 registered macrocells in the GLB are driven by the 32 outputs from the PTSA or the PTSA bypass. Each macrocell contains a programmable XOR gate, a pro- grammable register/latch and the necessary clocks and ...
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Figure 2. ispLSI 5256VE Block Diagram (144 I/O Version CLK2 I 160 3 160 160 CLK3 I 160 3 160 ...
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Figure 3. ispLSI 5000VE Generic Logic Block (GLB) From GRP ...
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Figure 4. ispLSI 5000VE Macrocell PTOE GOE0 GOE1 TOE PT Clock PT Reset Shared PT Reset PT Preset speed/ power Note: Not all macrocells have I/O pads. Specifications ispLSI 5256VE Global PTOE 0 Global PTOE 1 Global PTOE 2 Global ...
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Global Clock Distribution The ispLSI 5000VE Family has four dedicated clock input pins: CLK0 - CLK3. CLK0 input is used as the dedicated master clock that has the lowest internal clock skew with no clock inversion to maintain the fastest ...
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Figure 6. Boundary Scan Register Circuit for I/O Pins SCANIN BSCAN (from previous Registers cell Shift DR Clock DR Figure 7. Boundary Scan Register Circuit for Input-Only Pins Input Pin SCANIN ...
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Figure 8. Boundary Scan Waveforms and Timing Specifications TMS TDI T btch TCK TDO Data to be captured Data to be driven out SYMBOL PARAMETER t btcp TCK [BSCAN test] clock pulse width t btch TCK [BSCAN test] pulse width ...
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Absolute Maximum Ratings Supply Voltage V .................................. -0.5 to +5.4V cc Input Voltage Applied ............................... -0.5 to +5.6V Tri-Stated Output Voltage Applied ........... -0.5 to +5.6V Storage Temperature ................................ -65 to 150°C Case Temp. with Power Applied .............. -55 to ...
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Switching Test Conditions Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Ouput Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. Output Load Conditions (See Figure 9) 3.3V TEST CONDITION R1 ...
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DC Electrical Characteristics for 2.5V Range SYMBOL PARAMETER V I/O Reference Voltage CCIO V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH 1. I/O voltage configuration must be set ...
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External Switching Characteristics ...
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External Switching Characteristics ...
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Internal Timing Parameters PARAMETER DESCRIPTION In/Out Delays t in Input Buffer Delay t gclk_in Global Clock Buffer Input Delay (clk0) t rst Global Reset Pin Delay t goe Global OE Pin Delay t buf Output Buffer Delay t en Output ...
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Timing Parameters (continued) BASE PARAMETER ADDER TYPE Routing Adders route Tioi Input Adders t clk1 gclk_in t clk2 gclk_in t clk3 gclk_in 1 Tioo Output Adders t t Slow Slew I/O buf ...
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Timing Model From Feedback t ROUTE t BLA INREG t GCLK_IN CLK t IOI t RST RST t OE GOE In/Out Delays Note: Italicized parameters are delay adders above and beyond default ...
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Power Consumption Power consumption in the ispLSI 5256VE device de- pends on two primary factors: the speed at which the device is operating and the number of product terms used. The product terms have a fuse-selectable speed/ power tradeoff setting. ...
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Signal Descriptions Signal Name TMS Input - This pin is the Test Mode Select input, which is used to control the JTAG state machine. TCK Input - This pin is the Test Clock input pin used to clock through the ...
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Pin Configuration ispLSI 5256VE 100-Pin TQFP (0.5mm Lead Pitch / 14.0mm x 14.0mm Body Size GND 6 I VCC 8 I ...
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Pin Configuration ispLSI 5256VE 128-Pin TQFP (0.4mm Lead Pitch / 14.0mm x 14.0mm Body Size GND 7 I VCC 9 ...
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Signal Configuration ispLSI 5256VE 256-Ball fpBGA (1.0mm Ball Pitch / 17.0mm x 17.0mm Body Size I/O I/O I/O I/O I/O A 113 116 121 125 126 I/O I/O I/O I/O I/O 119/ B 108 115 ...
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Signal Configuration ispLSI 5256VE 272-Ball BGA (1.27mm Ball Pitch / 27.0mm x 27.0mm Body Size I/O I/O I/O I/O 119 114 115 126 CLK2 I/O I/O I ...
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Part Number Description ispLSI 5256VE Device Family Device Number Speed f 165 = 165 MHz max f 125 = 125 MHz max f 100 = 100 MHz max MHz max Ordering Information FAMILY fmax (MHz) tpd ...