LPC47B272 Standard Microsystems, LPC47B272 Datasheet
LPC47B272
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LPC47B272 Summary of contents
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Pin Enhanced Super I/O Controller with LPC • 3.3 Volt Operation, 5 Volt Tolerant • LPC Interface • Fan Control - Fan Speed Control Outputs (2) - Fan Tachometer Inputs (2) • Programmable Wake-up Event Interface • PC98, PC99, ...
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... LPC47B272QFP for 100 pin QFP package LPC47B272-MS for 100 pin QFP package (green, lead-free) 80 Arkay Drive Hauppauge, NY 11788 (631) 435-6000 FAX (631) 273-3123 Copyright © 2005 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given ...
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FEATURES..................................................................................................................................................................1 GENERAL DESCRIPTION .......................................................................................................................................6 PIN CONFIGURATION.............................................................................................................................................7 DESCRIPTION OF PIN FUNCTIONS..................................................................................................................... .................................................................................................................................12 UFFER YPE ESCRIPTIONS INS HAT EQUIRE XTERNAL BLOCK DIAGRAM...................................................................................................................................................13 REFERENCE DOCUMENTS..................................................................................................................................13 3 VOLT OPERATION / 5 VOLT TOLERANCE ...................................................................................................13 POWER FUNCTIONALITY ...
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PARALLEL PORT....................................................................................................................................................74 IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES ..................................................................75 EXTENDED CAPABILITIES PARALLEL PORT.................................................................................................79 PARALLEL PORT FLOPPY DISK CONTROLLER...........................................................................................90 FDC SWAP BIT..........................................................................................................................................................90 FLOPPY ON PARALLEL PORT PIN....................................................................................................................92 POWER MANAGEMENT .......................................................................................................................................93 SERIAL IRQ ..............................................................................................................................................................96 TIMING DIAGRAMS FOR SER_IRQ CYCLE ....................................................................................................96 8042 ...
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FIGURE 31 – JOYSTICK POSITION SIGNAL ................................................................................................189 PACKAGE OUTLINE............................................................................................................................................193 APPENDIX - TEST MODE....................................................................................................................................194 ...............................................................................................................................................194 OARD EST ODE SMSC LPC47B27x - 5 - DATASHEET Rev. 08-10-04 ...
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The LPC47B27x 3.3V PC98/PC99 compliant Super I/O controller. interface, a pin reduced ISA bus interface which provides the same or better performance as the ISA/X-bus with a substantial savings in pins used. The LPC47B27x provides fan control through ...
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GP40/DRVDEN0 1 GP41/DRVDEN1 2 nMTR0 3 nDSKCHG 4 nDS0 5 CLKI32 6 VSS 7 nDIR 8 nSTEP 9 nWDATA 10 nWGATE 11 nHDSEL 12 nINDEX 13 nTRK0 14 nWRTPRT 15 nRDATA 16 GP42/nIO_PME 17 VTR 18 CLOCKI 19 LAD0 20 ...
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PIN No./ QFP NAME 23:20 Multiplexed Command, Address, Data [3:0] 24 Frame 25 Encoded DMA Request 26 PCI Reset 27 Power Down 29 PCI Clock 30 Serial IRQ 6 32.768kHz Trickle Clock Input 19 14.318MHz Clock Input 51 General Purpose ...
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PIN No./ QFP NAME 14 Track 0 13 Index Pulse Input 1 General Purpose I/O/Drive Density Select 0 2 General Purpose I/O/Drive Density Select 1 84 Receive Serial Data 1 85 Transmit Serial Data 1 87 Request to Send 1 ...
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PIN No./ QFP NAME 70 Port Data 2/FDC Write Protected 71 Port Data 3/FDC Read Disk Data 72 Port Data 4/FDC Disk Change 73 Port Data 5 74 Port Data 6/ FDC Motor Port Data 7 77 ...
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PIN No./ QFP NAME 41 General Purpose I/O / P17 42 General Purpose I/O / P16 /nDS1 43 General Purpose I/O / P12/nMTR1 45 General Purpose I/O / System Option 46 General Purpose I/O /MIDI_IN 47 General Purpose I/O /MIDI_OUT ...
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Note 12: The TXD1 pin defaults to tristate following a VTR POR since the activate bit is ‘0’, which means Serial Port the inactive state. Buffer Type Descriptions Note: The buffer type values are specified at VCC=3.3V ...
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SMI PME WDT SER_IRQ SERIAL IRQ PCI_CLK ADDRESS BUS ACPI BLOCK LPC Bus LPC BUS Signals INTERFACE PROPRIETARY CLOCK GEN nINDEX nTRK0 nDSKCHG V Vcc Vss TR nWRPRT CLK32 CLOCKI nWGATE 32KHz 14MHz FIGURE 1 – LPC47B27x BLOCK ...
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POWER FUNCTIONALITY The LPC47B27x has three power planes: VCC, VTR and VREF. VCC Power The LPC47B27x is a 3.3 Volt part. The VCC supply is 3.3 Volts (nominal). See the Operational Description Section and the Maximum Current Values sub-section. VTR ...
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Indication of 32kHz Clock There is a bit to indicate whether or not the 32kHz clock input is connected to the LPC47B27x. This bit is located at bit 0 of the CLOCKI32 register at 0xF0 in Logical Device A. This ...
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The other GPIOs function as follows: GP36, GP37 and GP40: • Buffers are powered by VCC, but in the absence of VCC they are backdrive protected. These pins do not have input buffers into the wakeup logic that are powered ...
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The maximum VCC current given with all outputs open (not loaded) and all inputs in a fixed state (i.e 3.3V). The maximum VREF current given with all outputs open (not loaded) ...
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SUPER I/O REGISTERS The address map, shown below in Table 1, shows the addresses of the different blocks of the Super I/O immediately after power up. The base addresses of the FDC, serial and parallel ports, PME register block, Game ...
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LPC Cycles The following cycle types are supported by the LPC protocol. Cycle Type I/O Write I/O Read DMA Write DMA Read LPC47B27x ignores cycles that it does not support. Field Definitions The data transfers are based on specific fields ...
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POWER MANAGEMENT CLOCKRUN Protocol The CLKRUN# pin is not implemented in the LPC47B27x. See the Low Pin Count (LPC) Interface Specification Reference, Section 8.1. LPCPD Protocol See the Low Pin Count (LPC) Interface Specification Reference, Section 8.2. SYNC Protocol See ...
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I/O and DMA START Fields I/O and DMA cycles use a START field of 0000. Reset Policy The following rules govern the reset policy: 1) When nPCI_RESET goes inactive (high), the clock is assumed to have been running for 100usec ...
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The Floppy Disk Controller (FDC) provides the interface between a host microprocessor and the floppy disk drives. The FDC integrates the functions of the Formatter/Controller, Digital Data Separator, Write Precompensation and Data Rate Selection logic for an IBM XT/AT compatible ...
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BIT 4 nTRACK 0 Active low status of the TRK0 disk interface input. BIT 5 STEP Active high status of the STEP output disk interface output pin. BIT 6 nDRV2 This function is not supported. This bit is always read ...
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BIT 1 MOTOR ENABLE 1 Active high status of the MTR1 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset. BIT 2 WRITE GATE Active high status of the WGATE disk ...
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DIGITAL OUTPUT REGISTER (DOR) Address 3F2 READ/WRITE The DOR controls the drive select and motor enables of the disk interface outputs. It also contains the enable for the DMA logic and a software reset bit. The contents of the DOR ...
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Table 5 - Internal 2 Drive Decode - Drives 0 and 1 Swapped DIGITAL OUTPUT REGISTER Bit 5 Bit 4 Bit1 TAPE DRIVE REGISTER (TDR) Address 3F3 READ/WRITE The Tape Drive ...
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S/W POWER RESET DOWN RESET 0 0 COND. Other applications can set the data rate in the DSR. The data rate of the floppy controller is the most recent write of either the DSR or CCR. The DSR ...
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DRIVE RATE DRT1 DRT0 SEL1 Drive Rate Table (Recommended 360K, 1.2M, 720K, 1.44M and 2.88M Vertical Format 01 = 3-Mode Drive Meg Tape Note 1: The DRATE and DENSEL ...
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DATA REGISTER (FIFO) Address 3F5 READ/WRITE All command parameter information, disk data and result status are transferred between the host processor and the floppy disk controller through the Data Register. Data transfers are governed by the RQM and DIO bits ...
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BIT UNDEFINED The data bus outputs are read as ‘0’. BIT 7 DSKCHG This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the ...
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CONFIGURATION CONTROL REGISTER (CCR) Address 3F7 WRITE ONLY PC/AT and PS/2 Modes RESET N/A N/A COND. BIT 0 and 1 DATA RATE SELECT 0 and 1 These bits determine the data rate of the floppy controller. ...
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BIT NO. SYMBOL NAME Head Address The current head address. 1,0 DS1,0 Drive Select BIT NO. SYMBOL NAME 7 EN End of Cylinder Data Error 4 OR Overrun/ Underrun Data ...
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BIT NO. SYMBOL NAME 4 T0 Track Head Address Indicates the status of the HDSEL pin. 1,0 DS1,0 Drive Select RESET There are three sources of system reset on the FDC: the nPCI_RESET pin, a reset ...
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Before writing to the FDC, the host must examine the RQM and DIO bits of the Main Status Register. RQM and DIO must be equal to "1" and "0" respectively before command bytes may be written. RQM is set false ...
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Note that when the host is sending data to the FIFO of the FDC, the internal sector count will be complete when the FDC reads the last byte from its side of the FIFO. There may be a delay in ...
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Commands can be written whenever the FDC is in the command phase. Each command has a unique set of needed parameters and status results. The FDC checks to see that the first byte is a valid command and, if valid, ...
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Table 16 - Description of Command Symbols SYMBOL NAME N Sector Size Code This specifies the number of bytes in a sector. If this parameter is "00", then the sector size is 128 bytes. transferred is determined by the DTL ...
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PHASE R Command W MT MFM ──────── C ──────── W ──────── H ──────── W ──────── R ──────── W ──────── N ──────── W ─────── EOT ─────── W ─────── GPL ─────── W ─────── DTL ─────── Execution ...
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PHASE R Command W MT MFM ──────── C ──────── W ──────── H ──────── W ──────── R ──────── W ──────── N ──────── W ─────── EOT ─────── W ─────── GPL ─────── W ─────── DTL ─────── Execution ...
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PHASE R Command W 0 MFM Execution Result PHASE R Command W MT MFM ...
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PHASE R Command W 0 MFM Execution for W Each Sector Repeat Result ────── Undefined ────── R ────── Undefined ────── R ────── Undefined ────── ...
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PHASE R Command Execution PHASE R Command EIS EFIFO Execution W ───────── PRETRK ───────── PHASE R Command W 1 ...
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PHASE R Command W 0 MFM Execution Result R ──────── ST0 ──────── R ──────── ST1 ──────── R ──────── ST2 ──────── PHASE R Command PHASE ...
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FDC reads the sector's data field and transfers the data to the FIFO. After completion of the read operation from the current sector, the sector address is incremented by one ...
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Table 20 - Skip Bit vs Read Data Command DATA ADDRESS SK BIT MARK TYPE VALUE ENCOUNTERED 0 Normal Data 0 Deleted Data 1 Normal Data 1 Deleted Data Read Deleted Data This command is the same as the Read ...
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FINAL SECTOR MT HEAD TRANSFERRED TO HOST 0 0 Less than EOT Equal to EOT 1 Less than EOT Equal to EOT 1 0 Less than EOT Equal to EOT 1 Less than EOT Equal to EOT NC: No Change, ...
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DTL EOT ≤ # Sectors Per Side DTL EOT > # Sectors Per Side ≤ # Sectors Remaining AND EOT ≤ # Sectors Per Side 0 1 ...
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GAP4a SYNC IAM GAP1 80x 12x 50x SYSTEM 3740 (SINGLE DENSITY) FORMAT GAP4a SYNC IAM GAP1 40x 6x 26x GAP4a SYNC IAM GAP1 80x 12x 50x ...
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The following commands will generate an interrupt upon completion. They do not return any result bytes highly recommended that control commands be followed by the Sense Interrupt Status command. Otherwise, valuable interrupt status information will be lost. Recalibrate ...
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The Seek, Relative Seek, and Recalibrate commands have no result phase. The Sense Interrupt Status command must be issued immediately after these commands to terminate them and to provide verification of the head position (PCN). The H (Head Address) bit ...
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EFIFO - A "1" disables the FIFO (default). This means data transfers are asked for on a byte-by-byte basis. Defaults to "1", FIFO disabled. The threshold defaults to "1". POLL - Disable polling of the drives. Defaults to "0", polling ...
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Perpendicular Mode The Perpendicular Mode command should be issued prior to executing Read/Write/Format commands that access a disk drive with perpendicular recording capability. With this command, the length of the Gap2 field and VCO enable timing can be altered to ...
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WGATE GAP LOCK In order to protect systems with long DMA latencies against older application software that can disable the FIFO the LOCK Command has been added. This command should only be used by the FDC ...
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FDC SWAP BIT The FDC_SWAP bit in the FDD Mode Register (configuration register 0xF0) can be used to swap Drive 0 and Drive 1. The FDC_SWAP is defined as follows: Bit[4] FDC_SWAP Not Swap (default ...
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The LPC47B27x incorporates two full function UARTs. They are compatible with the NS16450, the 16450 ACE registers and the NS16C550A. The UARTS perform serial-to-parallel conversion on received characters and parallel-to- serial conversion on transmit characters. The data rates are independently ...
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Interrupt Identification Register and disables any Serial Port interrupt out of the LPC47B27x. All other system functions operate in their normal manner, including the Line Status and MODEM Status Registers. The contents of the Interrupt Enable Register are described below. ...
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INTERRUPT IDENTIFICATION REGISTER (IIR) Address Offset = 2H, DLAB = X, READ By accessing this register, the host CPU can determine the highest priority interrupt and its source. Four levels of priority interrupt exist. They are in descending order of ...
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FIFO INTERRUPT MODE IDENTIFICATION ONLY REGISTER PRIORITY BIT 3 BIT 2 BIT 1 BIT Third Fourth LINE CONTROL REGISTER (LCR) Address Offset = 3H, DLAB = 0, READ/WRITE This register contains ...
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Bit 4 Even Parity Select bit. When bit logic "1" and bit logic "0", an odd number of logic "1"'s is transmitted or checked in the data word bits and the parity bit. When ...
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LINE STATUS REGISTER (LSR) Address Offset = 5H, DLAB = X, READ/WRITE Bit 0 Data Ready (DR set to a logic "1" whenever a complete incoming character has been received and transferred into the Receiver Buffer Register or ...
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MODEM STATUS REGISTER (MSR) Address Offset = 6H, DLAB = X, READ/WRITE This 8 bit register provides the current state of the control lines from the MODEM (or peripheral device). In addition to this current state information, four bits of ...
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FIFO INTERRUPT MODE OPERATION When the RCVR FIFO and receiver interrupts are enabled (FCR bit 0 = "1", IER bit 0 = "1"), RCVR interrupts occur as follows: A. The receive data available interrupt will be issued when the FIFO ...
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Bit 5 indicates when the XMIT FIFO is empty. Bit 6 indicates that both the XMIT FIFO and shift register are empty. Bit 7 indicates whether there are any errors in the RCVR FIFO. There is no trigger level reached ...
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Note 1: The following defines the state of the TXD1 pin depending on the chip configuration. //Activate bit is cleared on a VTR POR, VCC POR, PCI Reset, or Soft Reset If (Activate Bit=0) then TXD1 is tristate. Else if ...
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...
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DLAB is Bit 7 of the Line Control Register (ADDR = 3). Note 1 Bit 0 is the least significant bit the first bit serially transmitted or received. Note 2 When operating in the XT mode, this bit ...
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NOTES ON SERIAL PORT OPERATION FIFO MODE OPERATION: GENERAL The RCVR FIFO will hold bytes regardless of which trigger level is selected. TX AND RX FIFO OPERATION The Tx portion of the UART transmits data through TXD ...
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The infrared interface provides a two-way wireless communications port using infrared as a transmission medium. Several IR implementations have been provided for the second UART in this chip (logical device 5), IrDA, Consumer Remote Control, and Amplitude Shift Keyed IR. ...
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Overview Serial Port 3 is used exclusively in the LPC47B27x as an MPU-401-compatible MIDI Interface. The LPC47B27x MPU-401 hardware includes a Host Interface, an MPU-401 command controller, configuration registers, and a compatible UART (Figure 2). Each of these components are ...
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Registers (Ports) The run-time registers in the MPU-401 Host Interface are shown below in Table 33. TABLE 33 - MPU-401 HOST INTERFACE REGISTERS REGISTER NAME ADDRESS MIDI DATA MPU-401 I/O Base Address STATUS MPU-401 I/O Base Address + 1 COMMAND ...
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Bit 6 – MIDI Transmit Busy Bit 6 MIDI Transmit Busy indicates the send (write) state of the MIDI Data port and Command port (Table 37). There are no interrupts associated with MIDI transmit (write) data. TABLE 37 - MIDI ...
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NOTE IRQ is the MPU-401 Host Interface IRQ shown in Figure 2. Threshold = 1. 4 NOTE MIDI RX CLOCK is the MIDI bit clock. The MIDI bit clock period is 32µs. MPU-401 Command Controller Overview Commands are written ...
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The MIDI protocol requires 31.25k Baud (±1%) and 10 bits total per frame: 1 start bit, 8 data bits, no parity, and 1 stop bit. For example, there are 320 microseconds per serial MIDI data byte. MIDI data is transferred ...
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The LPC47B27x incorporates an IBM XT/AT compatible parallel port. This supports the optional PS/2 type bi-directional parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP) parallel port modes. Refer to the Configuration Registers for information ...
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High Speed Mode Note: For the cable interconnection required for ECP support and the Slave Connector pin numbers, refer to the IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14, 1993. This document is ...
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BIT 1 AUTOFD - AUTOFEED This bit is inverted and output onto the nAUTOFD output. A logic 1 causes the printer to generate a line feed after each line is printed. A logic 0 means no autofeed. BIT 2 nINIT ...
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EPP DATA PORT 3 ADDRESS OFFSET = 07H The EPP Data Port 3 is located at an offset of '07H' from the base address. Refer to EPP DATA PORT 0 for a description of operation. This register is only available ...
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If the EPP bus is ready (nWAIT is inactive high) then the chip must wait for active low before changing the state of WRITE or before nDATASTB goes active. The read can complete once nWAIT is ...
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The host initiates an I/O read cycle to the selected EPP register. 3. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and the nWRITE signal is valid nWAIT is asserted, the ...
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These terms may be considered synonymous: PeriphClk, nAck HostAck, nAutoFd PeriphAck, Busy nPeriphRequest, nFault nReverseRequest, nInit nAckReverse, PError Xflag, Select ECPMode, nSelectln HostClk, nStrobe Reference Document: IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev 1.14, July 14, ...
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NAME TYPE nAck I Indicates valid data driven by the peripheral when asserted. This signal handshakes with nAutoFd in reverse. PeriphAck (Busy) I This signal deasserts to indicate that the peripheral can accept data. This signal handshakes with nStrobe in ...
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MODE 000 SPP mode 001 PS/2 Parallel Port mode 010 Parallel Port Data FIFO mode 011 ECP Parallel Port mode 100 EPP mode (If this option is enabled in the configuration registers) 101 Reserved 110 Test mode 111 Configuration mode ...
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BIT 1 AUTOFD - AUTOFEED This bit is inverted and output onto the nAUTOFD output. A logic 1 causes the printer to generate a line feed after each line is printed. A logic 0 means no autofeed. BIT 2 nINIT ...
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The readIntrThreshold can be determined by setting the direction bit to 1 and filling the empty tFIFO a byte at a time until serviceIntr is set. This may generate a spurious interrupt, but will indicate that the threshold has been ...
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This bit shall be set to 1 whenever there are readIntrThreshold or more valid bytes to be read from the FIFO. BIT 1 full Read only 1: The FIFO cannot accept another byte or the FIFO is completely full. 0: ...
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Once in an extended forward mode the software should wait for the FIFO to be empty before switching back to mode 000 or 001. In this case all control signals will be deasserted before the mode switch ecp ...
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Data Compression The ECP port supports run length encoded (RLE) decompression in hardware and can transfer compressed data to a peripheral. Run length encoded (RLE) compression in hardware is not supported. To transfer compressed data in ECP mode, the compression ...
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DMA TRANSFERS DMA transfers are always to or from the ecpDFifo, tFifo or CFifo. DMA utilizes the standard PC ...
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Programmed I/O - Transfers from the Host to the FIFO In the forward direction an interrupt occurs when serviceIntr is 0 and there are writeIntrThreshold or more bytes free in the FIFO. At this time if the FIFO is empty ...
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PARALLEL PORT FLOPPY DISK CONTROLLER The Floppy Disk Control signals are available optionally on the parallel port pins. When this mode is selected, the parallel port is not available. There are two modes of operation, PPFD1 and PPFD2. These modes ...
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NOTE : The Parallel Port Control register reads as “Cable Not Connected” when the Parallel Port FDC is enabled; i.e., STROBE = AUTOFD = SLC = 0 and nINIT = 1. Table 47 - FDC Parallel Port Pins CONNECTOR ...
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FLOPPY ON PARALLEL PORT PIN The “floppy on the parallel port” pin function, FDC_PP, is muxed onto GP43. This pin function can be used to switch the parallel port pins between the FDC and the parallel port. The FDC_PP pin ...
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Power management capabilities are provided for the following logical devices: floppy disk, UART 1, UART 2 and the parallel port. For each logical device, two types of power management are provided: direct powerdown and auto powerdown. FDC Power Management Direct ...
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Accessing the part during powerdown may cause an increase in the power consumption by the part. The part will revert back to its low power mode when the access ...
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FDD PINS nTRK0 nINDEX nDSKCHG nMTR0 nDS0 nDIR nSTEP nWDATA nWGATE nHDSEL DRVDEN[0:1] UART Power Management Direct power management is controlled by CR22. Refer to CR22 for more information. Auto Power Management is enabled by CR23-B4 and B5. When set, ...
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ECP is not enabled in the configuration registers. 2 SPP, PS/2 Parallel port or EPP mode is selected through ecr while in ECP mode. Exit Auto Powerdown The parallel port logic can change powerdown modes when the ECP mode ...
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Once a Start Frame has been initiated the Host Controller will take over driving the SER_IRQ low in the next clock and will continue driving the SER_IRQ low for a programmable period of three to seven clocks. This makes a ...
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The SMI is enabled onto the SMI frame of the Serial IRQ via bit 6 of SMI Enable Register 2 and onto the SMI pin via bit 7 of the SMI Enable Register 2. Stop Cycle Control Once all IRQ/Data ...
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KEYBOARD CONTROLLER DESCRIPTION The LPC47B27x is a Super I/O and Universal Keyboard Controller that is designed for intelligent keyboard management in desktop computer applications. The Universal Keyboard Controller uses an 8042 microcontroller CPU core. This section concentrates on the ...
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Keyboard Data Write This bit write only register. When written, the C/D status bit of the status register is cleared to zero and the IBF bit is set. Keyboard Data Read This bit read ...
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EXTERNAL KEYBOARD AND MOUSE INTERFACE Industry-standard PC-AT-compatible keyboards employ a two-wire, bidirectional TTL interface for data transmission. Several sources also supply PS/2 mouse products that employ the same type of interface. To facilitate system expansion, the LPC47B27x provides four signal ...
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IBF (Input Buffer Full)- This flag is set to 1 whenever the host system writes data into the input data register. Setting this flag activates the LPC47B27x CPU's nIBF (MIRQ) interrupt if enabled. When the LPC47B27x CPU reads the input ...
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Bit Function driven low. Writing this bit causes the ALT_A20 signal to be driven high. 0 Alternate System Reset. This read/write bit provides an alternate system reset function. This function provides an alternate means to reset the ...
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P20 KRST_GA20 P92 Bit 2 Bit 0 Pulse Gen Note: When Port 92 is disabled, writes are ignored and reads return undefined values. Bit 1 of Port 92, the ALT_A20 signal, is used to force nA20M to the ...
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Latches On Keyboard and Mouse IRQs The implementation of the latches on the keyboard and mouse interrupts is shown below. KLATCH Bit KINT 8042 FIGURE 5 – KEYBOARD LATCH MLATCH Bit MINT 8042 FIGURE 6 – MOUSE LATCH The KLATCH ...
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Bit[4]: MLATCH – Mouse Interrupt latch control bit. 0=MINT is the 8042 MINT ANDed with Latched MINT (default), 1=MINT is the latched 8042 MINT. Bit[3]: KLATCH – Keyboard Interrupt latch control bit. 0=KINT is the 8042 KINT ANDed with Latched ...
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KDAT and MDAT signals cannot be isolated internal to the part. This causes an IO_PME generated if the keyboard and/or mouse PME events are enabled. Note that the keyboard and mouse isolation bits only prevent the internal 8042 ...
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The LPC47B27x provides a set of flexible Input/Output control functions to the system designer through the 37 dedicated independently programmable General Purpose I/O pins (GPIO). The GPIO pins can perform basic I/O and many of them can be individually enabled ...
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TABLE 55 - General Purpose I/O Port Assignments PIN NO. DEFAULT ALT. /QFP FUNCTION FUNC GPIO Joystick 1 Button 1 33 GPIO Joystick 1 Button 2 34 GPIO Joystick 2 Button 1 35 GPIO Joystick 2 Button 2 ...
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PIN NO. DEFAULT ALT. /QFP FUNCTION FUNC GPIO Ring Indicator 2 94 GPIO Data Carrier Detect 2 95 GPIO Receive Serial Data 2 96 GPIO Transmit Serial Data 2 97 GPIO Data Set Ready 2 98 GPIO Request ...
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D-TYPE SD-bit D Q GPx_nIOW Transparent Q D GPx_nIOR GPIO Data Register Bit-n Note: When the following functions are selected, the associated GPIO pins have bi-directional functionality: P12, P16, P17 and game port x-axis and y-axis inputs (J1X, J1Y, J2X, ...
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GP60, GP61 The following PME status and enable registers for these GPIOs: PME_STS2 and PME_EN2 for GP10-GP17 PME_STS3 and PME_EN3 for GP20-GP22, GP24-GP27 PME_STS4 and PME_EN4 for GP30-GP33, GP41, GP43, GP60 and GP61 PME_STS5 and PME_EN5 for GP50-GP57 The following ...
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Note 6: These pins cannot be used for wakeup events to generate a PME while the part is under VTR power (VCC=0). The GP32, GP33 and GP53 pins come up as output and low on a VCC POR and hard ...
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Watchdog time-out status bit in the WDT_CTRL Runtime register. Note: Regardless of the current state of the WDT, the WDT time-out status bit can be directly set or cleared by the Host CPU. There ...
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The P12 function also has a polarity select bit in Configuration Register 0xF0 in Logical Device 1. The SMI logic for these events is implemented such that the output of the status bit for each event is combined with the ...
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The LPC47B27x offers support for power management events (PMEs). A power management event is requested by a function via the assertion of the nIO_PME signal. In the LPC47B27x, the nIO_PME is asserted by active transitions on the ring indicator inputs ...
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SMI output is inactive. 1=The group SMI output is active. Note: Bit 5 of the SMI_EN2 register must also be set. This bit is cleared on a write of ‘1’. There is a bit in the PME Enable ...
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Note: The generation of a PME for this event is controlled by the PME enable bit (located in the PME_EN1 register at bit 5) when the logic for feature is turned on. SMSC LPC47B27x - 118 - DATASHEET Rev. 08-10-04 ...
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FAN SPEED CONTROL AND MONITORING The LPC47B27x implements fan speed control outputs and fan tachometer inputs. The implementation of these features are described in the sections below. Fan Speed Control The fan speed control for the LPC47B27x is implemented as ...
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Fan x Clock Control, Bit D0 The Fan x Clock Control bit D0 is used to override the Duty Cycle Control for Fan x bits and force F always high. When D0 = “0”, the DCC bits determine the F ...
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The fan tachometer input signal and clock source is shown below. Fan Tachometer Input T P Clock Source for Counter The counter is reset by the rising edge of each pulse (and by writing the preload register). The counter does ...
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RPM for the fan by programming the divisor and preload value accordingly. Typical practice is to consider 70% of normal RPM a fan failure, at which point Term 1 in Equation 1 for the example above will ...
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The following register describes the functionality to support security in the LPC47B27x. GPIO Device Disable Register Control The GPIO pin GP43 is used for the Device Disable Register Control (DDRC) function. Setting bits[3:2] of the GP43 configuration register to ‘01’, ...
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Game software will write a byte to the game port to reset it, and then poll (read) the port until the x and y-axis RC time constant pins (TIMA,B) time out (return to zero). The elapsed time indicates the resistance ...
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The game port register is a read-only register. However, writing to the game port resets the RC time constant pins (TIMA zero. The reset of the time constant pins occur on the “back” edge of the write signal ...
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ISA IRQ TO SERIAL IRQ CONVERSION CAPABILITY Pins 92, and 94-100 have the ISA IRQs muxed onto the GPIO pins as inputs. If the IRQ function is chosen for these pins via the GPIO registers, then the associated IRQ input ...
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The following registers are runtime registers in the LPC47B27x. They are located at the address programmed in the Base I/O Address in Logical Device A at the offset shown. These registers are powered by VTR. Table 59 - Runtime Register ...
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REGISTER OFFSET HARD (hex) RESET TYPE R/W 0x00 36 ...
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REGISTER OFFSET HARD (hex) RESET TYPE R/W - 60- Note 1: This register contains some bits that are read or write only. Note 2: Bit 0 is not ...
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REG OFFSET NAME (hex) PME_STS1 04 Default = 0x00 (R/W) on VTR POR PME_STS2 05 Default = 0x00 (R/W) on VTR POR PME_STS3 06 Default = 0x00 (R/W) on VTR POR SMSC LPC47B27x DESCRIPTION PME Wake Status Register 1 This ...
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REG OFFSET NAME (hex) PME_STS4 07 Default = 0x00 (R/W) on VTR POR (Note 7) PME_STS5 08 Default = 0x00 (R/W) on VTR POR (Note 7) N/A 09 (R) PME_EN1 0A Default = 0x00 (R/W) on VTR POR SMSC LPC47B27x ...
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REG OFFSET NAME (hex) PME_EN2 0B Default = 0x00 (R/W) on VTR POR PME_EN3 0C Default = 0x00 (R/W) on VTR POR SMSC LPC47B27x DESCRIPTION PME Wake Enable Register 2 This register is used to enable individual LPC47B27x PME wake ...
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REG OFFSET NAME (hex) PME_EN4 0D Default = 0x00 (R/W) on VTR POR PME_EN5 0E Default = 0x00 (R/W) on VTR POR N/A 0F (R) SMI_STS1 10 Default = 0x02 (R/W) on VTR POR Bit 1 is set to ‘1’ ...
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REG OFFSET NAME (hex) SMI_STS2 11 Default = 0x00 (R/W) on VTR POR SMI_STS3 12 Default = 0x00 (R/W) on VTR POR SMI_STS4 13 Default = 0x00 (R/W) on VTR POR (Note 7) SMI_STS5 14 Default = 0x00 (R/W) on ...
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REG OFFSET NAME (hex) SMI_EN2 17 Default = 0x00 (R/W) on VTR POR SMI_EN3 18 Default = 0x00 (R/W) on VTR POR SMI_EN4 19 Default = 0x00 (R/W) on VTR POR SMI_EN5 1A Default = 0x00 (R/W) on VTR POR ...
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REG OFFSET NAME (hex) MSC_STS 1C Default = 0x00 (R/W) on VTR POR N/A 1D (R) Force Disk Change 1E Default = 0x03 on (R/W) VCC POR, Hard Reset, and VTR POR Floppy Data Rate 1F Select Shadow (R) UART1 ...
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REG OFFSET NAME (hex) UART2 FIFO Control 21 Shadow (R) Device Disable 22 Register Read/Write when Default = 0x00 GP43 register VTR POR bits[3: AND GP43 pin = 0 OR GP43 register bits[3:2] ≠ 01 READ-ONLY When GP43 ...
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REG OFFSET NAME (hex) GP11 24 Default = 0x01 on VTR POR (R/W) GP12 25 Default = 0x01 (R/W) on VTR POR GP13 26 Default = 0x01 (R/W) on VTR POR GP14 27 Default = 0x01 (R/W) on VTR POR ...
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REG OFFSET NAME (hex) GP17 2A Default = 0x01 (R/W) on VTR POR GP20 2B Default = 0x01 (R/W) on VTR POR GP21 2C Default =0x01 (R/W) on VTR POR GP22 2D Default =0x01 (R/W) on VTR POR N/A 2E ...
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REG OFFSET NAME (hex) GP25 30 (R/W) Default = 0x01 on VTR POR GP26 31 Default = 0x01 (R/W) on VTR POR GP27 32 Default = 0x01 (R/W) on VTR POR GP30 33 Default = 0x01 (R/W) on VTR POR ...
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REG OFFSET NAME (hex) GP33 36 Default = 0x01 (R/W) on VTR POR Default = 0x00 on VCC POR and Hard Reset (Note 4) GP34 37 Default = 0x05 (R/W) on VTR POR GP35 38 Default = 0x04 (R/W) on ...
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REG OFFSET NAME (hex) GP41 3C Default =0x01 (R/W) on VTR POR GP42 3D Default =0x01 (R/W) on VTR POR GP43 3E Default = 0x01 (R/W) on VTR POR Bits[3:2] are reset (cleared) on VCC POR, VTR POR and Hard ...
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REG OFFSET NAME (hex) GP50 3F Default = 0x01 (R/W) on VTR POR GP51 40 Default = 0x01 (R/W) on VTR POR GP52 41 Default = 0x01 (R/W) on VTR POR GP53 42 Default = 0x00 (R/W) on VTR POR, ...
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REG OFFSET NAME (hex) GP55 44 Default = 0x01 (R/W) on VTR POR GP56 45 Default = 0x01 (R/W) on VTR POR GP57 46 Default = 0x01 (R/W) on VTR POR GP60 47 Default = 0x01 (R/W) on VTR POR ...
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REG OFFSET NAME (hex) GP61 48 Default = 0x01 (R/W) on VTR POR N/A 49 (R) N/A 4A (R) GP1 4B Default = 0x00 (R/W) on VTR POR GP2 4C Default = 0x00 on VTR POR (R/W) GP3 4D Default ...
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REG OFFSET NAME (hex) GP6 50 Default = 0x00 (R/W) on VTR POR N/A 51 (R) WDT_TIME_OUT 52 Default = 0x00 (R/W) on Vcc POR or HARD RESET WDT_VAL 53 Default = 0x00 (R/W) on VCC POR or HARD RESET ...
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REG OFFSET NAME (hex) WDT_CTRL 55 Default = 0x00 (R/W) on VTR POR FAN1 56 Default = 0x00 (R/W) on VTR POR FAN2 57 Default = 0x00 (R/W) on VTR POR SMSC LPC47B27x DESCRIPTION Watch-dog timer Control Bit[0] Watch-dog Status ...
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REG OFFSET NAME (hex) Fan Control 58 Default = 0x50 (R/W) on VTR POR Fan1 Tachometer 59 Register (R) Default = 0x00 on VTR POR Fan2 Tachometer 5A Register (R) Default = 0x00 on VTR POR Fan1 Preload 5B Register ...
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REG OFFSET NAME (hex) LED1 5D Default = 0x00 (R/W) on VTR POR LED2 5E Default = 0x00 (R/W) on VTR POR Keyboard Scan 5F Code (R/W) Default = 0x00 on VTR POR N/A 60-7F (R) User Note: When selecting ...
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The Configuration of the LPC47B27x is very flexible and is based on the configuration architecture implemented in typical Plug-and-Play components. The LPC47B27x is designed for motherboard applications in which the resources required by their components are known. With its flexible ...
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Configuration Mode The system sets the logical device information and activates desired logical devices through the INDEX and DATA ports. In configuration mode, the INDEX PORT is located at the CONFIG PORT address and the DATA PORT is at INDEX ...
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INDEX TYPE HARD RESET 0x20 R 0x51 0x21 R (Note 1) 0x22 R/W 0x00 0x23 R/W 0x00 0x24 R/W 0x04 0x26 R/W Sysopt=0: 0x2E Sysopt=1: 0x4E 0x27 R/W Sysopt=0: 0x00 Sysopt=1: 0x00 0x28 R - 0x2A R/W - 0x2B R/W ...
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INDEX TYPE HARD RESET 0x60, R/W 0x00, 0x61 0x00 0x62, R/W 0x00, 0x63 0x00 0x70 R/W 0x00 0x74 R/W 0x04 0xF0 R/W 0x00 0xF1 R/W 0x02 0xF2 R/W 0x03 LOGICAL DEVICE 6 CONFIGURATION REGISTERS (Reserved) LOGICAL DEVICE 7 CONFIGURATION REGISTERS ...
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Table 63 - Chip Level Registers REGISTER ADDRESS Chip (Global) Control Registers 0x00 - 0x01 Config Control 0x02 W Default = 0x00 on VCC POR, VTR POR and HARD RESET 0x03 - 0x06 Reserved - Writes are ignored, reads return ...
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REGISTER ADDRESS Power Mgmt 0x23 R/W Default = 0x00 on VCC POR, VTR POR and HARD RESET Note 1: CR22 Bit 5 and Bit 7 are reset by VTR POR only. Table 63 – Chip Level Registers (cont’d) REGISTER ADDRESS ...
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Table 63 – Chip Level Registers (cont’d) REGISTER ADDRESS TEST 6 0x2A R/W Default = 0x00, on VCC POR and VTR POR TEST 4 0x2B R/W Default = 0x00, on VCC POR and VTR POR TEST 5 0x2C R/W Default ...
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Table 64 – Logical Device Registers LOGICAL DEVICE REGISTER ADDRESS Note1, Note 3 Activate (0x30) Default = 0x00 on VCC POR, VTR POR, HARD RESET and SOFT RESET Logical Device Control (0x31-0x37) Logical Device Control (0x38-0x3f) Memory Base Address (0x40-0x5F) ...
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The Logical device's Activate Bit and its Pwr/Control Bit are linked such that setting or clearing one sets or clears the other. Note 2: If the I/O Base Addr of the logical device is not within the Base I/O range ...
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Table 65 - I/O Base Address Configuration Register Description LOGICAL DEVICE LOGICAL REGISTER NUMBER DEVICE INDEX 0x07 KYBD n/a 0x08 Reserved n/a 0x09 Game Port 0x60,0x61 0x0A PME 0x60,0x61 0x0B MPU-401 0x60,0x61 Config. Config. Port 0x26, 0x27 Port (Note 2) ...
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Note: An Interrupt is activated by setting the Interrupt Request Level Select 0 register to a non-zero value AND : For the FDC logical device by setting DMAEN, bit D3 of the Digital Output Register. For the PP logical device ...
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MODE (FROM ECR REGISTER) 010 011 100 101 110 111 CONFIG d. Keyboard Controller: Refer to the KBD section of this spec. e. MPU-401: Refer to the MPU-401 section of this spec. SMSC Defined Logical Device Configuration Registers The SMSC ...
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Table 68 - Floppy Disk Controller, Logical Device 0 [Logical Device Number = 0x00] NAME REG INDEX FDD Option Register 0xF1 R/W Default = 0x00 on VCC POR, VTR POR and HARD RESET FDD Type Register 0xF2 R/W Default = ...
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Table 69 - Parallel Port, Logical Device 3 [Logical Device Number = 0x03] NAME REG INDEX PP Mode Register 0xF0 R/W Default = 0x3C on VCC POR, VTR POR and HARD RESET PP Mode Register 2 0xF1 R/W Default = ...
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UART Interrupt Operation Table 71 - Serial Port 2, Logical Device 5 [Logical Device Number = 0x05] NAME REG INDEX Serial Port 2 0xF0 R/W Mode Register Default = 0x00 on VCC POR, VTR POR and HARD RESET IR Option ...
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Table 72 - KYBD, Logical Device 7 [Logical Device Number = 0x07] NAME REG INDEX Bit[3] KLATCH (default) Bit[2] Port 92 Select Bit[1] Reserved Bit[0] Reserved 0xF1 - 0xFF Reserved - read as ‘0’ Table 73 - PME, Logical Device ...
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Table 74 – MPU-401 [Logical Device Number = 0x0B] NAME REG INDEX SOFT RESET, VCC POR and VTR POR SMSC LPC47B27x DEFINITION Bit[6] A6 Bit[7] A7 Note Bit[0] must be “0”. - 166 - DATASHEET STATE Rev. 08-10-04 ...
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OPERATIONAL DESCRIPTION MAXIMUM GUARANTEED RATINGS* Operating Temperature Range.....................................................................................................0 Storage Temperature Range..................................................................................................... -55 Lead Temperature Range ..........................................................................Refer to JEDEC Spec. J-STD-020 Positive Voltage on any pin, with respect to Ground.......................................................................... V Negative Voltage on any pin, with respect to Ground .............................................................................. ...
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PARAMETER SYMBOL IO8 Type Buffer Low Output Level High Output Level Output Leakage O8 Type Buffer Low Output Level High Output Level O12 Type Buffer Low Output Level High Output Level IO12 Type Buffer Low Output Level High Output Level ...
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PARAMETER SYMBOL Backdrive Protect/ChiProtect (All pins excluding LAD[3:0], nLDRQ, nLPCPD, nLFRAME) 5V Tolerant Pins (All pins excluding LAD[3:0], nLDRQ, nLPCPD, nLFRAME) Inputs and Outputs in High Impedance State LPC Bus Pins (LAD[3:0], nLDRQ, nLPCPD, nLFRAME) V Supply Current Active CC ...
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For the Timing Diagrams shown, the following capacitive loads are used on outputs. SER_IRQ nLAD[3:0] nLDRQ nDS0-1 PD[0:7] nSTROBE MIDI_Tx ...
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CLOCKI FIGURE 9A - INPUT CLOCK TIMING NAME DESCRIPTION t1 Clock Cycle Time for 14.318MHz t2 Clock High Time/Low Time for 14.318MHz t1 Clock Cycle Time for 32kHz t2 Clock High Time/Low Time for 32kHz Clock Rise Time/Fall Time (not ...
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CLK Output Delay Tri-State Output FIGURE 10 – OUPUT TIMING MEASUREMENT CONDITIONS, LPC SIGNALS NAME DESCRIPTION t1 CLK to Signal Valid Delay – Bused Signals t2 Float to Active Delay t3 Active to Float Delay CLK Input FIGURE 11 – ...
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PCI_CLK nLFRAME nLAD[3: Note: L1=Start; L2=CYCTYP+DIR; L3=Sync of 0000 PCI_CLK nLFRAME nLAD[3: Note: L1=Start; L2=CYCTYP+DIR; L3=Sync of 0000 SMSC LPC47B27x Address Data TAR Sync=0110 FIGURE 12 – I/O WRITE Address TAR Sync=0110 FIGURE 13 – I/O ...
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PCI_CLK nLDRQ Start FIGURE 14 – DMA REQUEST ASSERTION THROUGH nLDRQ PCI_CLK nLFRAME Start C+D CHL Size nLAD[3:0] FIGURE 15 – DMA WRITE (FIRST BYTE) Note: L1=Sync of 0000 PCI_CLK nLFRAME nLAD[3:0] Start C+D CHL Size FIGURE 16 – DMA ...
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FIGURE 17 – FLOPPY DISK DRIVE TIMING (AT MODE ONLY) NAME DESCRIPTION t1 nDIR Set Up to STEP Low t2 nSTEP Active Time Low t3 nDIR Hold Time after nSTEP t4 nSTEP ...
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PD<7:0> nDATASTB nADDRSTB nWAIT FIGURE 18 – EPP 1.9 DATA OR ADDRESS WRITE CYCLE NAME DESCRIPTION t1 nWAIT Asserted to nWRITE Asserted (Note 1) t2 nWAIT Asserted to nWRITE Change (Note 1) t3 nWAIT Asserted to PDATA Invalid ...
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PD<7:0> DATASTB ADDRSTB nWAIT FIGURE 19 – EPP 1.9 DATA OR ADDRESS READ CYCLE NAME DESCRIPTION t1 nWAIT Asserted to nWRITE Deasserted t2 nWAIT Asserted to nWRITE Modified (Notes 1,2) t3 nWAIT Asserted to PDATA Hi-Z (Note ...
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PD<7:0> nDATASTB nADDRSTB nWAIT FIGURE 20 – EPP 1.7 DATA OR ADDRESS WRITE CYCLE NAME DESCRIPTION t1 Command Deasserted to nWRITE Change t2 Command Deasserted to PDATA Invalid t3 PDATA Valid to Command Asserted t4 nWRITE to Command t5 ...
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PD<7:0> nDATASTB nADDRSTB nWAIT FIGURE 21 – EPP 1.7 DATA OR ADDRESS READ CYCLE NAME DESCRIPTION t1 Command Asserted to PDATA Valid t2 Command Deasserted to PDATA Hi-Z t3 Command Deasserted to nWAIT Deasserted SMSC LPC47B27x t1 MIN 0 ...
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ECP PARALLEL PORT TIMING Parallel Port FIFO (Mode 101) The standard parallel port is run at or near the peak 500KBytes/sec allowed in the forward direction using DMA. The state machine does not examine nACK and begins the next transfer ...
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PD<7:0> nSTROBE BUSY FIGURE 22 - PARALLEL PORT FIFO TIMING NAME DESCRIPTION t1 PDATA Valid to nSTROBE Active t2 nSTROBE Active Pulse Width t3 PDATA Hold from nSTROBE Inactive (Note 1) t4 nSTROBE Active to BUSY Active t5 BUSY Inactive ...
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PD<7:0> nSTROBE t6 BUSY FIGURE 23 - ECP PARALLEL PORT FORWARD TIMING NAME DESCRIPTION t1 nALF Valid to nSTROBE Asserted t2 PDATA Valid to nSTROBE Asserted t3 BUSY Deasserted to nALF Changed (Notes 1,2) t4 BUSY Deasserted to PDATA ...
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PD<7:0> nACK nALF FIGURE 24 - ECP PARALLEL PORT REVERSE TIMING NAME DESCRIPTION t1 PDATA Valid to nACK Asserted t2 nALF Asserted to PDATA Changed t3 nACK Asserted to nALF Deasserted (Notes 1,2) t4 nACK Deasserted to nALF Asserted (Note ...
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DATA IRRX n IRRX Pa rame ter t1 Pulse Width at 1 15kba ud t1 Pul se Wid th at 57.6kba ud t1 Pul se Wid th at 38.4kba ud t1 Pul se Wid th ...
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DAT IRT X n IRT X t1 Pulse Width at 115kbaud t1 Pulse Width at 57.6kbaud t1 Pulse Width at 38.4kbaud t1 Pulse Width at 19.2kbaud t1 Pulse Width at 9.6kbaud t1 ...
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DAT IRRX n IRRX IRRX IRRX Pa ramet odu lated Out put Bit T ime t2 Off Bit T ime t3 M odu lated Outp ut ...
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IRTX n IRT MIRTX MIRT odu lated Out put Bit T ime t2 Off Bit T ime t3 M odu lated Outp ut " ...
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PCI_CLK SER_IRQ FIGURE 29 – SETUP AND HOLD TIME NAME DESCRIPTION t1 SER_IRQ Setup Time to PCI_CLK Rising t2 SER_IRQ Hold Time to PCI_CLK Rising Data Start TXD1, 2 FIGURE 30 – SERIAL PORT DATA NAME DESCRIPTION t1 Serial Port ...
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J1X, J1Y, J2X, J2Y t1 FIGURE 31 – JOYSTICK POSITION SIGNAL NAME DESCRIPTION t1 Rise Time to 2/3 VREF J1B1, J1B2, J2B1, J2B2 FIGURE 32 – JOYSTICK BUTTON SIGNAL NAME DESCRIPTION t1, t2 Button Fall/Rise Time SMSC LPC47B27x MIN 20 ...
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CLK CLK KCLK MCLK Start Bit Bit 0 KDAT/ MDAT FIGURE 33 – KEYBOARD/MOUSE RECEIVE/SEND DATA TIMING NAME DESCRIPTION t1 Time from DATA transition to falling edge of CLOCK (Receive) t2 Time from ...
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Idle (No Data) Data Start Bit MIDI_Tx FIGURE 34 – MIDI DATA BYTE NAME DESCRIPTION t1 MIDI Data Bit Time Note: The MIDI bit clock is 31.25kHz +/- 1% t2 FANx FIGURE 35 – FAN OUTPUT TIMING NAME DESCRIPTION t1 ...
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FAN_TACHx FIGURE 36 – FAN TACHOMETER INPUT TIMING NAME DESCRIPTION t1 Pulse Time (1/2 Revolution Time=30/RPM) t2 Pulse High Time t3 Pulse Low Time Note the clock used for the tachometer counter 30.52 * DVSR, ...
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FIGURE 38 - 100 PIN QFP PACKAGE OUTLINE Min Nominal 0. 2. 23. 19.90 ~ 17. 13. 0.11 ~ 0.73 0. 1.95 ...
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Board Test Mode Board test mode can be entered as follows: On the rising (deasserting) edge of nPCI_RESET, drive nLFRAME low and drive LAD[0] low. Exit board test mode as follows: On the rising (deasserting) edge of nPCI_RESET, drive either ...
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Setup Warning: Ensure power supply is off during setup. 1. Connect VSS (pins 7, 31, 60, & 76) and AVSS (pin 40) to ground. 2. Connect VCC (pins 53, 65 & 93), VTR (pin 18), and VREF (pin 44) to ...