ST16C2550 Exar Corporation, ST16C2550 Datasheet

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... OCTOBER 2004 GENERAL DESCRIPTION The ST16C2550 (C2550 dual universal asynchronous receiver and transmitter (UART). The ST16C2550 is an improved version of the PC16550 UART with higher operating speed and faster access times. The C2550 provides functions with 16 byte FIFO’s, a modem control interface, and data rates Mbps ...

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... RXB 4 RXA 5 ST16C2550 TXRDYB# 6 48-pin TQFP TXA 7 TXB 8 9 OP2B# CSA# 10 CSB RXB 10 RXA 11 ST16C2550 TXRDYB# 12 44-pin PLCC TXA 13 TXB 14 OP2B# 15 CSA CSB# 36 RESET DTRB# 35 DTRA# 34 RTSA OP2A# 31 RXRDYA# INTA INTB ...

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... TQFP 2.97V TO 5.5V DUART WITH 16-BYTE FIFO O PERATING T EMPERATURE R ANGE 0°C to +70°C Active. See the ST16C2550CQ48 for new designs. 0°C to +70°C Active 0°C to +70°C Active -40°C to +85°C Active. See the ST16C2550IQ48 for new designs. -40°C to +85°C Active -40° ...

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... ST16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO PIN DESCRIPTIONS Pin Description 40-PDIP 44-PLCC N AME DATA BUS INTERFACE IOR IOW CSA CSB# ...

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... UART channel B Receive Data. Normal receive data input must idle at logic 1 condition not used, tie it to VCC or pull it high via a 100k ohm resistor UART channel B Request-to-Send (active low) or general purpose output not used, leave it unconnected. 5 ST16C2550 D ESCRIPTION ...

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... ST16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO Pin Description 40-PDIP 44-PLCC N AME CTSB DTRB DSRB CDB RIB OP2B ANCILLARY SIGNALS XTAL1 16 18 XTAL2 17 19 RESET 35 39 VCC 40 44 GND Pin type: I=Input, O=Output, IO= Input/output, OD=Output Open Drain. ...

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... REV. 4.4.0 1.0 PRODUCT DESCRIPTION The ST16C2550 (C2550) integrates the functions of two 16C550 Universal Asynchrounous Receiver and Transmitter (UART). Each UART is independently controlled having its own set of device configuration registers. The C2550 provides serial asynchronous receive data synchronization, parallel-to-serial and serial- to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into parallel data that is required with digital data systems ...

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... UART. No clock (oscillator nor external clock) is required to operate a data bus transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# signals. Both UART channels share the same data bus for host operations. The data bus interconnections are shown ST16C2550 D IGURE ...

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... AND INS PERATION FOR - least 1 byte in FIFO 1 = FIFO empty INTB AND IN PERATION - FIFO below trigger level 1 = FIFO above trigger level 9 ST16C2550 DMA M AND ODE ) NABLED FCR Bit (DMA Mode Enabled) T RANSMITTER FCR (FIFO E ) NABLED R OR ...

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... ST16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO 2.7 Crystal Oscillator or External Clock Input The C2550 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a system clock to the Baud Rate Generators (BRG) section found in each of the UART ...

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... ll sisto lta ST16C2550 XTENDED ATA ATE OWER UPPLY HART ...

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... ST16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO The C2550 divides the basic external clock by 16. The basic 16X clock provides table rates to support standard and custom applications using the same system design. The Baud Rate Generator divides the input 16X clock 16 by any divisor from ...

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... THR Interrupt (ISR bit-1) (THR) Enabled by IER bit-1 Transmit Shift Register (TSR) O FIFO M PERATION IN ODE Transm it FIFO THR THR Interrupt (ISR bit-1) when TX FIFO becom es em pty. FIFO is enabled by FCR bit-0=1. Transm it Data Shift Register (TSR) 13 ST16C2550 TXNOFIFO1 T XFIF O 1 ...

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... ST16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO 2.10.1 Receive Holding Register (RHR) - Read-Only The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift Register. It provides the receive data interface to the host processor. The RHR register is part of the receive FIFO of 16 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register ...

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... TO 5.5V DUART WITH 16-BYTE FIFO ACK IN HANNEL AND VCC (THR/FIFO) MCR bit-4=1 (RHR/FIFO) VCC RTS# CTS# VCC DTR# DSR# OP1# RI# VCC OP2# CD# 15 ST16C2550 TXA/TXB RXA/RXB RTSA#/RTSB# CTSA#/CTSB DTRA#/DTRB# DSRA#/DSRB# RIA#/RIB# OP2A#/OP2B# CDA#/CDB# ...

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... ST16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO 3.0 UART INTERNAL REGISTERS Each of the UART channel in the C2550 has its own set of configuration registers selected by address lines A0, A1 and A2 with CSA# or CSB# selecting the channel. The registers are 16C550 compatible. The complete register set is shown on ...

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... Error RI# DSR# CTS# Delta Input Input Input CD# Bit-6 Bit-5 Bit-4 Bit-3 Baud Rate Generator Divisor Bit-6 Bit-5 Bit-4 Bit-3 Bit-6 Bit-5 Bit-4 Bit-3 17 ST16C2550 OMMENT Bit-2 Bit-1 Bit-0 Bit-2 Bit-1 Bit-0 LCR[ Line TX RX Stat. ...

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... IER versus Receive/Transmit FIFO Polled Mode Operation When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the ST16C2550 in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). ...

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... RIORITY S B TATUS ITS LSR (Receiver Line Status Register RXRDY (Receive Data Time-out RXRDY (Received Data Ready TXRDY (Transmit Ready MSR (Modem Status Register None (default) 19 ST16C2550 L EVEL S OURCE OF INTERRUPT Table 8). ...

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... ST16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO 4.5 FIFO Control Register (FCR) - Write-Only This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and select the DMA mode. The DMA, and FIFO modes are defined as follows: FCR[0]: TX and RX FIFO Enable • ...

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... Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The receiver must be programmed to check the same format. 2.97V TO 5.5V DUART WITH 16-BYTE FIFO BIT-0 W ORD LENGTH (default TOP BIT LENGTH ORD (B LENGTH IT TIME 0 5,6,7,8 1 (default 1-1/2 1 6,7 ST16C2550 ( )) S ...

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... ST16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO LCR[5]: TX and RX Parity Select If the parity bit is enabled, LCR BIT-5 selects the forced parity format. • LCR[5] = logic 0, parity is not forced (default). • LCR[5] = logic 1 and LCR[4] = logic 0, parity bit is forced to a logical 1 for the transmit and receive data. ...

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... In the FIFO mode this bit is set when the transmit FIFO is empty cleared when the transmit FIFO contains at least 1 byte. LSR[6]: THR and TSR Empty Flag 2.97V TO 5.5V DUART WITH 16-BYTE FIFO Figure 11. 23 ST16C2550 ...

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... ST16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO This bit is set to a logic 1 whenever the transmitter goes idle set to logic 0 whenever either the THR or TSR contains a data character. In the FIFO mode this bit is set to a logic 1 whenever the transmit FIFO and transmit shift register are both empty. ...

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... Bits 7-0 = 0xXX Bits 7-0 = 0xXX Bits 7-0 = 0xXX Bits 7-0 = 0xXX Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x01 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x60 Bits 3-0 = Logic 0 Bits 7-4 = Logic levels of the inputs inverted Bits 7-0 = 0xFF RESET STATE Logic 1 Logic 1 Logic 1 Logic 1 Logic 1 Logic 0 Three-State Condition 25 ST16C2550 See ...

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... ST16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation PACKAGE THERMAL RESISTANCE DATA Thermal Resistance (48-TQFP) Thermal Resistance (44-PLCC) Thermal Resistance (40-PDIP) ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS TA=0 NLESS OTHERWISE NOTED 5.0V (± ...

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... ST16C2550 5.0V (±10 NIT OMMENTS ns ns MHz 55ns if VCC = 3.3V +10%/-5% and (See Figure 12 Bclk ns ns Bclk ...

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... ST16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO AC ELECTRICAL CHARACTERISTICS TA (-40 + FOR INDUSTRIAL GRADE PACKAGE LOAD WHERE APPLICABLE P S ARAMETER YMBOL T Reset Pulse Width RST N Baud Rate Divisor Bclk Baud Clock IGURE IMING ALUES 80 70 ...

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... A & B IMING OR HANNELS Change of state Change of state T MOD Active Active Valid Data 29 ST16C2550 Change of state Active Active T RSI Active Active Change of state Valid Address RDV Valid Data RDTm ...

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... ST16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO F 16 IGURE ATA US RITE IMING A0-A2 Valid Address T AS CSA#/ CSB# IOW# D0- & I IGURE ECEIVE EADY NTERRUPT RX Start D0:D7 Bit INT RXRDY# IOR# (Reading data out of RHR ...

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... ISR is read T WRI T SRT [FIFO M , DMA D IMING ODE D0:D7 D0:D7 D0: SSI RX FIFO fills Trigger Level or RX Data Timeout 31 ST16C2550 C A & B HANNELS D0:D7 ISR is read T WRI T SRT T WT TXNonFIFO ] C A & B ISABLED FOR HANNELS D0:D7 D0: FIFO drops below RX ...

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... ST16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO F 20 & I IGURE ECEIVE EADY NTERRUPT Start Stop Bit Bit RX D0:D7 D0: INT RX FIFO fills Trigger Level or RX Data Timeout RXRDY# IOR# (Reading data out of RX FIFO & I IGURE RANSMIT EADY NTERRUPT ...

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... TO 5.5V DUART WITH 16-BYTE FIFO T [FIFO M , DMA M IMING ODE Stop Bit T D0:D7 S D0:D7 S D0: FIFO no SRT longer empty TX FIFO Full 33 ST16C2550 & B ODE NABLED FOR HANNELS Last Data Byte Transmitted S D0:D7 T D0: FIFO Empty At least 1 empty location in FIFO ...

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... ST16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO PACKAGE DIMENSIONS (48 PIN TQFP - Seating Plane Note: The control dimension is the millimeter column SYMBOL α INCHES MILLIMETERS MIN MAX MIN 0.039 0.047 1 ...

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... MIN 0.165 0.180 4.19 0.090 0.120 2.29 0.020 --- 0.51 0.013 0.021 0.33 0.026 0.032 0.66 0.008 0.013 0.19 0.685 0.695 17.40 0.650 0.656 16.51 0.590 0.630 14.99 0.500 typ. 12.70 typ. 0.050 BSC 1.27 BSC 0.042 0.056 1.07 0.042 0.048 1.07 0.025 0.045 0.64 35 ST16C2550 C Seating Plane MAX 4.57 3.05 --- 0.53 0.81 0.32 17.65 16.66 16.00 1.42 1.22 1.14 ...

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... ST16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO PACKAGE DIMENSIONS (40 PIN PDIP Seating Plane L B Note: The control dimension is the millimeter column SYMBOL α INCHES MILLIMETERS MIN MAX MIN 0.160 0.250 4.06 0.015 0.070 ...

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... Datasheet October 2004. Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. 2.97V TO 5.5V DUART WITH 16-BYTE FIFO REVISION HISTORY Description , T and OSC and 16 to A0-A2. Clarified MCR bit-3 description. NOTICE 37 ST16C2550 ...

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... ST16C2550 REV. 4.4.0 GENERAL DESCRIPTION .................................................................................................1 A ................................................................................................................................................1 PPLICATIONS F .....................................................................................................................................................1 EATURES F 1. ST16C2550 B D IGURE LOCK IAGRAM ..................................................................................................................................................... 2 IGURE IN UT SSIGNMENT .................................................................................................................................3 ORDERING INFORMATION PIN DESCRIPTIONS .........................................................................................................4 1.0 PRODUCT DESCRIPTION .....................................................................................................................7 2.0 FUNCTIONAL DESCRIPTIONS .............................................................................................................8 2.1 CPU INTERFACE .............................................................................................................................................. ST16C2550 IGURE ATA US 2.2 DEVICE RESET ................................................................................................................................................ 8 2.3 CHANNEL A AND B SELECTION .................................................................................................................... ...

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... ODE NABLED FOR T [FIFO M , DMA M D IMING ODE ODE ISABLED T [FIFO M , DMA M E IMING ODE ODE NABLED II ST16C2550 REV. 4.4.0 A & B ......................................................... 30 A & B ....................................................... & B........................................ 31 HANNELS C A & B......................................... 32 HANNELS ] C A & B ........................... 32 FOR HANNELS ] C A & B ............................ 33 FOR HANNELS ...