MCM69F819TQ11 Motorola, MCM69F819TQ11 Datasheet

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MCM69F819TQ11

Manufacturer Part Number
MCM69F819TQ11
Description
256K x 18 bit flow-through burstRAM synchronous fast static RAM
Manufacturer
Motorola
Datasheet
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
256K x 18 Bit Flow–Through
BurstRAM Synchronous
Fast Static RAM
a burstable, high performance, secondary cache for the PowerPC
high performance microprocessors. It is organized as 256K words of 18 bits
each. This device integrates input registers, a 2–bit address counter, and high
speed SRAM onto a single monolithic circuit for reduced parts count in cache
data RAM applications. Synchronous design allows precise cycle control with the
use of an external clock (K).
enable (G) and linear burst order (LBO) are clock (K) controlled through positive–
edge–triggered noninverting registers.
addresses can be generated internally by the MCM69F819 (burst sequence
operates in linear or interleaved mode dependent upon the state of LBO) and
controlled by the burst address advance (ADV) input pin.
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.
nous write enable (SW) are provided to allow writes to either individual bytes or
to all bytes. The two bytes are designated as “a” and “b”. SBa controls DQa and
SBb controls DQb. Individual bytes are written if the selected byte writes SBx are
asserted with SW. All bytes are written if either SGW is asserted or if all SBx and
SW are asserted.
from the memory array.
operate on a 2.5 V or 3.3 V power supply. All inputs and outputs are JEDEC stan-
dard JESD8–5 compatible.
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
REV 7
1/22/98
MOTOROLA FAST SRAM
The MCM69F819 is a 4M bit synchronous fast static RAM designed to provide
Addresses (SA), data inputs (DQx), and all control signals except output
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst
Write cycles are internally self–timed and are initiated by the rising edge of the
Synchronous byte write (SBx), synchronous global write (SGW), and synchro-
For read cycles, a flow–through SRAM allows output data to simply flow freely
The MCM69F819 operates from a 3.3 V core power supply and all outputs
Motorola, Inc. 1998
MCM69F819–7.5: 7.5 ns Access/ 8.5 ns Cycle (117 MHz)
MCM69F819–8: 8 ns Access/10 ns Cycle (100 MHz)
MCM69F819–8.5: 8.5 ns Access/11 ns Cycle 90 MHz)
MCM69F819–11: 11 ns Access/20 ns Cycle (50 MHz)
3.3 V + 10%, – 5% Core Power Supply, 2.5 V or 3.3 V I/O Supply
ADSP, ADSC, and ADV Burst Control Pins
Selectable Burst Sequencing Order (Linear/Interleaved)
Single–Cycle Deselect Timing
Internally Self–Timed Write Cycle
Byte Write and Global Write Control
PB1 Version 2.0 Compatible
JEDEC Standard 119–Pin PBGA and 100–Pin TQFP Packages
and other
MCM69F819
CASE 983A–01
Order this document
TQ PACKAGE
ZP PACKAGE
CASE 999–02
by MCM69F819/D
PBGA
TQFP
MCM69F819
1

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MCM69F819TQ11 Summary of contents

Page 1

... PB1 Version 2.0 Compatible JEDEC Standard 119–Pin PBGA and 100–Pin TQFP Packages The PowerPC name is a trademark of IBM Corp., used under license therefrom. REV 7 1/22/98 MOTOROLA FAST SRAM Motorola, Inc. 1998 Order this document MCM69F819 ZP PACKAGE and other CASE 999–02 TQ PACKAGE CASE 983A– ...

Page 2

... ADSP SA SA1 SA0 SGW SW SBa SBb SE1 SE2 SE3 G MCM69F819 2 FUNCTIONAL BLOCK DIAGRAM BURST COUNTER K2 CLR 2 18 ADDRESS REGISTER WRITE REGISTER a WRITE REGISTER b K2 ENABLE REGISTER 2 18 256K x 18 ARRAY DATA–IN REGISTER K DQa – DQb MOTOROLA FAST SRAM ...

Page 3

... DQb V SS SA0 LBO DDQ TOP VIEW 119 BUMP PBGA MOTOROLA FAST SRAM PIN ASSIGNMENTS 7 100 9695 DDQ DDQ DQb 8 ...

Page 4

... SBx pins. If only byte write signals SBx are being used, tie this pin low Supply Core Power Supply. V DDQ Supply I/O Power Supply Supply Ground. NC — No Connection: There is no connection to the chip. Description MOTOROLA FAST SRAM ...

Page 5

... MOTOROLA FAST SRAM Symbol Type ADSC Input Synchronous Address Status Controller: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a READ, WRITE, or chip deselect ...

Page 6

... WRITE 0 X High–Z WRITE 1 X High–Z WRITE 1 X High–Z WRITE 4th Address (Internal X11 X00 X01 X10 4th Address (Internal X11 X10 X01 X00 SW SBa SBb MOTOROLA FAST SRAM ...

Page 7

... Indicates the average thermal resistance between the die and the printed circuit board. 4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method 1012.1). MOTOROLA FAST SRAM Value Unit ...

Page 8

... IH2 20% t KHKH (MIN) Figure 1. Undershoot Voltage Min Typ Max Unit 3.135 3.3 3.6 V 2.375 2.5 2.9 V – 0.3 — 0.7 V 1.7 — 0.3 V 1.7 — V DDQ + 0.3 V Min Typ Max Unit 3.135 3.3 3.6 V 3.135 3 – 0.5 — 0 — 0 — V DDQ + 0.5 V MOTOROLA FAST SRAM ...

Page 9

... TTL levels for I/O’s are IH2 . TTL levels for other inputs are V in CAPACITANCE (f = 1.0 MHz 3 Periodically Sampled Rather Than 100% Tested) Parameter Input Capacitance Input/Output Capacitance MOTOROLA FAST SRAM Symbol Min I lkg(I) — I lkg(O) — MCM69F819–7.5 I DDA — ...

Page 10

... See Figure 2 Unless Otherwise Noted MCM69F819–11 50 MHz Max Min Max U i Unit Notes N — 20 — ns — 4.5 — ns — 4.5 — ns 8.5 — 3.5 — 3.5 ns — 0 — — 2 — — 0 — 3.5 — 3 3 — 2 — ns — 0.5 — ns MOTOROLA FAST SRAM ...

Page 11

... Figure 3. Lumped Capacitive Load and Typical Derating Curve INPUT WAVEFORM OUTPUT WAVEFORM NOTES: 1. Input waveform has a slew rate of 1 V/ns. 2. Rise time is measured from 0.5 to 2.0 V unloaded. 3. Fall time is measured from 2.0 to 0.5 V unloaded. Figure 4. Unloaded Rise and Fall Time Characterization MOTOROLA FAST SRAM ...

Page 12

... Pull–Up for 3.3 V I/O Supply (c) Pull–Down – 38 – 105 CURRENT (mA) – 40 – 80 – 120 CURRENT (mA CURRENT (mA) MOTOROLA FAST SRAM ...

Page 13

... MOTOROLA FAST SRAM MCM69F819 13 ...

Page 14

... Force the address inputs to a low state ( preferably < 0.2 V. STOP CLOCK WITH READ TIMING Q(A1) Q( CLOCK STOP WAKE UP ADSP (CONTINUE (INITIATES BURST READ) BURST READ) A2 Q(A2) MOTOROLA FAST SRAM ...

Page 15

... NOTE: While the clock is stopped, DATA IN must be fixed in a high ( low ( state to reduce the DC current of the input buffers. For lowest power operation, all data and address lines should be held in a low ( state and control lines held in an inactive state. MOTOROLA FAST SRAM STOP CLOCK WITH WRITE TIMING D( FIXED (SEE NOTE) HIGH– ...

Page 16

... For lowest power operation, all data and address lines should be held in a low ( state and control lines held in an inactive state. MCM69F819 FIXED (SEE NOTE) HIGH–Z DATA CLOCK STOP (DESELECTED) WAKE UP MOTOROLA FAST SRAM ...

Page 17

... X X Blank = Trays Tape and Reel Speed (7.5 = 7.5 ns ns, 8.5 = 8.5 ns ns) Package (ZP = PBGA TQFP) MCM69F819ZP8 MCM69F819ZP8.5 MCM69F819ZP8R MCM69F819ZP8.5R MCM69F819TQ8 MCM69F819TQ8.5 MCM69F819TQ8R MCM69F819TQ8. ADSP ADSC ADV SE1 SE2 LBO D(F) D(H) D(G) WRITES MCM69F819ZP11 MCM69F819ZP11R MCM69F819TQ11 MCM69F819TQ11R MCM69F819 17 ...

Page 18

... DIMENSION b IS THE MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A. 4. DATUM A, THE SEATING PLANE, IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. MILLIMETERS DIM MIN MAX A ––– 2.40 A1 0.50 0.70 A2 1.30 1.70 A3 0.80 1.00 D 22.00 BSC D1 20.32 BSC D2 19.40 19.60 E 14.00 BSC E1 7.62 BSC E2 11.90 12.10 b 0.60 0.90 e 1.27 BSC MOTOROLA FAST SRAM ...

Page 19

... D1 TIPS 0.20 (0.008) C A–B A –H– –C– SEATING PLANE 0.05 (0.002 VIEW AB MOTOROLA FAST SRAM TQ PACKAGE TQFP CASE 983A– TIPS 0.20 (0.008) C A–B D –D– E/2 –B– E1 D ...

Page 20

... Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “ ...

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