LU3X31T-T64 Agere Systems, LU3X31T-T64 Datasheet
LU3X31T-T64
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LU3X31T-T64 Summary of contents
Page 1
... Typical applications for this part are CardBus and PCMCIA Ethernet products. Operating at 3.3 V, the LU3X31T-T64 is a powerful device for the forward migration of legacy 10 Mbits/s products and noncom- pliant (does not have autonegotiation) 100 Mbits/s devices ...
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... LU3X31T-T64 Single-Port 3 V 10/100 Ethernet Transceiver TX Contents Overview................................................................................................................................................................... 1 Features ................................................................................................................................................................... 1 Pin Descriptions........................................................................................................................................................ 6 Functional Description ............................................................................................................................................ 10 Media Independent Interface (MII) ...................................................................................................................... 10 100Base-X Module.............................................................................................................................................. 11 100Base-X Receiver ........................................................................................................................................... 14 100Base-X Link Monitor ...................................................................................................................................... 15 100Base-TX Transceiver..................................................................................................................................... 16 10Base-T Module ................................................................................................................................................ 16 Clock Synthesizer................................................................................................................................................ 18 Autonegotiation ................................................................................................................................................... 18 Reset Operation .................................................................................................................................................. 19 100Base-X PCS Configuration............................................................................................................................ 20 MII Registers .......................................................................................................................................................... 21 dc and ac Specifications......................................................................................................................................... 31 Absolute Maximum Ratings ...
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... Table 36. MII Transmit Timing ................................................................................................................................ 36 Table 37. Transmit Timing ...................................................................................................................................... 37 Table 38. Receive Timing....................................................................................................................................... 38 Table 39. Reset and Configuration Timing ............................................................................................................. 39 Table 40. PMD Characteristics............................................................................................................................... 40 Figures Figure 1. LU3X31T-T64 Block Diagram ................................................................................................................... 4 Figure 2. Pin Diagram .............................................................................................................................................. 5 Figure 3. 100Base-X Data Path ............................................................................................................................. 12 Figure 4. 10Base-T Module Data Path .................................................................................................................. 16 Figure 5. Hardware Reset Configurations.............................................................................................................. 19 Figure 6. System Timing........................................................................................................................................ 32 Figure 7 ...
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... RXDV RXER RXCLK COL CRS 4 10/100-TX PCS REGISTER/ CONFIG/ CONTROL PCS CLOCK SYNTHESIS AND RECOVERY BASELINE WANDER CORRECTION Figure 1. LU3X31T-T64 Block Diagram Preliminary Data Sheet July 2000 10/100-TX DRIVERS AUTONEG RX10 SQUELCH ADAPTIVE EQUALIZER Lucent Technologies Inc. TPTX TPRX 5-6779(F).ar.2 ...
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... Twisted-Pair Transmit Driver Pair. These pins are used to transmit 100Base-T MLT-3 signals on Category 5 UTP cable or 10Base-T Manchester signals on Category 3 UTP cable. Twisted-Pair Receive Pair. These pins receive 100Base-T MLT 3 or 10Base-T Manchester data. LU3X31T-T64 Single-Port 3 V 10/100 Ethernet Transceiver TX 48 XOUT 47 ...
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... LU3X31T-T64 Single-Port 3 V 10/100 Ethernet Transceiver TX Pin Descriptions Table 2. Twisted-Pair Transceiver Control Pin Pin Name I/O No. 50 REF100 I 49 REF10 I 5 TPTXTR I Table 3. MII Interface Pin Pin Name I/O No. 18 RXDV O 19 RXER O 20 RXD3 O 21 RXD2 O 22 RXD1 O 23 RXD0 O 24 RXCLK ...
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... When autonegotiation is enabled, this input sets the ability register bit in advertisement register 4. When autonegotiation is not enabled, this input will select the mode of operation. This pin has an internal 40 k resistor. See Table 7 for LEDSP description. LU3X31T-T64 Single-Port 3 V 10/100 Ethernet Transceiver TX pull- pull-up ...
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... Transmit LED or Activity LED. When bit 7 of register 17h is 0, this output will drive LED if the LU3X31T-T64 is transmitting data. If the control bit is set, then the LED will be driven whenever receive or transmit activity is present. This pin has an internal 40 k pull-down. The LED should be con- nected as LOGIC 0 configuration in Figure 5 without the 10 k resistor ...
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... XIN pin, then XOUT should be grounded for minimum power consumption. See Figure 15 for a connection dia- gram. Reset (Active-Low). This input must be held low for a minimum reset the LU3X31T-T64. Reserved. These pins are unused inputs and should be tied to ground. V ...
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... RXCLK is generated by the clock recovery module of either the 100Base-X or 10Base-T receiver. Status Interface. Two status signals, COL and CRS, are generated in the LU3X31T-T64 to indicate collision status and carrier sense status to the MAC. COL is asserted asynchronously whenever LU3X31T-T64 is transmitting and receiving at the same time in a half- duplex operation mode ...
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... Reading the interrupt status register (regis- ter 1Eh) shows the source of the interrupt and clears the interrupt output signal. In addition to the MDIOINTZ pin, the LU3X31T-T64 can also support the interrupt scheme used by the TI Thun- * derLAN MAC ...
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... The 100Base-X transmitter consists of functional blocks which convert synchronous 4-bit nibble data, as provided by the MII 125 Mbits/s serial data stream. The LU3X31T-T64 implements the 100Base-X transmit state machine as specified in the IEEE 802.3u Standard, Clause 24 and comprises the following func- tional blocks in its data path: ...
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... July 2000 Functional Description (continued) Assertion of the TXER input while the TXEN input is also asserted will cause the LU3X31T-T64 to substitute HALT code-groups for the 5B code derived from data present at TXD[3:0]. However, the SSD (/J/K) and ESD (/T/R) will not be substituted with HALT code-groups. ...
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... NRZI-to-NRZ & Serial-to-Parallel Conversion. The recovered data is converted from NRZI to NRZ and then to a 5-bit parallel format for the LU3X31T-T64 descrambler. The 5-bit parallel data is not necessarily aligned to 4B/5B code-group’s boundary. ...
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... If this condition is detected, then the LU3X31T-T64 will assert RXER and present RXD[3:0] = 1110 to the MII for the cycles that correspond to received 5B code- groups until at least two IDLE code groups are detected ...
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... It includes the receiver, transmitter, collision, heartbeat, loopback, jabber, waveshaper, and link integrity functions, as defined in the standard. Figure 4 provides an overview for the 10Base-T module. The LU3X31T-T64 10Base-T module is comprised of the following functional blocks: Manchester encoder and decoder Collision detector Link test function ...
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... The SQE test function is disabled in full-duplex mode. Jabber Function. The jabber function monitors the LU3X31T-T64's output and disables the transmitter if it attempts to transmit a longer than legal-sized packet. If TXEN is high for greater than 24 ms, the 10Base-T transmitter will be disabled and COL will go high ...
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... Whether a valid link has been established (bit 2). The autonegotiation advertisement register at address 04h indicates the autonegotiation abilities to be adver- tised by the LU3X31T-T64. All available abilities are transmitted by default, but any ability can be sup- pressed by writing to this register or configuring exter- nal pins. ...
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... Note that initializing the PHY address to zero automatically isolates the MII interface. Autonegotiation and Speed Configuration The five pins listed in Table 11 configure the speed capability of LU3X31T-T64. The logic state of these pins, at powerup or reset, are latched into the advertisement register (register address 04h) for autonegotiation purpose. ...
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... LU3X31T-T64 Single-Port 3 V 10/100 Ethernet Transceiver TX Functional Description (continued) Table 11. Autonegotiation Configuration Pins at RESET 100FDEN 100HDEN AUTOEN Pin 2 Pin 11 Pin 4 (Reg 4.8) (Reg 4. 100Base-X PCS Configuration The logic state of BPSCR, BP4B5B, and BPALIGN pins latched into bits 15, 14, and 12 of the Config 100 register at address 18h during powerup or reset ...
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... PHY Reset. 0 Normal operation. Setting this bit initiates the software reset function that resets the entire LU3X31T-T64 device, except for the phase-locked loop cir- cuit. It will relatch in all hardware configura- tion pin values and set all registers to their default values. The software reset process takes complete ...
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... Setting this control bit isolates the LU3X31T-T64 from the MII, with the excep- tion of the serial management interface. When this bit is asserted, the LU3X31T-T64 does not respond to TXD[3:0], TXEN, and TXER inputs, and it presents a high imped- ance on its TXCLK, RXCLK, RXDV, RXER, RXD[3:0], COL, and CRS outputs ...
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... LU3X31T-T64 supports 10Base-T half-duplex mode. 1 Capable of 100Base-T2. 0 Not capable of 100Base-T2. This bit is hardwired to 0, indicating that the LU3X31T-T64 does not support 100Base-T2. Ignore when read. Accepts management frames with pre- amble suppressed. 0 Will not accept management frames with preamble suppressed. This bit is hardwired to 1, indicating that the LU3X31T-T64 accepts management frame without preamble ...
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... It is unlatched when this reg- ister is read. 1 Capable of autonegotiation. 0 Not capable of autonegotiation. This bit defaults to 1, indicating that the LU3X31T-T64 is capable of autonegotiation. 1 Link is up. 0 Link is down. This bit reflects the current state of the link- test-fail state machine. Loss of a valid link causes a 0 latched into this bit ...
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... This 4-bit field contains the advertised ability of this PHY. At powerup or reset, the logic level of 100FDEN, 100HDEN, 10FDEN, and 10HDEN pins are latched into bits 8 through 5, respectively. These 5 bits are hardwired to 00001h, indicating that the LU3X31T-T64 supports IEEE 802.3 CSMA/CD. Description 1 Capable of next-page function. 0 Not capable of next-page function ...
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... Local device is next-page capable. 0 Local device is not next-page capa- ble. This bit defaults to 0, indicating that the LU3X31T-T64 is not next-page able new page has been received new page has been received. This bit is latched to 1 when a new link code word page has been received. This ...
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... LEDRX output. 0 Normal operation. 1 3-state LEDTX/ACTLED output. 0 Normal operation. 1 3-state LNKLED output. 0 Normal operation. 1 3-state LEDCOL output. 0 Normal operation. 1 3-state LEDFD output. 0 Normal operation. 1 3-state LEDSP output. 0 Normal operation. LU3X31T-T64 Single-Port 3 V R/W Default RO 0h R/W 0h R/W 0h R R/W 0h R/W 0 R/W 0 R/W 0 ...
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... LU3X31T-T64 Single-Port 3 V 10/100 Ethernet Transceiver TX MII Registers (continued) Table 21. PHY Control/Status Register (Register 17h) (continued) Bit(s) Name 0 LED Pulse Stretching Disable 1 Table 22. Config 100 Register (Register 18h) Bit(s) Name 15 BPSCR 14 BP4B5B 13 Reserved 12 BPALIGN 11:10 Reserved 9 Force Good Link 100 8:6 Reserved 5 Accept Halt ...
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... Low squelch level selected. 0 Normal squelch level selected. 1 Jabber function disabled. 0 Normal operation. Reserved. 1—Powers down the LU3X31T-T64 com- pletely. The part comes out of this mode after a reset is asserted and deasserted. 0—Normal operation. Reserved. 1—Disable autopolarity function. 0—Enable autopolarity function. Reserved. ...
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... LU3X31T-T64 Single-Port 3 V 10/100 Ethernet Transceiver TX MII Registers (continued) Table 25. Status 100 Register (Register 1Bh) Bit(s) Name 15:14 Reserved 13 PLL Lock Status 12:0 Reserved Table 26. Status 10 Register (Register 1Ch) Bit(s) Name 15 Polarity 14:0 Reserved Table 27. Interrupt Mask Register (Register 1Dh) Bit(s) Name 15 Reserved 14 Receiver Error Counter Full 0 ...
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... Parameter Operating Supply Voltage * Power Dissipation : 100 Mbits Mbits/s Autonegotiating * Power dissipations are specified at 3.3 V and 25 °C. This is the power dissipated by the LU3X31T-T64. Lucent Technologies Inc. Description Reserved. 1 Receive error counter has rolled over. 0 Receive error counter has not rolled over ...
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... LU3X31T-T64 Single-Port 3 V 10/100 Ethernet Transceiver TX dc and ac Specifications Table 31. dc Characteristics Parameter Symbol Recommended Power V Supply V Supply Current I DD 100Base-TX Supply Current I DD 10Base-TX Supply Current I DD Autonegotiation Mode Supply Current I DD 100Base-FX TTL Input High Voltage V TTL Input Low Voltage ...
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... TXCLK Low Pulse Width (10 Mbits/s) t4 TXCLK Period (100 Mbits/s)* TXCLK Period (10 Mbits/s)* ± * Specified at 100 ppm. t1 TXCLK X IN Figure 7. Transmit Timing (Input and Output) Lucent Technologies Inc. Description t2 t3 LU3X31T-T64 Single-Port 3 V 10/100 Ethernet Transceiver TX Min Max Unit 140 260 ns 14 — — ...
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... LU3X31T-T64 Single-Port 3 V 10/100 Ethernet Transceiver TX Clock Timing (continued) Table 34. Management Clock Symbol t1 MDC High Pulse Width t2 MDC Low Pulse Width t3 MDC Period t4 MDIO(I) Setup to MDC Rising Edge t5 MDIO(O) Hold Time from MDC Rising Edge t6 MDIO(O) Valid from MDC Rising Edge ...
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... RXCLK Period (100 Mbits/s) RXCLK Period (10 Mbits/s MII) RXCLK Period (10 Mbits/s serial) RXCLK RXER, RXDV, RXD[3:0] Lucent Technologies Inc. Description Figure 9. MII Receive Timing LU3X31T-T64 Single-Port 3 V 10/100 Ethernet Transceiver TX Min Max Unit 10 — — 140 ...
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... LU3X31T-T64 Single-Port 3 V 10/100 Ethernet Transceiver TX Clock Timing (continued) Table 36. MII Transmit Timing Symbol t1 TXER, TXEN, TXD[3:0] Setup to TXCLK Rise t2 TXER, TXEN, TXD[3:0] Hold After TXCLK Rise TXCLK TXER, TXEN, TXD[3:0] 36 Description t1 Figure 10. MII Transmit Timing Preliminary Data Sheet July 2000 ...
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... Sampled TXEN Inactive to End of Frame (100 Mbits/s) Sampled TXEN Inactive to End of Frame (10 Mbits/s) TXCLK TXEN CRS TPTX Lucent Technologies Inc. Description t1 t3 PREAMBLE Figure 11. Transmit Timing LU3X31T-T64 Single-Port 3 V 10/100 Ethernet Transceiver TX Min Max Unit 0 4 bits — 1.5 bits 0 16 bits — ...
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... LU3X31T-T64 Single-Port 3 V 10/100 Ethernet Transceiver TX Clock Timing (continued) Table 38. Receive Timing Symbol t1 Receive Frame to Sampled Edge of RXDV (100 Mbits/s) Receive Frame to Sampled Edge of RXDV (10 Mbits/s) t2 Receive Frame to CRS High (100 Mbits/s) Receive Frame to CRS High (10 Mbits/s) t3 End of Receive Frame to Sampled Edge of ...
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... Power On to Reset High t2 Reset Pulse Width t3 Configuration Pin Setup t4 Configuration Pin Hold V CC RSTZ CONFIG Lucent Technologies Inc. Description Figure 13. Reset and Configuration Timing LU3X31T-T64 Single-Port 3 V 10/100 Ethernet Transceiver TX Min Max Unit 1.0 — ms 1.0 — ms 1.0 — ms 1.0 — 5-6791(F) ...
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... LU3X31T-T64 Single-Port 3 V 10/100 Ethernet Transceiver TX Clock Timing (continued) Table 40. PMD Characteristics Symbol t1 TPTX+/TPTX– Rise Time t2 TPTX+/TPTX– Fall Time t3 TP Skew TPTX+ TPTX– 40 Description t1 t3 Figure 14. PMD Timing Preliminary Data Sheet July 2000 Min Max Unit 3 ...
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... Preliminary Data Sheet July 2000 Clock Timing (continued PPM CRYSTAL REFERENCE Z Figure 15. Connection Diagrams (Frequency References) Lucent Technologies Inc OSC PPM X OUT LU3X31T-T64 Single-Port 3 V 10/100 Ethernet Transceiver OUT GND 25 MH OSCILLATOR REFERENCE Z 5-6793(F).Cr.1 41 ...
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... LU3X31T-T64 Single-Port 3 V 10/100 Ethernet Transceiver TX Clock Timing (continued) LU3X31T-T64 DIGITAL V DD TRANSMIT V DD RECEIVE V DD CSVCC TPTX+ TPTX– TPRX+ TPRX– 301 REF100 4.64 k REF10 RECEIVE GND TRANSMIT GND 0.1 F DIGITAL GND 0.1 F GND Figure 16. Connection Diagrams (10/100BTX Operation 0 ...
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... July 2000 Outline Diagram 64-Pin TQFP Dimensions are in millimeters. 12.00 0.20 10.00 0.20 PIN #1 IDENTIFIER ZONE DETAIL A DETAIL B 0.50 TYP Lucent Technologies Inc 10.00 0.20 12.00 0. 1.40 0.05 1.60 MAX SEATING PLANE 0.08 0.05/0.15 LU3X31T-T64 Single-Port 3 V 10/100 Ethernet Transceiver TX 1.00 REF 0.25 GAGE PLANE SEATING PLANE 0.45/0.75 DETAIL A 0.106/0.200 0.19/0.27 0.08 M DETAIL B 5-7101(F) 43 ...
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... LU3X31T-T64 Single-Port 3 V 10/100 Ethernet Transceiver TX Ordering Information Device Code LU3X31T-T64 For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro E-MAIL: docmaster@micro.lucent.com N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte ...