UPD72850AGK-9EU NEC, UPD72850AGK-9EU Datasheet
UPD72850AGK-9EU
Related parts for UPD72850AGK-9EU
UPD72850AGK-9EU Summary of contents
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... The PD72850A is the 3-port physical layer LSI which complies with the P1394a draft 2.0 specifications. The PD72850A works up to 400 Mbps upgrade of NEC's PD72850. FEATURES • The Three-port Physical Layer LSI complies to IEEE P1394a draft 2.0 • Connection debounce • Arbitration enhancements • ...
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BLOCK DIAGRAM CMC PC0 PC1 PC2 PORTDIS PSEL SUS/RES LREQ LPS DIRECT SCLK LKON CTL0 CTL1 Link D0 Interface D1 I RESETB Cable CPS Power Status 2 Cable Port1 Arbitration and Control State Machine ...
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PIN CONFIGURATION (Top View) • 80-pin plastic TQFP (Fine pitch) ( mm) PC1 1 PC0 2 CMC 3 DGND 4 LPS 5 LREQ DGND 8 SCLK DGND 11 CTL0 12 ...
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... Power Class Set Input PORTDIS : Port Disable PSEL : Support Number of Port Select RESETB : Power on Reset Input RI0 : Reference Power Set, Connect Resistor 0 RI1 : Reference Power Set, Connect Resistor 1 SCLK : Link Control Output Clock SUS/RES : Suspend/Resume Function Select TpA0n : First Port Twisted Pair Cable A Negative Phase I/O ...
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... Connection Method............................................................................................................................... 15 3.1.2 LPS (Link Power Status)....................................................................................................................... 15 3.1.3 LREQ, CTL0,CTL1, and D0-D7 Pins .................................................................................................... 15 3.1.4 SCLK..................................................................................................................................................... 15 3.1.5 LKON .................................................................................................................................................... 16 3.1.6 Direct .................................................................................................................................................... 16 3.1.7 Isolation Barrier..................................................................................................................................... 16 3.2 Cable Interface ............................................................................................................................... 18 3.2.1 Connections .......................................................................................................................................... 18 3.2.2 Cable Interface Circuit .......................................................................................................................... 19 3.2.3 Unused Ports ........................................................................................................................................ 19 3.2.4 CPS....................................................................................................................................................... 19 3.3 Suspend/Resume........................................................................................................................... 19 3.3.1 Suspend/Resume On Mode (SUS/RES = “H”)...................................................................................... 19 3.3.2 Suspend/Resume Off Mode (SUS/RES = “L”) ...................................................................................... 19 3.4 PLL and Crystal Oscillation Circuit.............................................................................................. 20 3 ...
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... Extended PHY Packet .................................................................................................................... 34 5.4.1 Ping Packet........................................................................................................................................... 35 5.4.2 Remote Access Packet......................................................................................................................... 35 5.4.3 Remote Reply Packet ........................................................................................................................... 36 5.4.4 Remote Command Packet.................................................................................................................... 36 5.4.5 Remote Confirmation Packet ................................................................................................................ 37 5.4.6 Resume Packet..................................................................................................................................... 37 6. ELECTRICAL SPECIFICATIONS .......................................................................................................... 38 7. APPLICATION CIRCUIT EXAMPLE...................................................................................................... 43 7.1 IEEE1394 Interface ......................................................................................................................... 43 7.2 NEC/FFM Board Sharing ............................................................................................................... 44 8. PACKAGE DRAWING............................................................................................................................ 45 9. RECOMMENDED SOLDERING CONDITIONS ................................................................................... 46 6 Data Sheet S14452EJ1V0DS00 PD72850A ...
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... SUS/RES=“0”). 64pin 1Port(Port0) 0 2Port(Port0,1) 1 3Port(Port0-2) 0 When SUS/RES=“1”, this pin should be connected to AGND. Suspend/Resume function select 1: Suspend/Resume on (P1394a draft 2.1 compliant) 0: Suspend/Resume off (P1394a draft 1.3 compliant) Power cable status. Connect to the cable through a 390 k resistor. 0: Cable power fail 1: Cable power on ...
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... This pin status will be loaded to Pwr_class bit which allocated to PHY register 4H. IEEE1394-1995 chapter [4.3.4.1] Configuration manager capable setting. This pin status will be loaded to Contender bit which allocated to PHY register 4H. 0: Non contender 1: Contender Power on reset input. Connect to DGND through a 0.1 F capacitor. 0: Reset 1: Normal Data Sheet S14452EJ1V0DS00 PD72850A ...
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... Third port twisted pair output Resistor connection pin0 for reference current generator. Please connect to RI1 pin via 9.1 k resistor. Resistor connection pin1 for reference current generator. Please connect to RI0 pin via 9.1 k resistor. APLL filter (No need to assemble) APLL filter ground (No need to assemble) Crystal oscillator connection XI ...
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PHY REGISTERS 2.1 Complete Structure for PHY Registers Figure 2-1. Complete Structure of PHY Registers 0 1 0000 0001 RHB IBR 0010 Extended (7) 0011 Max_speed 0100 Link_active Contender 0101 Resume_int ISBR 0110 0111 Page_select 1000 1001 1010 1011 ...
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Field Size R/W Reset value Physical_ID 6 R 000000 RHB 1 R/W 0 IBR 1 R/W 0 Gap_count 6 R/W 111111 Extended 3 R 111 Total_ports 4 R 0011 Max_speed 3 R 010 ...
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... Set to 1 when the Int_Enable bit in the register map of each port is 1 and there is a change in the ports connected, Bias, Disabled and Fault bits. Set to 1 when the Resume_int bit is 1 and any one port does resume. Writing 1 to this bit clears ...
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... Shows the maximum data transfer rate of the node connected to this port. 000: 100 Mbps 001: 200 Mbps 010: 400 Mbps 0 The Port_event is set change the Connected, Bias, Disable, and Fault bits. 0 Set error occurs during Suspend/Resume. Writing 1 to this bit clears ...
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... Vendor_ID 24 R 00004CH Product_ID 24 R Reserved - R 000… 14 Figure 2-3. Vendor ID Page Compliance_level Reserved Vendor_ID Product_ID Table 2-3. Bit Field Description Description According to IEEE P1394a. Company ID Code value, NEC IEEE OUI. Product code. Reserved. Read as 0. Data Sheet S14452EJ1V0DS00 PD72850A ...
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... Link Clamping to GND connects through isolation barrier to Link. The isolation barrier connection circuit is described in 3.1.7 Isolation Barrier. 3.1.2 LPS (Link Power Status) LPS is a function to monitor the On/Off status of the Link power supply. After 1.2 sec or more, LPS is Low, the PHY/Link is reset and D and CTL are output Low (when the isolation barrier is Hi-Z) ...
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... The PD72850A uses the isolation barrier to couple the AC between the PHY/Link interface to overcome the ground difference problem. Connecting the Direct pin to Low enables the digital differential circuit of the PD72850A. The differential circuit propagates only the change in the signal; the interface will be driven only during transitions ...
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Figure 3-3. Isolation Barrier Circuits (a) CTL0,CTL1, D0-Dn Isolation Barrier Circuit Required when LinkV LinkV Link 100 0.001 F 0.001 300 ...
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... 0.01 F 5.1 k Data Sheet S14452EJ1V0DS00 PD72850A Driver Receiver + - Arbitration Comparators + - + - Connection Detection Comparator + - Driver Receiver + - Arbitration Comparators + - + - ...
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... One is when the receipt of a remote command packet that sets the initiate suspend command. After that, the PHY transmits a remote confirmation packet with the ok bit set, subsequently signals TX_SUSPEND to the connected peer PHY with the port which specified by the port field in the remote command packet, and then the PHY port transitions to the suspended state ...
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... RESETB Connect an external capacitor of 0.1 F between the pins RESETB and GND. If the voltage drops below reset pulse is generated. All of the circuits are initialized, including the contents of the PHY register. 3.7 RI1, RI0 Connect an external resistor of 9 limit the LSI’ ...
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... SCLK to Link stops and it outputs Low (When the isolation barrier is Hi-Z). Parameter LPS = Low propagation delay (with isolation barrier) LPS = High propagation delay (with isolation barrier) Reset active Disable active Setup time when using isolation barrier Figure 4-1. LPS Waveform when Connected to Isolation Barrier Table 4-1. LPS Timing Parameters Symbol t LPSL t LPSH ...
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Figure 4-2. PHY/Link Interface Reset and Disable D, CTL, LREQ LPS LPS (with isolation barrier) SCLK D, CTL, LREQ LPS LPS (with isolation barrier) SCLK 4.2 Link-on Indication When the power supply of Link is off (LPS is Low and ...
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... Table 4-4. CTL Controls Link Content Link completes the packet transmission and releases the PHY/Link interface. 1) Link transmits Hold until the data is ready for transmission. 2) Link transmits the interface connect packet. Link transmits the data to PHY. Not used. Figure 4-3. LREQ and CTL Timing ...
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LREQ format • Bus Request Bit Type 0 start 1-3 request 4-6 speed 7 stop • PHY Register Read Request Table 4-6. Read Request Register Format Bit Type 0 start 1-3 request 4-7 access address 8 stop • PHY ...
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Acceleration Controller Table 4-8. Acceleration Controller Request Format Bit Type 0 start 1-3 request 4 access address 5 stop Bit Type 000 ImmReq 001 IsoReq 010 PriReq 011 FairReq 100 RdReg 101 WrReg 110 AccCtrl 111 - For the ...
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... Link issues the request after completing the decoding of Destination_ID, when the acknowledge packet is ready. After the packet is received necessary to transmit the first bit of the request within four cycles. correct If the isochronous packet transmission is prepared for the isochronous period issued ...
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Table 4-11. PHY Operation Before LREQ Request to the CTL Function Changes Request State of CTL LREQ was issued Fair, Priority Receive Grant Idle, Status Immediate Grant Receive Idle, Status Isochronous Transmit Idle (driven by Link) Grant ...
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... PD72850A does not require setting the Acceleration Control during isochronous transmit to enable the isochronous request fly-by acceleration not necessary to issue Acceleration Control request when the cycle master is absent from the serial bus. These enhancements are enabled if the Enab_accel bit in the PHY register is set. The PD72850A supports Variable Acceleration controlled by the Acceleration Control during power-on reset ...
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Transmit Status Pin D0,D1 of the PD72850A transmits status information to the Link. Status is asserted to CTL while transmitting Status. The status transmission is interrupted if the serial bus receives a packet which contains states other than status ...
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Transmit The PD72850A arbitrates the serial bus using Link’s LREQ. • When the PD72850A acquires the bus, a Grant period of 1 SCLK is executed to CTL0,CTL1. After that, an Idle period of 1 SCLK cycle is executed. • ...
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... The following limitations exist though Link can transmit the concatenated packet with a different transfer rate. Link cannot transmit other than S100 connecting packets after S100 (concatenated) packets have been transmitted. A new request to transmit must be issued in order to transmit S100 packets at a transfer rate of S200 or more. ...
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Figure 4-8. Link Cancel Timing (After Hold) PHY CTL0,CTL1 PHY D0-D7 Link CTL0,CTL1 Link D0-D7 4.8 Receive This section shows the operation when the packet is received from the serial bus. • When the PD72850A detects DATA_PREFIX on the serial ...
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... The node consumes 3W maximum power. 110: The node consumes 3W maximum power. At least 3W are necessary to enable Link. 111: The node consumes 3W maximum power. At least 7W are necessary to enable Link shows that the node issued Bus Reset and the bus was reset. ...
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Link-on Packet The PD72850A outputs the Link-on signal of 6.144 MHz from the pin LKON when receiving the Link-on packet. 01 phy_ID 0000 Field phy_ID Physical_ID of the destination of the Link-on packet 5.3 PHY Configuration Packet Use the ...
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Ping Packet When the PD72850A receives the Ping packet, it will transmit the Self_ID packet within the RESPONSE_TIME. 00 phy_ID 00 Field phy_ID Physical ID of the destination node of the Ping packet type Indicates that there is a ...
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Remote Reply Packet The PD72850A transmits the value in the register by using the Remote reply packet as a response to the Remote access packet. 00 phy_ID 00 Field phy_ID Physical ID of the node (Node’s original packet transmit) ...
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... Specifies the command value with the Remote command packet 5.4.6 Resume Packet When the PD72850A receives the Resume packet, all of the ports that were suspended resume the connection. The Resume packet does the broadcast. 00 phy_ID 00 Field ...
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ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Parameter Power supply voltage Input voltage Output voltage Storage temperature Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are ...
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DC Characteristics Common Parameter Supply current PHY/Link Interface Parameter High-level output voltage (Undifferentiated) High-level output voltage (Differentiated) Low-level output voltage (Undifferentiated) Low-level output voltage (Differentiated) High-level input voltage (Undifferentiated) Low-level input voltage (Undifferentiated) Input rising threshold voltage (LPS) Input falling ...
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AC Characteristics PHY/Link Interface Parameter D, CTL, LREQ setup time D, CTL, LREQ hold time D, CTL output timing SCLK cycle time SCLK high level time SCLK low level time LKON cycle time Link Interface Timing (SCLK, LKON) SCLK t ...
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Link Interface Timing (CTL, D) SCLK t D Transmit CTL0,CTL1 t D D0-D7 Receive CTL0,CTL1 D0-D7 Link Interface Timing (LREQ) SCLK LREQ Data Sheet ...
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Cable Interface Parameter TpA, TpB transfer jitter TpA strobe, TpB data transfer TPA, TPB rise time/fall time 42 Symbol Condition MIN. t Between TpA and TpB JITTER t Between TpA and TpB SKEW t /t 10% to 90%, via 55 ...
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APPLICATION CIRCUIT EXAMPLE 7.1 IEEE1394 Interface Note Note AGND 61 AGND PORTDIS 64 AGND 65 PSEL 0.1 F AGND 68 AGND 69 AGND 70 SUS/RES AGND 72 AV ...
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... NEC/FFM Board Sharing 0 MD8405E 1 220 pF 0 PD72850A AGND ...
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PACKAGE DRAWING 80-PIN PLASTIC TQFP (FINE PITCH) (12x12 NOTE Each lead centerline is located within 0. its true position (T.P.) at maximum material condition ...
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... The PD72850A should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 9-1. Surface Mounting Type Soldering Conditions ...
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... HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry ...
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... Sony Corporation. The export of this product from Japan is prohibited without governmental license. To export or re-export this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version ...