UPD75P3036GC-3B9 NEC, UPD75P3036GC-3B9 Datasheet
UPD75P3036GC-3B9
Related parts for UPD75P3036GC-3B9
UPD75P3036GC-3B9 Summary of contents
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... WQFN Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. In this document, the term PROM is used in parts common to one-time PROM versions and EPROM versions. The information in this document is subject to change without notice. ...
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Functional Outline Parameter Instruction execution time • 0.95, 1.91, 3.81, 15.3 s (main system clock: during 4.19-MHz operation) • 0.67, 1.33, 2.67, 10.7 s (main system clock: during 6.0-MHz operation) • 122 s (subsystem clock: during 32.768-kHz operation) Internal memory ...
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... Port Pins ................................................................................................................................................ 7 3.2 Non-port Pins ........................................................................................................................................ 9 3.3 Pin Input/Output Circuits ...................................................................................................................... 11 3.4 Recommended Connection of Unused Pins ...................................................................................... MODE AND Mk II MODE SELECTION FUNCTION .............................................................. 15 4.1 Difference between Mk I Mode and Mk II Mode .................................................................................. 15 4.2 Setting of Stack Bank Selection Register (SBS) ................................................................................ 16 5. DIFFERENCES BETWEEN PD75P3036 AND PD753036 ........................................................ 17 6. PROGRAM COUNTER (PC) AND MEMORY MAP ....................................................................... 18 6 ...
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... S23 9 S22 10 S21 11 S20 12 S19 13 S18 14 S17 15 S16 16 S15 17 S14 18 S13 19 20 S12 Caution Connect the V pin directly mm ...
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PIN IDENTIFICATIONS P00 to P03 : Port0 P10 to P13 : Port1 P20 to P23 : Port2 P30 to P33 : Port3 P40 to P43 : Port4 P50 to P53 : Port5 P60 to P63 : Port6 P70 to P73 ...
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BLOCK DIAGRAM 8-BIT TI0/P13 TIMER/EVENT PTO0/P20 COUNTER #0 INTT0 TOUT0 AN0-AN5 AN6/P82 8 A/D AN7/P83 CONVERTER AV REF AV SS BASIC INTERVAL TIMER/ WATCHDOG TIMER INTBT INTT1 TI1/P80 8-BIT CASCADED TIMER/EVENT PTO1/P21 16-BIT COUNTER #1 TIMER/ TI2/P81 8-BIT EVENT ...
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... Connection of an on-chip pull-up resistor can be specified in 4-bit units by software. This is a programmable 4-bit I/O port (PORT3). Input and output can be specified in bit units. Connection of an on-chip pull-up resistor can be specified in 4-bit units by software. This is an N-ch open-drain 4-bit I/O port (PORT4). When set to open-drain, voltage ...
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... Notes 1. Circuit types enclosed in brackets indicate Schmitt trigger input BP0 through BP7 select V However, the output levels change depending on the external circuit of BP0 through BP7 and V * Example Because BP0 through BP7 are mutually connected inside the PD75P3036, the output levels of BP0 through BP7 are determined LC1 ...
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... Rising edge detection test input Asynchonous Parallel falling edge detection test input Parallel falling edge detection test input Ceramic/crystal oscillation circuit connection for main system clock. If using an external clock, input to X1 and input inverted phase to X2. Crystal oscillation circuit connection for subsystem clock. ...
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Non-port Pins (2/2) Pin name I/O Alternate function S12 to S23 Output — S24 to S31 Output BP0 to BP7 COM0 to COM3 Output — — — LC0 LC2 BIAS Output — Note 2 LCDCL Output ...
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Pin Input/Output Circuits The input/output circuits for the PD75P3036’s pins are shown in schematic form below. TYPE P-ch IN N-ch CMOS standard input buffer TYPE B IN Schmitt trigger input with hysteresis characteristics. TYPE B-C V ...
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TYPE F-A P.U.R. enable data Type D output disable Type B P.U.R. : Pull-Up Resistor TYPE F-B P.U.R. enable output V disable (P) data output disable output disable (N) P.U.R. : Pull-Up Resistor * TYPE G-A V LC0 V LC1 ...
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TYPE M-E data N-ch (+13 V output withstand disable V voltage) DD input P-ch instruction Note P.U.R. Voltage limitation circuit Note The pull-up resistor operates only when an input instruction is executed (current flows from V the pin when ...
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... Connect Input status : connect via a resistor individually Output status: open Connect Input status : connect via a resistor individually Output status: open Open Connect Connect to V only when are all not used. ...
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Mk I MODE AND Mk II MODE SELECTION FUNCTION Setting a stack bank selection (SBS) register for the PD75P3036 enables the program memory to be switched between Mk I mode and Mk II mode. This function is applicable when ...
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Setting of Stack Bank Selection Register (SBS) Use the stack bank selection register to switch between Mk I mode and Mk II mode. Figure 4-1 shows the format for doing this. The stack bank selection register is set using ...
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DIFFERENCES BETWEEN PD75P3036 AND PD753036 The PD75P3036 replaces the internal mask ROM in the program memory of the PD753036 with a one-time PROM or EPROM. The PD75P3036’ mode supports the Mk I mode in the PD753036 and ...
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PROGRAM COUNTER (PC) AND MEMORY MAP 6.1 Program Counter (PC) ... 14 bits This is a 14-bit binary counter that stores program memory address data. Figure 6-1. Configuration of Program Counter PC13 PC12 PC11 PC10 PC9 6.2 Program Memory ...
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Figure 6-2 shows the addressing ranges for the program memory, branch instruction and the subroutine call instruction 0000H MBE RBE Internal reset start address (upper 6 bits) Internal reset start address (lower 8 bits) 0002H MBE RBE ...
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Data Memory (RAM) ... 768 x 4 bits Figure 6-3 shows the data memory configuration. Data memory consists of a data area and a peripheral hardware area. The data area consists of 768 x 4-bit static RAM. General-purpose register ...
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INSTRUCTION SET (1) Representation and coding formats for operands In the instruction’s operand area, use the following coding format to describe operands corresponding to the instruction’s operand representations (for further description, see the RA75X Assembler Package User’s Manual—Language (EEU-1363)). ...
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Operation legend register; 4-bit accumulator register register register register register register register XA : Register ...
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Description of symbols used in addressing area MB = MBE • MBS *1 MBS = 0- MBE = (000H-07FH (F80H-FFFH) *3 MBE = ...
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Instruction Mnemonic Operand group Transfer MOV A, #n4 reg1, #n4 XA, #n8 HL, #n8 rp2, #n8 A, @HL A, @HL+ A, @HL– A, @rpa1 XA, @HL @HL, A @HL mem XA, mem mem, A mem reg1 ...
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Instruction Mnemonic Operand group Bit transfer MOV1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit fmem.bit, CY pmem.@L, CY @H+mem.bit, CY Arithmetic/ ADDS A, #n4 logical XA, #n8 operation A, @HL XA, rp’ rp’1, XA ADDC A, @HL XA, rp’ rp’1, XA ...
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Instruction Mnemonic Operand group Comparison SKE reg, #n4 @HL, #n4 A, @HL XA, @HL A, reg XA, rp’ Carry flag SET1 CY manipulation CLR1 CY SKT CY NOT1 CY Memory bit SET1 mem.bit manipulation fmem.bit pmem.@L @H+mem.bit CLR1 mem.bit fmem.bit ...
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Instruction Mnemonic Operand group Branch BR Note 1 addr addr1 !addr $addr $addr1 PCDE PCXA BCDE BCXA Note 1 BRA !addr1 BRCB !caddr Notes 1. The above operations in the double boxes can be performed only in the Mk II ...
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Instruction Mnemonic Operand group Subroutine CALLA Note !addr1 stack control CALL Note !addr CALLF Note !faddr RET Note Note RETS RETI Note Note The above operations in the double boxes can be performed only in the Mk II mode. The ...
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Instruction Mnemonic Operand group Subroutine PUSH rp stack control BS POP rp BS Interrupt EI control IEXXX DI IEXXX I/O IN Note 1 A, PORTn XA, PORTn Note 1 OUT PORTn, A PORTn, XA CPU control HALT STOP NOP Special ...
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... D4/P50 to D7/P53 (upper 4 bits Caution Pins not used for program memory write/verify should be connected to V 8.1 Operation Modes for Program Memory Write/Verify When + applied to the V pin and +12 the V DD mode. The following operation modes can be specified by setting pins MD0 to MD3 as shown below. ...
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Program Memory Write Procedure Program memory can be written at high speed using the following procedure. (1) Pull unused pins (2) Supply the V and V DD (3) Wait 10 s. (4) ...
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Program Memory Read Procedure The PD75P3036 can read program memory contents using the following procedure. (1) Pull unused pins to V through resistors. Set the X1 pin low. SS (2) Supply the V and V ...
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... Due to its structure, the one-time PROM versions ( PD75P3036GC-3B9, PD75P3036GK-BE9) cannot be fully tested before shipment by NEC. Therefore, NEC recommends that after the required data is written and the PROM is stored under the temperature and time conditions shown below, the PROM should be verified via a screening. ...
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ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings ( Parameter Symbol Supply voltage V DD PROM supply voltage V PP Input voltage Output voltage V O High-level output current I OH Low-level output ...
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Main System Clock Oscillation Circuit Characteristics (T Recommended Resonator Constants Ceramic resonator Crystal resonator External clock X1 X2 Notes 1. The oscillation frequency and X1 input frequency shown ...
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Subsystem Clock Oscillation Circuit Characteristics (T Recommended Resonator Constants Crystal resonator XT1 XT2 External clock XT1 XT2 Notes 1. The oscillation frequency shown above indicate characteristics of the oscillation circuit only. For the instruction execution ...
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DC Characteristics (T = – Parameter Symbol Low-level output I Per pin OL current Total of all pins High-level input V Ports 2, 3, P82, P83 IH1 voltage V Ports P80, ...
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DC Characteristics (T = – Parameter Symbol LCD drive voltage V VAC0 = 0 LCD VAC0 = 1 Note 1 VAC current I VAC0 = 1, V VAC LCD output voltage 1.0 ...
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... RESET low-level width t RSL Notes 1. The cycle time of the CPU clock ( ) is determined by the oscillation frequency of the connected resonator (and ex- ternal clock), the system clock control register (SCC), and processor clock control register (PCC). The figure on the right shows the sup- ply voltage V vs ...
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Serial transfer operation 2-wire and 3-wire serial I/O modes (SCK ··· internal clock output): (T Parameter Symbol SCK cycle time t KCY1 SCK high-, low-level widths t , KL1 t KH1 Note 1 SI setup time (to SCK ) t ...
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SBI mode (SCK ··· internal clock output (master)): (T Parameter Symbol SCK cycle time t KCY3 SCK high-, low-level widths t , KL3 t KH3 SB0, 1 setup time t SIK3 (to SCK ) SB0, 1 hold time (from SCK ...
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A/D Converter Characteristics (T = – Parameter Symbol Resolution Absolute accuracy Note 1 Conversion time t CONV Sampling time t SAMP Analog input voltage V IAN Analog input impedance current I REF ...
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AC timing test points (except X1 and XT1 inputs) V (MIN (MAX (MIN (MAX.) OL Clock timing X1 input XT1 input TI0, TI1, TI2 timing TI0, TI1, TI2 V (MIN (MAX.) IL ...
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Serial transfer timing 3-wire serial I/O mode SCK 2-wire serial I/O mode SCK SB0 KSO1 KCY1 KL1, 2 KH1 SIK1, 2 KSI1, 2 Input data KSO1, ...
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Serial transfer timing Bus release signal transfer SCK t t KSB SBL SB0, 1 Command signal transfer SCK t KSB SB0, 1 Interrupt input timing INT0 KR0-7 RESET input timing RESET t KCY3 KL3, ...
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Data retention characteristics of data memory in STOP mode and at low supply voltage (T = – Parameter Symbol Release signal setup time t SREL Oscillation stabilization t WAIT Note 1 wait time Notes 1. The ...
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... HAD MD3 hold time (from MD0 ) t M3HR MD3 Data output float delay time t DFR Notes 1. Symbol of corresponding PD27C256A 2. The internal address signal is incremented the 4th rise of the X1 input, and is not connected to a pin ˚ 6.0 0. Conditions MIN. ...
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Program Memory Write Timing t VPS VDS D0/P40-D3/P43 Data Input D4/P50-D7/P53 MD0 t PW MD1 PCR ...
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CHARACTERISTIC CURVES (FOR REFERENCE ONLY 5.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 0 1 (main system clock: 6.0-MHz crystal resonator Supply voltage V (V) DD ...
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I vs. V (main system clock: 4.19-MHz crystal resonator 5.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 PCC = 0011 PCC = 0010 PCC = 0001 PCC = 0000 Main system clock HALT ...
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PACKAGE DRAWINGS 80 PIN PLASTIC QFP (14 14 NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition ...
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PIN PLASTIC TQFP (FINE PITCH NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition ...
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PIN CERAMIC WQFN * NOTE Each lead centerline is located within 0.06 mm (0.003 inch) of its true position (T.P.) at maximum material condition ITEM MILLIMETERS 14.0 ± 0.2 ...
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... Solder the PD75P3036 under the following recommended conditions. For the details on the recommended soldering conditions, refer to Information Document Semiconductor Device Mounting Technology Manual (C10535E). For the soldering methods and conditions other than those recommended, consult NEC. Table 15-1. Soldering Conditions of Surface Mount Type (1) PD75P3036GC-3B9: 80-pin plastic QFP (14 14 mm) ...
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APPENDIX A. FUNCTION LIST OF PD75336, 753036, AND 75P3036 ROM (bytes) 16256 Mask ROM RAM (x 4 bits) 768 mode selection function No Instruction set 75X High-End I/O ports Total 44 CMOS input 8 CMOS I/O ...
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APPENDIX B. DEVELOPMENT TOOLS The following development tools have been provided for system development using the PD75P3036. Use the common relocatable assembler for the series together with the device file according to the model. RA75X relocatable assembler Host machine PC-9800 ...
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... This is a PROM programmer adapter for the PD75P3036GC used by connecting to a PG-1500. This is a PROM programmer adapter for the PD75P3036GK used by connecting to a PG-1500. This is a PROM programmer adapter for the PD75P3036KK-T used by connecting to a PG- 1500. Connects PG-1500 to host machine with serial and parallel interface and controls PG-1500 on host machine ...
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... When being used connected with the IE-75000-R or IE-75001-R and the IE-75300-R-EM. EV-9500GK-80 It includes an 80-pin conversion adapter (EV-9500GK-80) to facilitate connections with target system. Software IE control program This program can control the IE-75000-R or IE-75001 host machine when connected to the IE-75000-R or IE-75001-R via an RS-232-C and Centronics interface. Host machine PC-9800 Series * IBM PC/AT or compatible Notes 1 ...
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OS for IBM PCs The following operating systems for the IBM PC are supported Caution Ver. 5.0 or later includes a task swapping function, but this software is not able to use that function. OS Version TM PC ...
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... Document IC Package Manual Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Electrostatic Discharge (ESD) Test Guide to Quality Assurance for Semiconductor Devices Microcomputer – Related Product Guide – Third Party Products – Caution The related documents listed above are subject to change without notice. Be sure to use the latest documents for designing, etc ...
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PD75P3036 61 ...
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... HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry ...
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... Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • ...
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... The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. ...