UPD7225G00 NEC, UPD7225G00 Datasheet

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UPD7225G00

Manufacturer Part Number
UPD7225G00
Description
Programmable LCD controller/driver
Manufacturer
NEC
Datasheet

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UPD7225G00
Manufacturer:
NEC
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Document No. S14308EJ6V0DS00 (6th edition)
Date Published June 1999 N CP (K)
Printed in Japan
(O.D. No. IC-1555)
serially interfaced with the CPU in a microcomputer and can directly drive 2, 3, or 4-time division LCD. The PD7225
contains a segment decoder which can generate specific segment patterns. In addition, the PD7225 can be used to
control on/off (blinking) operation of a display.
FEATURES
• Can directly drive LCD
• Programmable time-division multiplexing
• Number of digits displayed
• Bias method
• Segment decoder output
• Blinking operation
• Multi-chip configuration possible
• 8-bit serials interface
• CMOS
• Single power supply
ORDERING INFORMATION
PD7225G00
PD7225G01
PD7225GB-3B7
PD7225GC-AB6
Static, 1/2, 1/3
75X series and 78K series compatible
The PD7225 is a software-programmable LCD (Liquid Crystal Display) controller/driver. The PD7225 can be
Part Number
Static drive
Divide-by-2, 3, or -4 time division multiplexing
7-segment
Divide-by-4
Divide-by-3
Divide-by-2
Static................................................. 4 digits
14-segment
Divide-by-4
7-segment : Numeric characters 0 to 9, six symbols
14-segment : 36 alphanumeric characters, 13 symbols
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
PROGRAMMABLE LCD CONTROLLER/DRIVER
time division ............... 16 digits
time division ............... 10 2/3 digits
time division ............... 8 digits
time division ............... 8 digits
52-pin plastic QFP (14
52-pin plastic QFP (straight) (
56-pin plastic QFP (10
52-pin plastic QFP (14
The mark
DATA SHEET
14 mm)
10 mm)
14 mm)
14 mm)
shows major revised points.
Package
MOS INTEGRATED CIRCUIT
PD7225
©
1986, 1999

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UPD7225G00 Summary of contents

Page 1

... QFP (14 The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S14308EJ6V0DS00 (6th edition) (O ...

Page 2

... CL1 : External Resistor 1 (External Clock) CL2 : External Resistor 2 RESET : Reset Power Supply For LCD Drive LC1 LC3 V : Power Supply Ground Internally Connected Data Sheet S14308EJ6V0DS00 PD7225 39 S19 38 S18 37 S17 S16 36 S15 35 34 S14 S13 31 ...

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... S20 1 S21 2 S22 3 S23 4 S24 5 S25 6 S26 7 S27 8 S28 9 S29 10 S30 11 S31 12 CL1 Note IC Pin must be connected mm left unconnected. DD Data Sheet S14308EJ6V0DS00 PD7225 ...

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BLOCK DIAGRAM S31 V LC1 V LC2 LCD TIMING V CONTROL LC3 /SYNC CL1 SEGMENT OSC CL2 /RESET /CS WRITE C, /D CONTROL /BUSY 4 S30 S29 LCD DRIVER DISPLAY DATA LATCH DATA MEMORY DECODER COMMAND/DATA ...

Page 5

... LCD. 1.6 /SYNC (SYNChronous) Input/Output The /SYNC pin is used to make a wired-OR connection when the common pins are shared or when blinking operation is synchronized in a multi-chip configuration. When the PD7225 is reset (/RESET = 0), the /SYNC pin outputs the clock frequency (f Figure 1-1), and synchronizes the system clock (f display timing of each PD7225 is synchronized with the common drive signal timing shown in Figure 1-2 ...

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... S0-S31 (Segment) Output These pins output segment drive signals. 1.9 COM0-COM3 (COMmon) These pins output common drive signals. 1.10 CL1, CL2 (Clock) A resistor is connected across these pins for internal clock generation. When inputting an external clock, use the CL1 pin for input. 1. LC1 ...

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V DD Positive power supply pin. Either pin 7 or pin 33 can be used. 1. GND pin. Data Sheet S14308EJ6V0DS00 PD7225 7 ...

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INTERNAL SYSTEM CONFIGURATION 2.1 Serial Interface The serial interface consists of an 8-bit serial register and a 3-bit SCK counter. The serial register clocks in the serial data from the SI pin at the rising edge of /SCK. At ...

Page 9

... When displaying the output of the segment decoder (display data) on the LCD, use an LCD configured as shown in Figure 2-1 or Figure 2-2. If another type of LCD is used, the displayed pattern will be different. When configuring the LCD for divide-by-3 time division mode, connect as follows: SEGn + 1 SEGn + ...

Page 10

... When configuring the LCD for divide-by-4 time division mode, connect as follows: SEGn SEGn + COM0 COM2 SEGn : SEGn + COM0 : a, f COM1 : b, g COM2 : c, e COM3 : d, DP Data Sheet S14308EJ6V0DS00 PD7225 COM1 COM3 ...

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... The 14-segment type LCD can be used only in the divide-by-4 time division mode. For the 14-segment LCD type, connect segments and commons as follows: SEGn + 3 SEGn + 2 SEGn + 1 SEGn The following shows the input data and display pattern, and the configuration of the display data which is automatically written into the data memory ...

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Data memory Divide-by-3 Data Display time division (HEX) pattern Figure 2-3. ...

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Figure 2-4. 14-Segment LCD A Data memory Display Display Data pattern pattern (HEX) N+3 N+2 N ...

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Data Memory/Data Pointer The data memory is a memory which stores display data (32 immediate data, etc., is written to the data memory Bit the data memory, either data from the serial register ...

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Divide-by-3 time division The contents of the 8 bits of the serial register of the segment decoder output (8 bits) are written to bits 0, 1, and 2 of each address. In this case, 0 will be automatically written ...

Page 16

All bits of each address are effective. After the data is written, the data pointer points to address The segment decoder output written to the data memory corresponds to segments ( DP) shown in Figure ...

Page 17

... PD7225 when configured in a multi- chip configuration multi-chip configuration, the common signal can be used in common or blinking operation can be synchronized by making a wired-OR connection with the /SYNC pin of each PD7225. 4-bit segment driver. Each bit of the display data latch Data Sheet S14308EJ6V0DS00 ...

Page 18

FRAME FREQUENCY AND BLINKING FREQUENCY SETTING 3.1 Frame Frequency Setting The frame frequency is set according to M1, M0 (number of time-divisions setting), and F1, F0 (frequency division ratio) as indicated in the figure below. Figure 3-1. Frame Frequency ...

Page 19

LCD DRIVE POWER SUPPLY PIN VOLTAGE SETTING The bias method for setting the LCD drive power supply pin allows a different voltage to be supplied to each pin. Static 1/2 bias 1/3 bias Remark V : LCD voltage LCD ...

Page 20

Divide-by-3, -4 time division (1/3 bias LC1 PD7225 LC2 LC3 LCD 3(V DD GND Data Sheet S14308EJ6V0DS00 ...

Page 21

... CLOCK CIRCUIT The clock oscillator can be configured by connecting a resistor (R) across the CL1 and CL2 clock pins. When using the external clock, CL1 can be used to input the external clock (CL2: Open). Figure 5-1. External Circuit for Clock Oscillation Pins PD7225 OSC LCD timing ...

Page 22

RESET FUNCTION When a low level of 12 clock cycles or more is input to the /RESET pin, the PD7225 will be reset to the following conditions: • This condition is the same as when M2 • Display data ...

Page 23

... If it becomes necessary to interrupt serial data transfer when transferring two or more bytes of data due to an interrupt for the CPU interrupt, execute the PAUSE TRANSFER command after checking that the byte has been transferred, then set /CS to high ...

Page 24

Figure 7-2. Inputting 5 Bytes Successively Serial data Byte 1 /CS /BUSY 24 Byte 2 Byte 3 Byte 4 Data Sheet S14308EJ6V0DS00 PD7225 Byte 5 ...

Page 25

COMMAND 8.1 MODE SET This command sets the number of time divisions for the LCD display static drive or the time-division drive, bias method, and frame frequency. (1) M1 and M0 ...

Page 26

... In addition, the data pointer is not cleared at the first rising edge of the /CS pin (refer to 2.5 Data Memory/Data Pointer). This command is used when it becomes necessary to set the /CS pin to high due to an interrupt for the CPU in the middle of serial data input operation. ...

Page 27

DISPLAY OFF When this command is executed, the relationship of all common drive signals and segment drive signals enters the non-select state result, the display is turned off. Transferring display data from ...

Page 28

AND DATA MEMORY This command ANDs the contents of the data memory addressed by the data pointer and immediate data D3-D0, and stores the result to the data memory, then increments ...

Page 29

DISPLAY OUTPUT The following describes the serial data organization, display data organization in the data memory, segment drive signal, and common drive signal when the display is active in the static and divide-by-2, -3, -4 time division modes. 9.1 ...

Page 30

Segment and common drive signals SEGn, SEGn + 2 SEGn + 1, SEGn + 7 COM0 COM0 30 SEGn + 6 COM0 SEGn SEGn + 1 Data Sheet S14308EJ6V0DS00 PD7225 V LC0 V LC3 V LC0 V LC3 V ...

Page 31

Divide-by-2 Time Division When displaying just the digit “6” in the divide-by-2 time division mode: (1) Serial data organization: F5 (2) Display data organization in the data memory Bit (3) Power supply (1/2 bias LC0 DD ...

Page 32

Segment and common drive signals SEGn SEGn + 1 SEGn + 2 SEGn + 3 COM0 COM1 COM0 SEGn + 3 COM1 SEGn Data Sheet S14308EJ6V0DS00 PD7225 V ...

Page 33

Divide-by-3 Time Division When displaying the digit “6.” in the divide-by-3 time division mode: (1) Serial data organization • Without segment decoder: FE • With segment decoder : 06 (However, the floating point is set to “1” by command.) ...

Page 34

Segment and common drive signals SEGn SEGn + 1 SEGn + 2 COM0 COM1 COM2 COM1 SEGn + 2 COM2 SEGn + Data Sheet S14308EJ6V0DS00 PD7225 V ...

Page 35

Divide-by-4 Time Division When displaying the digit “6.” in the divide-by-4 time division mode: (1) Serial data organization • Without segment decoder: FD • With segment decoder : 06 (However, the floating point is set to “1” by command.) ...

Page 36

Segment and common drive signals SEGn SEGn + 1 COM0 COM3 COM1 COM2 COM0 SEGn + 1 COM1 SEGn Data Sheet S14308EJ6V0DS00 PD7225 V LC0 V ...

Page 37

ELECTRICAL CHARACTERISTICS Absolute Maximum Rating ( Item Symbol Power supply voltage V DD Input voltage V Output voltage V O Operating ambient temperature T A Storage temperature T stg Caution If the absolute maximum rating ...

Page 38

DC Characteristics ( + Item Symbol High level input voltage V IH Low level input voltage V IL High level output voltage V OH Low level output voltage V OL1 V OL2 Output short-circuit ...

Page 39

AC Characteristics ( + Item Symbol Operating frequency f C Oscillation frequency f OSC High level clock pulse width t WHC Low level clock pulse width t WLC /SCK frequency t CYK High level ...

Page 40

AC Characteristics ( + Item Symbol Operating frequency f C Oscillation frequency f OSC High level clock pulse width t WHC Low level clock pulse width t WLC /SCK frequency t CYK High level ...

Page 41

Timing Wave-Form CL1 t DCSB /CS Note 1 /BUSY 0 HBK Note 2 /SCK Note Notes 1. V 0.5 V when 0.8 V when V = 2.7 ...

Page 42

Typical Characteristic Curve ( External resistor and oscillation frequency 200 100 100 200 External resistor R (k ohms) Power supply voltage and operating current CL2 ...

Page 43

PACKAGE DRAWINGS PD7225G00 52 PIN PLASTIC QFP (14x14 NOTES 1. Controlling dimension 2. Each lead centerline is located within 0. its true position (T.P.) at maximum ...

Page 44

PD7225G01 52PIN PLASTIC QFP (STRAIGHT) ( 14) NOTE Each lead centerline is located within 0.20 mm (0.008 inch) of its true position (T.P.) at maximum material condition ...

Page 45

PD7225GB-3B7 56 PIN PLASTIC QFP (10 10 NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition ...

Page 46

PD7225GC-AB6 52 PIN PLASTIC QFP (14 14 NOTE Each lead centerline is located within 0.20 mm (0.008 inch) of its true position (T.P.) at maximum material condition ...

Page 47

... Preheating temperature: 120 C MAX. (Package surface) Caution Do not use two or more soldering methods in combination (except the partial heating method). Reference Documents NEC Semiconductor Device Reliability / Quality Control System (C10983E) Quality Grades to NEC’s Semiconductor Devices (C11531E) Semiconductor Device Mounting Technology Manual (C10535E) 14 mm) ...

Page 48

Data Sheet S14308EJ6V0DS00 PD7225 ...

Page 49

Data Sheet S14308EJ6V0DS00 PD7225 49 ...

Page 50

Data Sheet S14308EJ6V0DS00 PD7225 ...

Page 51

... HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry ...

Page 52

... Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance ...

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