MACH210A-7VC Advanced Micro Devices, MACH210A-7VC Datasheet

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MACH210A-7VC

Manufacturer Part Number
MACH210A-7VC
Description
High-density EE CMOS programmable logic, 7ns, input pull-up resistors
Manufacturer
Advanced Micro Devices
Datasheet

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MACH210A-7/10/12
MACH210-12/15/20
MACH210AQ-12/15/20
High-Density EE CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
GENERAL DESCRIPTION
The MACH210 is a member of AMD’s high-performance
EE CMOS MACH 2 device family. This device has
approximately six times the logic macrocell capability of
the popular PAL22V10 without loss of speed.
The MACH210 consists of four PAL blocks intercon-
nected by a programmable switch matrix. The four PAL
blocks are essentially “PAL22V16” structures complete
with product-term arrays and programmable macro-
cells, including additional buried macrocells. The switch
matrix connects the PAL blocks to each other and to all
input pins, providing a high degree of connectivity
between the fully-connected PAL blocks. This allows
designs to be placed and routed efficiently.
The MACH210 has two kinds of macrocell: output and
buried. The MACH210 output macrocell provides regis-
44 Pins
64 Macrocells
7.5 ns t
12 ns t
133 MHz f
38 Inputs; 210A Inputs have built-in pull-up
resistors
PD
PD
FINAL
Industrial
CNT
Commercial
COM’L: -7/10/12/15/20, Q-12/15/20
tered, latched, or combinatorial outputs with program-
mable polarity. If a registered configuration is chosen,
the register can be configured as D-type or T-type to
help reduce the number of product terms. The register
type decision can be made by the designer or by the
software. All output macrocells can be connected to an
I/O cell. If a buried macrocell is desired, the internal
feedback path from the macrocell can be used, which
frees up the I/O pin for use as an input.
The MACH210 has dedicated buried macrocells which,
in addition to the capabilities of the output macrocell,
also provide input registers or latches for use in
synchronizing signals and reducing setup time require-
ments.
Peripheral Component Interconnect (PCI)
compliant
32 Outputs
64 Flip-flops; 2 clock choices
4 “PAL22V16” blocks with buried macrocells
Pin-compatible with MACH110, MACH111,
MACH211, and MACH215
IND: -12/14/18/24
Publication# 14128
Issue Date: May 1995
Rev. I
Advanced
Devices
Amendment /0
Micro

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MACH210A-7VC Summary of contents

Page 1

... FINAL MACH210A-7/10/12 MACH210-12/15/20 MACH210AQ-12/15/20 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS 44 Pins 64 Macrocells 7 Commercial Industrial PD 133 MHz f CNT 38 Inputs; 210A Inputs have built-in pull-up resistors GENERAL DESCRIPTION The MACH210 is a member of AMD’s high-performance EE CMOS MACH 2 device family. This device has approximately six times the logic macrocell capability of the popular PAL22V10 without loss of speed ...

Page 2

AMD BLOCK DIAGRAM I/O –I I/O Cells 8 8 Macrocells Macrocells AND Logic Array and Logic Allocator AND Logic Array and Logic Allocator OE Macrocells Macrocells 8 8 ...

Page 3

CONNECTION DIAGRAM Top View I/O 5 I GND CLK I/O 8 I/O 9 I/O 10 I/O 11 Note: Pin-compatible with MACH110, MACH111, MACH211, and MACH215. PLCC ...

Page 4

AMD CONNECTION DIAGRAM Top View I/O5 I/O6 I/ GND CLK0/I2 I/O8 I/O9 I/O10 I/O11 Note: Pin-compatible with MACH111 and MACH211. PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output V = ...

Page 5

... Valid Combinations MACH210A-7 JC, MACH210A-10 VC MACH210A-12 MACH210-12 MACH210-15 MACH210-20 JC MACH210AQ-12 MACH210AQ-15 MACH210AQ-20 MACH210-7/10/12/15/20, Q-12/15/20 (Com’l) MACH 210A - Valid Combinations The Valid Combinations table lists configurations planned to be supported in volume for this device. Con- sult the local AMD sales office to confirm availability of specific valid combinations or to check on newly re- leased combinations ...

Page 6

... Macrocells, 44 Pins, Input Pull-Up Resistors SPEED - - Valid Combinations MACH210A-12 MACH210A-14 JI MACH210-14 MACH210-18 MACH210-24 6 MACH 210A - Valid Combinations The Valid Combinations table lists configurations planned to be supported in volume for this device. Con- ...

Page 7

... PAL blocks for efficient design implementation. There are two clock pins that can also be used as dedicated inputs. The MACH210A inputs and I/O pins have built-in pull-up resistors. While it is always a good design practice to tie unused pins high, the 210A pull-up resistors provide design security and stability in the event that unused pins are left disconnected ...

Page 8

... PCI Compliance The MACH210A-7/10 is fully compliant with the PCI Local Bus Specification published by the PCI Special Interest Group. The MACH210A-7/10’s predictable timing ensures compliance with the PCI AC specifica- tions independent of the design. On the other hand, in ...

Page 9

Switch Matrix Figure 1. MACH210 PAL Block MACH210-7/10/12/15/20, Q-12/15/20 AMD Output Enable ...

Page 10

... 0 Max (Note 3) OUT Outputs Open ( 5 MHz (Note 4) and I (or I and OZL IH OZH MACH210A-7 (Com’l) ) Operating + with +4. +5.25 V Min Typ Max 2.4 0.5 2.0 0.8 10 –100 10 –100 –30 –160 = 0 mA) ...

Page 11

... Transparent Input Latch to Output Latch Gate Test Conditions MHz OUT D-Type T-Type LOW HIGH D-Type T-Type D-Type ) CNT T-Type D-Type T-Type LOW HIGH MACH210A-7 (Com’l) AMD Typ Unit = Min Max Unit 7.5 ns 5 ...

Page 12

... APR t Input, I/O, or Feedback to Output Enable EA t Input, I/O, or Feedback to Output Disable ER Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 12 MACH210A-7 (Com’l) -7 Min Max Unit 11 ...

Page 13

... (Note 0 Max (Note 3) OUT 5V MHz CC A (Note 4) and I (or I and OZL IH OZH MACH210A-10/12 (Com’l) AMD ) Operating + with +4. +5.25 V Min Typ Max Unit 2.4 V 0.5 V 2 –100 A ...

Page 14

... MHz OUT D-Type T-Type LOW HIGH D-Type 1/( T-Type D-Type ) CNT T-Type 1/( D-Type T-Type LOW HIGH 1/( WICL WICH MACH210A-10/12 (Com’l) Typ Unit = -10 -12 Min Max Min Max Unit 6 7 ...

Page 15

... Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. 3. Parameters measured with 16 outputs switching. MACH210A-10/12 (Com’l) AMD -10 -12 Min Max ...

Page 16

... (Note 0 Max (Note 3) OUT 5V MHz CC A (Note 4) and I (or I and OZL IH OZH MACH210A-12/14 (Ind) ) Operating – + with +4 +5.5 V Min Typ Max 2.4 0.5 2.0 0.8 10 –100 10 –100 –30 –160 135 Unit ...

Page 17

... MHz OUT D-Type T-Type LOW HIGH D-Type 1/( T-Type D-Type ) CNT T-Type 1/( D-Type T-Type LOW HIGH 1/( WICL WICH MACH210A-12/14 (Ind) AMD Typ Unit = -12 -14 Min Max Min Max Unit 7.5 ...

Page 18

... Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. 3. Parameters measured with 16 outputs switching. 18 MACH210A-12/14 (Ind) -12 -14 Min Max Min Max ...

Page 19

ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . Ambient Temperature with Power Applied . . . . . . . . . . . . . Supply Voltage with Respect to Ground ...

Page 20

AMD CAPACITANCE (Note 1) Parameter Symbol Parameter Description C Input Capacitance IN C Output Capacitance OUT SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter Symbol Parameter Description t Input, I/O, or Feedback to Combinatorial Output PD (Note 3) Setup ...

Page 21

SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) (continued) Parameter Symbol Parameter Description t Input Latch Gate Width LOW WIGL t Input, I/O, or Feedback to Output Through Transparent PDLL Input and Output Latches t Asynchronous Reset to Registered or ...

Page 22

AMD ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . Ambient Temperature With Power Applied . . . . . . . . . . . . . Supply Voltage with Respect to ...

Page 23

CAPACITANCE (Note 1) Parameter Symbol Parameter Description CIN Input Capacitance COUT Output Capacitance SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2) Parameter Symbol Parameter Description tPD Input, I/O, or Feedback to Combinatorial Output (Note 3) Setup Time from Input, I/O, ...

Page 24

AMD SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2) (continued) Parameter Symbol Parameter Description tAR Asynchronous Reset to Registered or Latched Output tARW Asynchronous Reset Width (Note 1) tARR Asynchronous Reset Recovery Time (Note 1) tAP Asynchronous Preset to Registered ...

Page 25

... (Note 0 Max (Note 3) OUT MHz CC A (Note 4) and I (or I and OZL IH OZH MACH210AQ-12 (Com’l) AMD ) Operating + with +4. +5.25 V Min Typ Max Unit 2.4 V 0.5 V 2 –100 A ...

Page 26

... Test Conditions MHz OUT D-type T-type LOW HIGH D-type T-type D-type ) CNT T-type D-type T-type LOW HIGH MACH210AQ-12 (Com’l) Typ Unit = -12 Min Max Unit ...

Page 27

... Input, I/O, or Feedback to Output Disable ER Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. MACH210AQ-12 (Com’l) AMD -12 Min Max Unit 6 ns ...

Page 28

... (Note 0 Max (Note 3) OUT 5V MHz CC A (Note 4) and I (or I and OZL IH OZH MACH210AQ-15/20 (Com’l) ) Operating + with +4. +5.25 V Min Typ Max 2.4 0.5 2.0 0.8 10 –100 10 –100 –30 –160 45 Unit ...

Page 29

... D-type T-type LOW HIGH D-type 1/( T-type D-type ) CNT T-type D-type 1/( T-type D-type T-type LOW HIGH 1/( WICL WICH MACH210AQ-15/20 (Com’l) AMD Typ Unit = -15 -20 Min Max Min Max Unit ...

Page 30

... Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. 3. Parameters measured with 16 outputs switching. 30 MACH210AQ-15/20 (Com’l) -15 -20 Min Max Min ...

Page 31

... VIN = 5.25 V, VCC = Max (Note 2) VIN = 0 V, VCC = Max (Note 2) VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.5 V, VCC = Max (Note 3) VCC = MHz (Note 4) MACH210AQ-18/24 (Ind) AMD ) – + ...

Page 32

... Test Conditions VIN = 2.0 V VCC = 5 VOUT = 2 MHz D-type T-type LOW HIGH D-type 1/(tS + tCO) T-type D-type T-type D-type 1/(tS + tH) T-type D-type T-type LOW HIGH 1/(tWICL + tWICH ) MACH210AQ-18/24 (Ind) Typ Unit -18 -24 Min Max Min Max Unit 20 ...

Page 33

... Input, I/O, or Feedback to Output Disable (Note 3) Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. 3. Parameters measured with 16 outputs switching. MACH210AQ-18/24 (Ind) AMD -18 -24 Min Max ...

Page 34

AMD TYPICAL CURRENT VS. VOLTAGE (I-V) CHARACTERISTICS –1 (mA –0.8 –0.6 –0.4 –0 –20 –40 –60 –80 Output, LOW I (mA) ...

Page 35

... The selected “typical” pattern is a 16-bit up/down counter. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. Maximum frequency shown uses internal feedback and a D-type register. MACH210AQ Frequency (MHz) MACH210-7/10/12/15/20, Q-12/15/20 AMD MACH210A MACH210 80 90 100 14128I-8 35 ...

Page 36

AMD TYPICAL THERMAL CHARACTERISTICS Measured ambient. These parameters are not tested. Parameter Symbol Parameter Description Thermal impedance, junction to case jc Thermal impedance, junction to ambient ja Thermal impedance, junction to jma ambient with air flow Plastic ...

Page 37

SWITCHING WAVEFORMS Input, I/O, or Feedback Combinatorial Input, I/O, or Feed- back t S Clock Registered Output Registered Output t WH Clock Clock Width Registered Input t SIR Input Register Clock Combinatorial Output Registered Input (MACH 2 and 4) Notes: ...

Page 38

AMD SWITCHING WAVEFORMS Latched In Gate Combinatorial Output Latched In Latched Out t IGOL Input Latch Gate t IGS Output Latch Gate Notes 1 Input pulse amplitude 3 Input ...

Page 39

SWITCHING WAVEFORMS t WICH Clock Input Register Clock Width (MACH 2 and 4) t ARW Input, I/O, or Feedback t AR Registered Output Clock Asynchronous Reset Input, I/O, or Feedback Outputs Notes 1 Input ...

Page 40

AMD KEY TO SWITCHING WAVEFORMS SWITCHING TEST CIRCUIT Specification Closed Open Closed Open Closed *Switching several outputs simultaneously should be avoided ...

Page 41

PARAMETERS MAX The parameter f is the maximum clock rate at which MAX the device is guaranteed to operate. Because the flexi- bility inherent in programmable logic devices offers a choice of clocked flip-flop designs, f three types of ...

Page 42

AMD ENDURANCE CHARACTERISTICS The MACH families are manufactured using AMD’s advanced Electrically Erasable process. This technol- ogy uses an EE cell to replace the fuse link used in Endurance Characteristics Parameter Symbol Parameter Description Min Pattern Data Retention Time t ...

Page 43

INPUT/OUTPUT EQUIVALENT SCHEMATICS ESD Protection 1 k Input 100 k Preload Feedback Circuitry Input I/O MACH210-7/10/12/15/20, Q-12/15/20 AMD V CC 100 14128I-25 43 ...

Page 44

AMD POWER-UP RESET The MACH devices have been designed with the capa- bility to reset during system power-up. Following power- up, all flip-flops will be reset to LOW. The output state will depend on the logic polarity. This feature provides ...

Page 45

USING PRELOAD AND OBSERVABILITY In order to be testable, a circuit must be both controllable and observable. To achieve this, the MACH devices incorporate register preload and observability. In preload mode, each flip-flop in the MACH device can be loaded ...

Page 46

... Sunnyvale, CA 94088-3543 (800) 222-9323 or (408) 732-2400 Advanced Micro Devices, Inc. P.O. Box 3453, MS 1028 Sunnyvale, CA 94088-3543 (800) 222-9323 or (408) 732-2400 Advanced Micro Devices, Inc. P.O. Box 3453, MS 1028 Sunnyvale, CA 94088-3543 (800) 222-9323 or (408) 732-2400 Cadence Design Systems 555 River Oaks Pkwy San Jose, CA 95134 ...

Page 47

... GmbH Busenstrasse 6 D-8033 Martinsried, Munich, Germany (87) 857-6667 Advanced Micro Devices is not responsible for any information relating to the products of third parties. The inclusion of such information is not a representation nor an endorsement by AMD of these products. (subject to change) (continued) SOFTWARE DEVELOPMENT SYSTEMS (Requires MACH Fitter) ...

Page 48

... No. 1, Alley 8, Lane 45 Bao Shing Rd., Shin Diau Taipei, Taiwan 2-917-3005 APPROVED ON-BOARD PROGRAMMERS MANUFACTURER Corelis, Inc. 12607 Hidden Creek Way, Suite H Cerritos, California 70703 (310) 926-6727 Advanced Micro Devices P.O. Box 3453, MS-1028 Sunnyvale, CA 94088-3453 (800) 222-9323 48 (subject to change) PROGRAMMER CONFIGURATION Pilot U84 BP1200 TM ...

Page 49

PROGRAMMER SOCKET ADAPTERS MANUFACTURER EDI Corporation P.O. Box 366 Patterson, CA 95363 (209) 892-3270 Emulation Technology 2344 Walsh Ave., Bldg. F Santa Clara, CA 95051 (408) 982-0660 Logical Systems Corp. P.O. Box 6184 Syracuse, NY 13217-6184 (315) 478-0722 Procon Technologies, ...

Page 50

AMD PHYSICAL DIMENSIONS* PL 044 44-Pin Plastic Leaded Chip Carrier (measured in inches) .685 .695 .650 .656 Pin 1 I.D. .685 .695 .650 .656 .026 .050 REF .032 TOP VIEW 50 .062 .083 .042 .056 .009 .015 .090 .120 .165 ...

Page 51

... BSC is an ANSI standard for Basic Space Centering. Trademarks Copyright 1995 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, MACH, and PAL are registered trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. 9.80 10.20 9 ...

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