MC68HC908AZ60ACFU Motorola, MC68HC908AZ60ACFU Datasheet
MC68HC908AZ60ACFU
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MC68HC908AZ60ACFU Summary of contents
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MC68HC908AZ60A/D REV 2.0 MC68HC908AZ60A MC68HC908AS60A Technical Data HCMOS Microcontroller Unit ...
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...
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... Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use ...
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... Technical Data 4 MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
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... Section 15. Computer Operating Properly (COP 223 Section 16. Low Voltage Inhibit (LVI 229 Section 17. External Interrupt Module (IRQ 235 Section 18. Serial Communications Interface (SCI 243 Section 19. Serial Peripheral Interface (SPI 285 Section 20. Timer Interface Module B (TIMB 317 MC68HC908AZ60A — Rev 2.0 MOTOROLA List of Paragraphs List of Paragraphs Technical Data 5 ...
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... Section 24. Keyboard Module (KBD 431 Section 25. Timer Interface Module A (TIMA 441 Section 26. Analog-to-Digital Converter (ADC 471 Section 27. Byte Data Link Controller (BDLC 483 Section 28. Electrical Specifications 529 Section 29. MC68HC908AS60 and MC68HC908AZ60 . 553 Technical Data 6 MC68HC908AZ60A — Rev 2.0 List of Paragraphs MOTOROLA ...
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... Technical Data — MC68HC908AZ60A 1.1 1.2 1.3 1.4 1.5 1.6 2.1 2.2 2.3 2.4 2.5 3.1 3.2 3.3 4.1 4.2 MC68HC908AZ60A — Rev 2.0 MOTOROLA Section 1. General Description Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Ordering Information Section 2. Memory Map Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Additional Status and Control Registers . . . . . . . . . . . . . . . . . . 58 Vector Addresses and Priority . . . . . . . . . . . . . . . . . . . . . . . . . 61 Section 3. RAM Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Section 4 ...
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... FLASH-2 Control and Block Protect Registers . . . . . . . . . . . . . 79 FLASH-2 Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 FLASH-2 Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . 83 FLASH-2 Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . 84 FLASH-2 Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 Section 6. EEPROM-1 Memory Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 EEPROM-1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 91 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 EEPROM-1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . 99 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 Table of Contents MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
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... MC68HC908AZ60A — Rev 2.0 MOTOROLA Section 7. EEPROM-2 Memory Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 EEPROM-2 Register Summary . . . . . . . . . . . . . . . . . . . . . . . 111 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 EEPROM-2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . 119 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 Section 8. Central Processor Unit (CPU) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Arithmetic/logic unit (ALU) ...
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... CGM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 190 Section 11. Configuration Register (CONFIG-1) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Section 12. Configuration Register (CONFIG-2) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Section 13. Break Module (BRK) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Table of Contents MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
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... MC68HC908AZ60A — Rev 2.0 MOTOROLA Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 Section 14. Monitor ROM (MON) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Section 15. Computer Operating Properly (COP) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 I/O Signals ...
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... Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263 SCI During Break Module Interrupts 264 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 I/O Registers 265 Section 19. Serial Peripheral Interface (SPI) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 Table of Contents MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
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... MC68HC908AZ60A — Rev 2.0 MOTOROLA Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 Pin Name and Register Name Conventions . . . . . . . . . . . . . . 287 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 Interrupts 301 Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . . 302 Section 20. Timer Interface Module B (TIMB) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 Interrupts ...
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... Port 355 Port 357 Port 360 Port 363 Port 366 Port 369 Port .373 Section 23. MSCAN Controller (MSCAN08) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 External Pins 382 Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 Interrupts 392 Table of Contents MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
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... MC68HC908AZ60A — Rev 2.0 MOTOROLA Protocol Violation Protection 394 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .394 Section 24. Keyboard Module (KBD) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432 Keyboard Initialization 435 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .436 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . .436 I/O Registers 437 Section 25. Timer Interface Module A (TIMA) Contents ...
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... Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 BDLC MUX Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 BDLC Protocol Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 BDLC CPU Interface 512 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .527 Section 28. Electrical Specifications Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 547 Table of Contents MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
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... MC68HC908AZ60A — Rev 2.0 MOTOROLA Section 29. MC68HC908AS60 and MC68HC908AZ60 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553 Changes from the MC68HC908AS60 and MC68HC908AZ60 (non-A suffix devices 553 Revision History Major Changes Between Revision 2.0 and Revision 1 559 Major Changes Between Revision 1.0 and Revision 0 559 Table of Contents Table of Contents Technical Data ...
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... Table of Contents Technical Data 18 MC68HC908AZ60A — Rev 2.0 Table of Contents MOTOROLA ...
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... MC68HC908AZ60A — Rev 2.0 MOTOROLA Title MCU Block Diagram for the MC68HC908AZ60A (64-Pin QFP MCU Block Diagram for the MC68HC908AS60A (64-Pin QFP and 52-pin PLCC MC68HC908AZ60A (64-Pin QFP MC68HC908AS60A (64-Pin QFP MC68HC908AS60A (52-Pin PLCC Power supply bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Memory Map (Continued I/O Data, Status and Control Registers . . . . . . . . . . . . . . . . . . 54 Additional Status and Control Registers ...
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... Condition code register (CCR 133 SIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 SIM I/O Register Summary 149 CGM Clock Signals 151 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Sources of Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Interrupt Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 List of Figures MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
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... Slow Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 18-10 Fast Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260 18-11 SCI Control Register 1 (SCC1 266 18-12 SCI Control Register 2 (SCC2 269 18-13 SCI Control Register 3 (SCC3 272 18-14 SCI Status Register 1 (SCS1 274 18-15 Flag Clearing Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . .276 MC68HC908AZ60A — Rev 2.0 MOTOROLA . . . . . . . . . . . . . . . . . . . . . . . . 246 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 . . . . . . . . . . . . . . . . . . . . . . 254 List of Figures List of Figures Technical Data 21 ...
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... PIT Counter Modulo Registers (PMODH–PMODL 351 22-1 I/O Port Register Summary 354 22-2 Port A Data Register (PTA .355 22-3 Data Direction Register A (DDRA 355 22-4 Port A I/O Circuit 356 22-5 Port B Data Register (PTB .357 22-6 Data Direction Register B (DDRB 358 22-7 Port B I/O Circuit 359 Technical Data 336 List of Figures MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
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... MSCAN08 Control Register Structure . . . . . . . . . . . . . . . . . . 409 23-15 Module Control Register 0 (CMCR0 .411 23-16 Module Control Register (CMCR1 413 23-17 Bus Timing Register 0 (CBTR0 414 23-18 Bus Timing Register 1 (CBTR1 415 23-19 Receiver Flag Register (CRFLG 417 MC68HC908AZ60A — Rev 2.0 MOTOROLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 List of Figures List of Figures Technical Data 23 ...
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... J1850 VPW Received Passive EOF and IFS Symbol Times .502 27-9 J1850 VPW Received Active Symbol Times . . . . . . . . . . . . . 503 27-10 J1850 VPW Received BREAK Symbol Times . . . . . . . . . . . .504 27-11 J1850 VPW Bitwise Arbitrations . . . . . . . . . . . . . . . . . . . . . . . 505 27-12 BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 Technical Data 462 List of Figures . . . . . . . . . . . . . . . . . . . . 433 MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
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... Types of In-Frame Response (IFR 520 27-19 BDLC State Vector Register (BSVR .524 27-20 BDLC Data Register (BDR .526 28-1 SPI Master Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .537 28-2 SPI Slave Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 538 28-3 BDLC Variable Pulse Width Modulation (VPW) Symbol Timing MC68HC908AZ60A — Rev 2.0 MOTOROLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545 List of Figures List of Figures Technical Data 25 ...
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... List of Figures Technical Data 26 MC68HC908AZ60A — Rev 2.0 List of Figures MOTOROLA ...
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... READ (Read Memory) Command . . . . . . . . . . . . . . . . . . . . . 215 14-4 WRITE (Write Memory) Command 216 14-5 IREAD (Indexed Read) Command . . . . . . . . . . . . . . . . . . . . . 216 14-6 IWRITE (Indexed Write) Command . . . . . . . . . . . . . . . . . . . . 217 14-7 READSP (Read Stack Pointer) Command . . . . . . . . . . . . . . .217 MC68HC908AZ60A — Rev 2.0 MOTOROLA Title External Pins Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Clock Source Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Clock Signal Naming Conventions . . . . . . . . . . . . . . . . . . . . . . 47 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Vector Addresses ...
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... Port F Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 22-7 Port G Pin Functions 375 22-8 Port H Pin Functions 378 23-1 MSCAN08 Interrupt Vector Addresses . . . . . . . . . . . . . . . . . . 393 23-2 MSCAN08 vs CPU operating modes . . . . . . . . . . . . . . . . . . .395 23-3 Time segment syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 23-4 CAN Standard Compliant Bit Time Segment Settings . . . . . . 402 Technical Data 28 MC68HC908AZ60A — Rev 2.0 List of Tables MOTOROLA ...
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... BDLC I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 486 27-2 BDLC J1850 Bus Error Summary .511 27-3 BDLC Transceiver Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514 27-4 BDLC Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516 27-5 BDLC Transmit In-Frame Response Control Bit Priority Encoding 27-6 BDLC Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 MC68HC908AZ60A — Rev 2.0 MOTOROLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519 List of Tables List of Tables Technical Data 29 ...
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... List of Tables Technical Data 30 MC68HC908AZ60A — Rev 2.0 List of Tables MOTOROLA ...
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... MC68HC908AZ60A — Rev 2.0 MOTOROLA Section 1. General Description Introduction Features MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Pin Assignments Power Supply Pins (V DD Oscillator Pins (OSC1 and OSC2 External Reset Pin (RST External Interrupt Pin (IRQ Analog Power Supply Pin (V Analog Ground Pin (V SSA External Filter Capacitor Pin (CGMXFC .41 ADC Analog Power Supply Pin (VDDAREF) ...
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... Kbyte of On-Chip Electrically Erasable Programmable Read- Only Memory with Security Option (EEPROM) 2 Kbyte of On-Chip RAM Clock Generator Module (CGM) Serial Peripheral Interface Module (SPI) Serial Communications Interface Module (SCI) 8-Bit, 15-Channel Analog-to-Digital Converter (ADC-15) General Description MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
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... Master Reset Pin and Power-On Reset 16-Bit, 2-Channel Timer Interface Module (TIMB) (AZ only) 5-Bit Keyboard Interrupt Module (64-Pin QFP only) MSCAN Controller (Motorola Scalable CAN) implements CAN 2.0b Protocol as Defined in BOSCH Specification September 1991 (AZ only) SAE J1850 Byte Data Link Controller Digital Module (AS only) ...
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... General Description 1.4 MCU Block Diagram Figure 1-1 Figure 1-2 Technical Data 34 shows the structure of the MC68HC908AZ60A shows the structure of the MC68HC908AS60A General Description MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
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... PTA PTB PTC DDRA DDRB DDRC MC68HC908AZ60A — Rev 2.0 MOTOROLA PTF PTD PTE DDRF DDRE DDRD General Description General Description MCU Block Diagram PTG PTH DDRG DDRH Technical Data 35 ...
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... General Description PTA PTB PTC DDRA DDRB DDRC Technical Data 36 PTF PTD PTE DDRF DDRD DDRE General Description PTG* PTH* DDRG DDRH BDTxD BDRxD MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
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... PTF2/TACH4 6 PTF3/TACH5 7 PTF4/TBCH0 8 CANRx 9 CANTx 10 PTF5/TBCH1 11 PTF6 12 PTE0/TxD 13 PTE1/RxD 14 PTE2/TACH0 15 PTE3/TACH1 16 Figure 1-3. MC68HC908AZ60A (64-Pin QFP) MC68HC908AZ60A — Rev 2.0 MOTOROLA shows the MC68HC908AZ60A pin assignments. General Description General Description Pin Assignments PTH0/KBD3 48 PTD3/ATD11 47 PTD2/ATD10 REFL V 44 DDAREF PTD1/ATD9 43 PTD0/ATD8 42 PTB7/ATD7 ...
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... PTE1/RxD 14 PTE2/TACH0 15 PTE3/TACH1 16 Figure 1-4. MC68HC908AS60A (64-Pin QFP) Technical Data 38 shows the MC68HC908AS60A 64-pin QFP pin assignments. General Description PTH0/KBD3 48 PTD3/ATD11 47 PTD2/ATD10 REFL V 44 DDAREF PTD1/ATD9 43 PTD0/ATD8 42 PTB7/ATD7 41 PTB6/ATD6 40 PTB5/ATD5 39 PTB4/ATD4 38 PTB3/ATD3 37 PTB2/ATD2 36 PTB1/ATD1 35 PTB0/ATD0 34 PTA7 33 MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
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... RST 10 PTF0/TACH2 11 PTF1/TACH3 12 PTF2/TACH4 13 PTF3/TACH5 14 BDRxD 15 BDTxD 16 PTE0/TxD 17 PTE1/RxD 18 PTE2/TACH0 19 PTE3/TACH1 20 Figure 1-5. MC68HC908AS60A (52-Pin PLCC) MC68HC908AZ60A — Rev 2.0 MOTOROLA shows MC68HC908AS60A 52-pin PLCC pin assignments. General Description General Description Pin Assignments PTD3/ATD11 46 PTD2/ATD10 45 PTD1/ATD9 44 PTD0/ATD8 43 PTB7/ATD7 42 PTB6/ATD6 41 PTB5/ATD5 40 PTB4/ATD4 39 PTB3/ATD3 38 PTB2/ATD2 ...
Page 40
... Input/Output Ports and are the power supply and ground pins. The MCU operates SS MCU 0.1 µ NOTE: Component values shown represent typical applications. Figure 1-6. Power supply bypassing on page 285. General Description on page 353. Figure V SS MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 41
... External Filter Capacitor Pin (CGMXFC) CGMXFC is an external filter capacitor connection for the Clock Generator Module (CGM). See page 169. MC68HC908AZ60A — Rev 2.0 MOTOROLA Clock Generator Module (CGM) on page 147 for more information. on page 235. ) DDA is the power supply pin for the analog portion of the Clock ...
Page 42
... SS REFL ) REFH provides the reference high voltage for the Analog-to-Digital Analog-to-Digital Converter (ADC) on page 353. on page 471 and Input/Output Ports on page 353. General Description on page 471. on page Analog-to-Digital Converter on page 353. MC68HC908AZ60A — Rev 2.0 MOTOROLA on ...
Page 43
... Input/Output Ports 1.5.17 Port G I/O Pins (PTG2/KBD2–PTG0/KBD0) Port 3-bit special function port that shares all of its pins with the Keyboard Module (KBD). See and MC68HC908AZ60A — Rev 2.0 MOTOROLA on page 441, Timer Interface Module B (TIMB) on page 353. on page 243, Serial Peripheral Interface (SPI) Timer Interface Module A (TIMA) on page 353 ...
Page 44
... Table 1-1. External Pins Summary Function General-Purpose I/O General-Purpose I/O ADC Channel General-Purpose I/O General Purpose I/O General Description on page 431 MSCAN Byte Data Hysteresis Driver Reset State (1) Type Dual State No Input Hi-Z Dual State No Input Hi-Z Dual State No Input Hi-Z Dual State No Input Hi-Z MC68HC908AZ60A — Rev 2.0 MOTOROLA Byte ...
Page 45
... PTE7/SPSCK PTE6/MOSI PTE5/MISO PTE4/SS PTE3/TACH1 PTE2/TACH0 PTE1/RxD PTE0/TxD PTF6 PTF5/TBCH1–PTF4/TBCH0 PTF3/TACH5 PTF2/TACH4 PTF1/TACH3 MC68HC908AZ60A — Rev 2.0 MOTOROLA Driver Function Type General-Purpose I/O ADC Channel/Timer Dual State External Input Clock General-Purpose I/O Dual State ADC Channel General-Purpose I/O ADC Channel/Timer Dual State External Input Clock ...
Page 46
... Reset N/A CAN Serial Input N/A CAN Serial Output Output BDLC Serial Input N/A BDLC Serial Output Output General Description Hysteresis Reset State (1) Yes Input Hi-Z Yes Input Hi-Z Yes Input Hi-Z N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Input Hi-Z N/A Output N/A N/A N/A Input Hi-Z N/A Output Low Yes Input Hi-Z No Output Yes Input Hi-Z No Output MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 47
... Clock Signal Name MC68HC908AZ60A — Rev 2.0 MOTOROLA Table 1-2. Clock Signal Naming Conventions CGMXCLK Clock Generation Module (CGM) PLL-based or OSC1-based clock output from CGMOUT Bus Clock SPSCK TACLK TBCLK Table 1-3. Clock Source Summary Module ADC CAN COP CPU FLASH EEPROM RAM SPI ...
Page 48
... This section contains instructions for ordering the MC68HC908AZ60A / MC68HC908AS60A. 1.6.1 MC Order Numbers MC68HC908AS60ACFU (64-Pin QFP) MC68HC908AS60AVFU (64-Pin QFP) MC68HC908AS60AMFU (64-Pin QFP) MC68HC908AS60ACFN (52-Pin PLCC) MC68HC908AS60AVFN (52-Pin PLCC) MC68HC908AS60AMFN (52-Pin PLCC) MC68HC908AZ60ACFU (64-Pin QFP) MC68HC908AZ60AVFU (64-Pin QFP) MC68HC908AZ60AMFU (64-Pin QFP) Technical Data 48 Table 1-4. MC Order Numbers MC Order Number General Description Operating Temperature Range ° ...
Page 49
... The following definitions apply to the memory map representation of reserved and unimplemented locations. • • MC68HC908AZ60A — Rev 2.0 MOTOROLA Introduction I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Additional Status and Control Registers . . . . . . . . . . . . . . . 58 Vector Addresses and Priority . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 2-1, includes: 60K Bytes of FLASH EEPROM 2048 Bytes of RAM ...
Page 50
... System Integration Module MC68HC908AS60A I/O REGISTERS (64 BYTES) UNIMPLEMENTED , 11 BYTES I/O REGISTERS, 5 BYTES RAM-1, 1024 BYTES EEPROM-2, 512 BYTES Memory Map (SIM)). FLASH-2, 432 BYTES MC68HC908AZ60A — Rev 2.0 MOTOROLA $0000 ↓ $003F $0040 ↓ $004A $004B $004F $0050 ↓ $044F $0450 ↓ ...
Page 51
... EEPROM-1EEDIVH NON-VOLATILE REGISTER(EE1DIVHNVR) MC68HC908AZ60A — Rev 2.0 MOTOROLA EEPROM-1, 512 BYTES RAM-2 , 1024 BYTES FLASH-2, 29,184 BYTES FLASH-1, 32,256BYTES SIM BREAK STATUS REGISTER (SBSR) SIM RESET STATUS REGISTER (SRSR) RESERVED SIM BREAK FLAG CONTROL REGISTER (SBFCR) ...
Page 52
... RESERVED RESERVED RESERVED RESERVED Memory Map $FE11 $FE12 $FE13 $FE14 $FE15 $FE16 $FE17 $FE18 $FE19 $FE1A $FE1B $FE1C $FE1D $FE1E $FE1F $FE20 ↓ $FF1F $FF20 ↓ $FF6F $FF70 $FF71 $FF72 $FF73 $FF74 $FF75 $FF76 $FF77 $FF78 $FF79 MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 53
... Note 1: Registers appearing in italics are for Motorola test purpose only and only appear in the Memory Map for reference. Note2: While some differences between MC68HC908AS60A and MC68HC908AZ60A are highlighted, some registers remain available on both parts. Refer to individual modules for details whether these registers are active or inactive. ...
Page 54
... DDRD1 DDRD0 PTE3 PTE2 PTE1 PTF3 PTF2 PTF1 0 0 PTG2 PTG1 PTH1 DDRE3 DDRE2 DDRE1 DDRE0 DDRF3 DDRF2 DDRF1 DDRF0 0 0 DDRG2 DDRG1 DDRG0 R R MC68HC908AZ60A — Rev 2.0 MOTOROLA Bit 0 PTA0 PTB0 PTC0 PTD0 PTE0 PTF0 PTG0 PTH0 ...
Page 55
... PLL Bandwidth Control $001D Register (PBWC) PLL Programming Register $001E (PPG) Configuration Write-Once $001F Register (CONFIG-1) Timer A Status and Control $0020 Register (TASC) Figure 2-2. I/O Data, Status and Control Registers (Sheet MC68HC908AZ60A — Rev 2.0 MOTOROLA Bit Read Write Read: SPRIE ...
Page 56
... ELS2B ELS2A TOV2 CH2MAX ELS3B ELS3A TOV3 CH3MAX ELS4B ELS4A TOV4 CH4MAX MC68HC908AZ60A — Rev 2.0 MOTOROLA Bit 8 R Bit 0 R Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 ...
Page 57
... Timer B Counter Register Low $0042 (TBCNTL) Timer B Modulo Register High $0043 (TBMODH) Timer B Modulo Register Low $0044 (TBMODL) Figure 2-2. I/O Data, Status and Control Registers (Sheet MC68HC908AZ60A — Rev 2.0 MOTOROLA Bit Read: Bit Write: Read: Bit ...
Page 58
... CH0MAX ELS1B ELS1A TOV1 CH1MAX PPS2 PPS1 PPS0 Reserved inFigure 2-3. A noted exception MC68HC908AZ60A — Rev 2.0 MOTOROLA Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 ...
Page 59
... EEPROM-1 Nonvolatile Register $FE1C (EE1NVR) EEPROM-1 Control Register $FE1D (EE1CR) EEPROM-1 Array Configuration $FE1F Register (EE1ACR) $FF70 EE2DIV Hi Non-volatile Register (EE2DIVHNVR) Figure 2-3. Additional Status and Control Registers (Sheet MC68HC908AZ60A — Rev 2.0 MOTOROLA Bit Read Write: Read: POR PIN COP Write: ...
Page 60
... Bit 0 EEDIV3 EEDIV2 EEDIV1 EEDIV0 0 0 EEDIV1 EEDIV9 EEDIV8 0 EEDIV3 EEDIV2 EEDIV1 EEDIV0 EEBP3 EEBP2 EEBP1 EEBP0 T EELAT AUTO EEPGM EEBP3 EEBP2 EEBP1 EEBP0 T BPR3 BPR2 BPR1 BPR0 BPR3 BPR2 BPR1 BPR0 0 HVEN VERF ERASE PGM R = Reserved MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 61
... The vector addresses are shown note that certain vector addresses differ between the MC68HC908AS60A and the MC68HC908AZ60A as shown in the table recommended that all vector addresses are defined. Lowest Priority MC68HC908AZ60A — Rev 2.0 MOTOROLA Table 2-1. Vector Addresses Address MC68HC908AZ60A $FFCC TIMA Channel 5 Vector (High) ...
Page 62
... TIMA Channel 1 Vector (High) TIMA Channel 1 Vector (Low) TIMA Channel 0 Vector (High) TIMA Channel 0 Vector (Low) PLL Vector (High) PLL Vector (Low) IRQ1 Vector (High) IRQ1 Vector (Low) SWI Vector (High) SWI Vector (Low) Reset Vector (High) Reset Vector (Low) MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 63
... RAM locations efficiently. Page zero RAM, therefore, provides ideal locations for frequently accessed global variables. Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU registers. MC68HC908AZ60A — Rev 2.0 MOTOROLA Introduction Functional Description .63 RAM Section 3. RAM Technical Data ...
Page 64
... During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls. NOTE: Be careful when using nested subroutines. The CPU could overwrite data in the RAM during a subroutine or during the interrupt stacking operation. Technical Data 64 MC68HC908AZ60A — Rev 2.0 RAM MOTOROLA ...
Page 65
... This memory can be read, programmed and erased from a single external supply. The program and erase operations are enabled through the use of an internal charge pump. MC68HC908AZ60A — Rev 2.0 MOTOROLA Section 4. FLASH-1 Memory Introduction Functional Description .66 FLASH-1 Control and Block Protect Registers . . . . . . . . . . 67 FLASH-1 Control Register ...
Page 66
... Programming tools are available from Motorola. Contact your local Motorola representative for more information. NOTE: A security feature prevents viewing of the FLASH contents security feature is absolutely secure. However, Motorola’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Technical Data 66 $8000– ...
Page 67
... HVEN can only be set if either PGM = 1 or ERASE = 1 and the proper sequence for program or erase is followed. MASS — Mass Erase Control Bit Setting this read/write bit configures the FLASH-1 array for mass or page erase operation. MC68HC908AZ60A — Rev 2.0 MOTOROLA $FF88 Bit ...
Page 68
... Technical Data Erase operation selected 0 = Erase operation unselected 1 = Program operation selected 0 = Program operation unselected $FF80 Bit BPR7 BPR6 BPR5 BPR4 Figure 4-2. FLASH-1 Block Protect Register (FL1BPR) FLASH-1 Memory Bit 0 BPR3 BPR2 BPR1 BPR0 MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 69
... FLASH-1 memory at $FFFF. With this mechanism, the protect start address can be $XX00 and $XX80 (128 byte page boundaries) within the FLASH-1 array. FLASH-1 Protected Ranges: MC68HC908AZ60A — Rev 2.0 MOTOROLA Start address of FLASH block protect 1 Figure 4-3. FLASH-1 Block Protect Start Address FL1BPR[7:0] ...
Page 70
... When bits within FL1BPR are programmed (logic 0), they lock a block of memory address ranges as shown in on page 68. If FL1BPR is programmed with any value other than $FF, the protected block of FLASH memory can not be erased or programmed. Technical Data 70 FLASH-1 Block Protect Register MC68HC908AZ60A — Rev 2.0 FLASH-1 Memory MOTOROLA ...
Page 71
... FLASH array. B. While these operations must be performed in the order shown, other unrelated operations may occur between the steps. Care must be taken however to ensure that these operations do not access any address MC68HC908AZ60A — Rev 2.0 MOTOROLA Register (FL1CR). data. . NVS ...
Page 72
... Register (COPCTL) at $FFFF highly recommended that interrupts be disabled during program/erase operations. Technical Data 72 Register (FL1CR). of the page (128 byte block erased. . NVS . ERASE . NVH , after which the memory can be accessed in RCV normal read mode. FLASH-1 Memory MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 73
... Wait for time Repeat step 7 and 8 until all the bytes within the row are 10. Clear the PGM bit. 11. Wait for time, t MC68HC908AZ60A — Rev 2.0 MOTOROLA $XX00 to $XX3F $XX40 to $XX7F $XX80 to $XXBF $XXC0 to $XXFF configures the memory for program operation and enables the latching of address and data programming ...
Page 74
... FLASH Memory Characteristics max. PROG $FFD2-$FFD3 and $FFDA-$FFFF: Vector area on MC68HC908AS60A (40 bytes) $FFCC-$FFFF: Vector area on MC68HC908AZ60A (52 bytes) FLASH-1 Memory Figure maximum defined as the 64) ð t PGS NVS NVH PROG on page 543. MC68HC908AZ60A — Rev 2.0 MOTOROLA 4-4. HV ...
Page 75
... PROG This row program algorithm assumes the row programmed are initially erased. Figure 4-4. FLASH Programming Algorithm Flowchart MC68HC908AZ60A — Rev 2.0 MOTOROLA 1 Set PGM bit 2 Read the FLASH block protect register 3 Write any data to any FLASH address within the row address range desired ...
Page 76
... FLASH program/erase operations and leave the memory in a Standby Mode. NOTE: Standby Mode is the power saving mode of the FLASH module, in which all internal control signals to the FLASH are inactive and the current consumption of the FLASH is minimum. Technical Data 76 MC68HC908AZ60A — Rev 2.0 FLASH-1 Memory MOTOROLA ...
Page 77
... This memory can be read, programmed and erased from a single external supply. The program and erase operations are enabled through the use of an internal charge pump. MC68HC908AZ60A — Rev 2.0 MOTOROLA Section 5. FLASH-2 Memory Introduction Functional Description .78 FLASH-2 Control and Block Protect Registers . . . . . . . . . . 79 FLASH-2 Control Register ...
Page 78
... Programming tools are available from Motorola. Contact your local Motorola representative for more information. NOTE: A security feature prevents viewing of the FLASH contents security feature is absolutely secure. However, Motorola’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Technical Data 78 $0450– ...
Page 79
... HVEN can only be set if either PGM = 1 or ERASE = 1 and the proper sequence for program or erase is followed. MASS — Mass Erase Control Bit Setting this read/write bit configures the FLASH-2 array for mass or page erase operation. MC68HC908AZ60A — Rev 2.0 MOTOROLA $FE08 Bit ...
Page 80
... Technical Data Erase operation selected 0 = Erase operation unselected 1 = Program operation selected 0 = Program operation unselected $FF81 Bit BPR7 BPR6 BPR5 BPR4 Figure 5-2. FLASH-2 Block Protect Register (FL2BPR) FLASH-2 Memory Bit 0 BPR3 BPR2 BPR1 BPR0 MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 81
... FLASH-2 memory at $7FFF. With this mechanism, the protect start address can be $XX00 and $XX80 (128 byte page boundaries) within the FLASH-2 array. FLASH-2 Protected Ranges: MC68HC908AZ60A — Rev 2.0 MOTOROLA Start address of FLASH block protect 1 Figure 5-3. FLASH-2 Block Protect Start Address FL2BPR[7:0] ...
Page 82
... When bits within FL2BPR are programmed (logic 0), they lock a block of memory address ranges as shown in on page 80. If FL2BPR is programmed with any value other than $FF, the protected block of FLASH memory can not be erased or programmed. Technical Data 82 FLASH-2 Block Protect Register MC68HC908AZ60A — Rev 2.0 FLASH-2 Memory MOTOROLA ...
Page 83
... FLASH array. B. While these operations must be performed in the order shown, other unrelated operations may occur between the steps. Care must be taken however to ensure that these operations do not access any address MC68HC908AZ60A — Rev 2.0 MOTOROLA Register (FL2CR). data. . NVS ...
Page 84
... Register (COPCTL) at $FFFF highly recommended that interrupts be disabled during program/erase operations. Technical Data 84 Register (FL2CR). of the page (128 byte block erased. . NVS . ERASE . NVH , after which the memory can be accessed in RCV normal read mode. FLASH-2 Memory MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 85
... Wait for time Repeat step 7 and 8 until all the bytes within the row are 10. Clear the PGM bit. 11. Wait for time, t MC68HC908AZ60A — Rev 2.0 MOTOROLA $XX00 to $XX3F $XX40 to $XX7F $XX80 to $XXBF $XXC0 to $XXFF configures the memory for program operation and enables the latching of address and data programming ...
Page 86
... PROG must satisfy this condition FLASH Memory Characteristics max. PROG $0450-$047F: First row of FLASH-2 (48 bytes) FLASH-2 Memory Figure maximum defined as the 64) ð t PGS NVS NVH PROG on page 543. MC68HC908AZ60A — Rev 2.0 MOTOROLA 5-4. HV ...
Page 87
... PROG This row program algorithm assumes the row programmed are initially erased. Figure 5-4. FLASH Programming Algorithm Flowchart MC68HC908AZ60A — Rev 2.0 MOTOROLA 1 Set PGM bit 2 Read the FLASH block protect register 3 Write any data to any FLASH address within the row address range desired ...
Page 88
... FLASH program/erase operations and leave the memory in a Standby Mode. NOTE: Standby Mode is the power saving mode of the FLASH module, in which all internal control signals to the FLASH are inactive and the current consumption of the FLASH is minimum. Technical Data 88 MC68HC908AZ60A — Rev 2.0 FLASH-2 Memory MOTOROLA ...
Page 89
... MC68HC908AZ60A — Rev 2.0 MOTOROLA Section 6. EEPROM-1 Memory Introduction Features EEPROM-1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . 91 Functional Description .92 EEPROM-1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 92 EEPROM-1 Timebase Requirements . . . . . . . . . . . . . . . . 93 EEPROM-1 Program/Erase Protection . . . . . . . . . . . . . . . 93 EEPROM-1 Block Protection . . . . . . . . . . . . . . . . . . . . . . .94 EEPROM-1 Programming and Erasing EEPROM-1 Register Descriptions EEPROM-1 Control Register . . . . . . . . . . . . . . . . . . . . . . .99 EEPROM-1 Array Configuration Register . . . . . . . . . . . 101 EEPROM-1 Nonvolatile Register 103 EEPROM-1 Timebase Divider Register ...
Page 90
... Technical Data 90 on page 109. 512 bytes Non-Volatile Memory Byte, Block, or Bulk Erasable Non-Volatile EEPROM Configuration and Block Protection Options On-chip Charge Pump for Programming/Erasing Security Option AUTO Bit Driven Programming/Erasing Time Feature EEPROM-1 Memory EEPROM-2 MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 91
... Reset: Read: UNUSED UNUSED UNUSED EEPRTCT EEPROM-1 Array $FE1F Configuration Register Write: (EE1ACR) Reset: * Non-volatile EEPROM register; write by programming. Figure 6-1. EEPROM-1 Register Summary MC68HC908AZ60A — Rev 2.0 MOTOROLA Bit EEDIVSECD Unaffected by reset; $FF when blank EEDIV7 EEDIV6 EEDIV5 EEDIV4 Unaffected by reset; $FF when blank ...
Page 92
... Array Configuration Register (EE1ACR). For the EE1DIVNCR (two 8-bit registers: EE1DIVHNVR and EE1DIVLNVR), the corresponding volatile register is the EEPROM-1 Divider Register (EE1DIV: EE1DIVH and EE1 DIVL). Technical Data 92 EEPROM-1 Timebase Reference EEPROM-1 Security Option EEPROM-1 Block Protection EEPROM-1 Memory MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 93
... Once the EEPRTCT bit is programmed to 0 for the first time: • • • • MC68HC908AZ60A — Rev 2.0 MOTOROLA EEPROM-1 Configuration Programming and erasing of secured locations $08F0 to $08FF is permanently disabled. Secured locations $08F0 to $08FF can be read as normal. Programming and erasing of EE1NVR is permanently disabled. ...
Page 94
... Block Number (EEBPx) EEBP0 EEBP1 EEBP2 EEBP3 on page 101 for more information. EEPROM-1 Memory on page 94 and EEPROM-1 Array Table 6-1 shows the address Address Range $0800–$087F $0880–$08FF $0900–$097F $0980–$09FF EEPROM-1 Array MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 95
... Fourth event is recorded by programming bit position 3 Events five through eight are recorded in a similar fashion Note that none of the bit locations are actually programmed more than once although the byte was programmed eight times. MC68HC908AZ60A — Rev 2.0 MOTOROLA Description EEPROM-1 Memory EEPROM-1 Memory Functional Description Table 6-2 ...
Page 96
... EEPROM-1 write. Technical Data 96 EEPROM-1 Erasing on page 97 and on page 99 for more information. ( Step 7 if AUTO is set program the byte. EEPGM , for the programming voltage to fall EEFPV Step 8. (E) EEPROM-1 Memory EEPROM-1 Programming EEPROM-1 Control (A) (B) (D) MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 97
... NOTE: If using the AUTO mode, also set the AUTO bit in Step 1. 2. Byte erase: write any data to the desired address. 3. Set the EEPGM bit. MC68HC908AZ60A — Rev 2.0 MOTOROLA . However, on other MCUs, this delay time may be different. EEPGM (A) EELAT in EE1CR. Block erase: write any data to an address within the desired (B) block ...
Page 98
... EEPROM-1 array. Technical Data 98 for byte erase; t EEBYTE t for bulk erase. EEBULK. , for the erasing voltage to fall Step 8. EEFPV ( However, on other MCUs, this delay EEBYTE EEBLOCK EEBULK EEPROM-1 Memory for block erase; EEBLOCK (D) MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 99
... This read/write bit disables the EEPROM-1 module for lower power consumption. Any attempts to access the array will give unpredictable results. Reset clears this bit. EERAS1 and EERAS0 — Erase/Program Mode Select Bits These read/write bits set the erase modes. Reset clears these bits. MC68HC908AZ60A — Rev 2.0 MOTOROLA $FE1D Bit ...
Page 100
... Buses configured for EEPROM-1 programming or erase operation 0 = Buses configured for normal operation EEPROM-1 Programming on page 97 and EEPROM Memory Characteristics 1 = Automatic clear of EEPGM is enabled 0 = Automatic clear of EEPGM is disabled 1 = EEPROM-1 programming/erasing power switched EEPROM-1 programming/erasing power switched off EEPROM-1 Memory on page 96, EEPROM-1 on MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 101
... EEPRTCT — EEPROM-1 Protection Bit The EEPRTCT bit is used to enable the security feature in the EEPROM (see This feature is a write-once feature. Once the protection is enabled it may not be disabled. MC68HC908AZ60A — Rev 2.0 MOTOROLA $FE1F Bit Contents of EE1NVR ($FE1C) EEPROM-1 Program/Erase ...
Page 102
... Protected Byte Programming Available Available Only Byte Erasing Available Protected Protected Available Secured (No Programming or Erasing) Protected Byte Programming Available Available Only Byte Erasing Available Protected Protected Byte Programming Available Available Only Byte Erasing Available Available Protected Protected MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 103
... Address: Read: Write: Reset: NOTE: The EE1NVR will leave the factory programmed with $F0 such that the full array is available and unprotected. MC68HC908AZ60A — Rev 2.0 MOTOROLA EEPROM-1 Control Register $FE1C Bit UNUSED UNUSED UNUSED EEPRTCT = Unimplemented Figure 6-4. EEPROM-1 Nonvolatile Register (EE1NVR) ...
Page 104
... Figure 6-5. EE1DIV Divider High Register (EE1DIVH) $FE1B Bit EEDIV7 EEDIV6 EEDIV5 EEDIV4 Contents of EE1DIVLNVR ($FE11) Figure 6-6. EE1DIV Divider Low Register (EE1DIVL) EEPROM-1 Memory Bit 0 0 EEDIV10 EEDIV9 EEDIV8 Bit 0 EEDIV3 EEDIV2 EEDIV1 EEDIV0 MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 105
... For example, if the reference frequency is 4.9152MHz, the EE1DIV value is 172 NOTE: Programming/erasing the EEPROM with an improper EE1DIV value may result in data lost and reduce endurance of the EEPROM device. MC68HC908AZ60A — Rev 2.0 MOTOROLA 1 = EE1DIV security feature disabled 0 = EE1DIV security feature enabled EEPROM-1 Memory EEPROM-1 Memory EEPROM-1 Register Descriptions -6 +0 ...
Page 106
... Unaffected by reset; $FF when blank R = Reserved (EE1DIVHNVR)) $FE11 Bit EEDIV7 EEDIV6 EEDIV5 EEDIV4 Unaffected by reset; $FF when blank (EE1DIVLNVR) Register) or programmed to a logic 1 in the EEPROM-1 Memory Bit 0 R EEDIV10 EEDIV9 EEDIV8 Bit 0 EEDIV3 EEDIV2 EEDIV1 EEDIV0 EEPROM-1 MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 107
... If stop mode is entered while EELAT and EEPGM is cleared, the programming sequence will be terminated abruptly. In either case, the data integrity of the EEPROM is not guaranteed. MC68HC908AZ60A — Rev 2.0 MOTOROLA EEPROM-1 Memory EEPROM-1 Memory Low-Power Modes Technical Data ...
Page 108
... EEPROM-1 Memory Technical Data 108 EEPROM-1 Memory MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 109
... MC68HC908AZ60A — Rev 2.0 MOTOROLA Section 7. EEPROM-2 Memory Introduction 110 Features 110 EEPROM-2 Register Summary . . . . . . . . . . . . . . . . . . . . . . 111 Functional Description .112 EEPROM-2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . 112 EEPROM-2 Timebase Requirements . . . . . . . . . . . . . . . 112 EEPROM-2 Program/Erase Protection . . . . . . . . . . . . . . 113 EEPROM-2 Block Protection . . . . . . . . . . . . . . . . . . . . . .114 EEPROM-2 Programming and Erasing 114 EEPROM-2 Register Descriptions 119 EEPROM-2 Control Register ...
Page 110
... Technical Data 110 on page 89. 512 bytes Non-Volatile Memory Byte, Block, or Bulk Erasable Non-Volatile EEPROM Configuration and Block Protection Options On-chip Charge Pump for Programming/Erasing Security Option AUTO Bit Driven Programming/Erasing Time Feature EEPROM-2 Memory EEPROM-1 MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 111
... Reset: Read: UNUSED UNUSED UNUSED EEPRTCT EEPROM-2 Array $FF7F Configuration Register Write: (EE2ACR) Reset: * Non-volatile EEPROM register; write by programming. Figure 7-1. EEPROM-2 Register Summary MC68HC908AZ60A — Rev 2.0 MOTOROLA Bit EEDIVSECD Unaffected by reset; $FF when blank EEDIV7 EEDIV6 EEDIV5 EEDIV4 Unaffected by reset; $FF when blank ...
Page 112
... CGMXCLK or bus clock (selected by EEDIVCLK bit in CONFIG-2 Register) using a timebase divider circuit controlled by the 16-bit EEPROM-2 Timebase Divider EE2DIV Register (EE2DIVH and EE2DIVL). Technical Data 112 EEPROM-2 Timebase Reference EEPROM-2 Security Option EEPROM-2 Block Protection EEPROM-2 Memory MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 113
... Once armed, the protect option is permanently enabled consequence, all functions in the EE2NVR will remain in the state they were in immediately before the security was enabled. MC68HC908AZ60A — Rev 2.0 MOTOROLA EEPROM-2 Configuration Programming and erasing of secured locations $06F0 to $06FF is permanently disabled. Secured locations $06F0 to $06FF can be read as normal. ...
Page 114
... Table 7-1. EEPROM-2 Array Address Blocks Block Number (EEBPx) EEBP0 EEBP1 EEBP2 EEBP3 on page 121 for more information. EEPROM-2 Memory shows the address Address Range $0600–$067F $0680–$06FF $0700–$077F $0780–$07FF EEPROM-2 Array MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 115
... Note that none of the bit locations are actually programmed more than once although the byte was programmed eight times. When this technique is utilized, a program/erase cycle is defined as multiple program sequences (up to eight unique location followed by a single erase operation. MC68HC908AZ60A — Rev 2.0 MOTOROLA Description EEPROM-2 Memory EEPROM-2 Memory Functional Description Table 7-2 ...
Page 116
... Technical Data 116 EEPROM-2 Erasing on page 117 and on page 119 for more information. ( Step 7 if AUTO is set program the byte. EEPGM , for the programming voltage to fall EEFPV Step 8. (E) EEPROM-2 Memory EEPROM-2 Programming EEPROM-2 (A) (B) (D) MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 117
... Wait for a time Clear EEPGM bit. 6. Wait for a time Poll the EEPGM bit until it is cleared by the internal timer. MC68HC908AZ60A — Rev 2.0 MOTOROLA . However, on other MCUs, this delay time may be different. EEPGM (A) EELAT in EE2CR. Block erase: write any data to an address within the desired (B) block ...
Page 118
... E. Any attempt to clear both EEPGM and EELAT bits with a single instruction will only clear EEPGM. This is to allow time for removal of high voltage from the EEPROM-2 array. Technical Data 118 ( However, on other MCUs, this delay EEBYTE EEBLOCK EEBULK EEPROM-2 Memory MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 119
... This read/write bit is software programmable but has no functionality. EEOFF — EEPROM-2 power down This read/write bit disables the EEPROM-2 module for lower power consumption. Any attempts to access the array will give unpredictable results. Reset clears this bit. MC68HC908AZ60A — Rev 2.0 MOTOROLA $FF7D Bit ...
Page 120
... EEPROM Memory Characteristics 1 = Automatic clear of EEPGM is enabled 0 = Automatic clear of EEPGM is disabled 1 = EEPROM-2 programming/erasing power switched EEPROM-2 programming/erasing power switched off EEPROM-2 Memory EERAS0 MODE 0 Byte Program 1 Byte Erase 0 Block Erase 1 Bulk Erase X No Erase/Program on page 116, EEPROM- MC68HC908AZ60A — Rev 2.0 MOTOROLA on ...
Page 121
... EEPRTCT — EEPROM-2 Protection Bit The EEPRTCT bit is used to enable the security feature in the EEPROM (see This feature is a write-once feature. Once the protection is enabled it may not be disabled. MC68HC908AZ60A — Rev 2.0 MOTOROLA $FF7F Bit Contents of EE2NVR ($FF7C) EEPROM-2 Program/Erase ...
Page 122
... Protected Byte Programming Available Available Only Byte Erasing Available Protected Protected Available Secured (No Programming or Erasing) Protected Byte Programming Available Available Only Byte Erasing Available Protected Protected Byte Programming Available Available Only Byte Erasing Available Available Protected Protected MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 123
... Address: Read: Write: Reset: NOTE: The EE2NVR will leave the factory programmed with $F0 such that the full array is available and unprotected. MC68HC908AZ60A — Rev 2.0 MOTOROLA EEPROM-2 Control Register $FF7C Bit UNUSED UNUSED UNUSED EEPRTCT = Unimplemented Figure 7-4. EEPROM-2 Nonvolatile Register (EE2NVR) ...
Page 124
... Figure 7-5. EE2DIV Divider High Register (EE2DIVH) $FF7B Bit EEDIV7 EEDIV6 EEDIV5 EEDIV4 Contents of EE2DIVLNVR ($FF71) Figure 7-6. EE2DIV Divider Low Register (EE2DIVL) EEPROM-2 Memory Bit 0 0 EEDIV10 EEDIV9 EEDIV8 Bit 0 EEDIV3 EEDIV2 EEDIV1 EEDIV0 MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 125
... For example, if the reference frequency is 4.9152MHz, the EE2DIV value is 172 NOTE: Programming/erasing the EEPROM with an improper EE2DIV value may result in data lost and reduce endurance of the EEPROM device. MC68HC908AZ60A — Rev 2.0 MOTOROLA 1 = EE2DIV security feature disabled 0 = EE2DIV security feature enabled EEPROM-2 Memory EEPROM-2 Memory EEPROM-2 Register Descriptions -6 +0 ...
Page 126
... EEDIVSECD Unaffected by reset; $FF when blank R = Reserved (EE2DIVHNVR)) $FF71 Bit EEDIV7 EEDIV6 EEDIV5 EEDIV4 Unaffected by reset; $FF when blank (EE2DIVLNVR) EEPROM-2 Memory Bit 0 R EEDIV10 EEDIV9 EEDIV8 Bit 0 EEDIV3 EEDIV2 EEDIV1 EEDIV0 MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 127
... If stop mode is entered while EELAT and EEPGM is cleared, the programming sequence will be terminated abruptly. In either case, the data integrity of the EEPROM is not guaranteed. MC68HC908AZ60A — Rev 2.0 MOTOROLA EEPROM-2 Memory EEPROM-2 Memory Low-Power Modes Technical Data ...
Page 128
... EEPROM-2 Memory Technical Data 128 EEPROM-2 Memory MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 129
... Introduction This section describes the central processor unit (CPU8). The M68HC08 CPU is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (Motorola document number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture. MC68HC908AZ60A — Rev 2.0 MOTOROLA Section 8 ...
Page 130
... Figure 8-1. CPU registers Central Processor Unit (CPU) 0 ACCUMULATOR (A) 0 INDEX REGISTER (H:X) 0 STACK POINTER (SP) 0 PROGRAM COUNTER (PC) 0 CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 131
... In the indexed addressing modes, the CPU uses the contents of the index register to determine the conditional address of the operand. Read: H:X Write: Reset: The index register can also be used as a temporary data storage location. MC68HC908AZ60A — Rev 2.0 MOTOROLA Bit Unaffected by reset Figure 8-2. Accumulator (A) Bit 15 14 ...
Page 132
... Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. Technical Data 132 Figure 8-4. Stack pointer (SP) Central Processor Unit (CPU MC68HC908AZ60A — Rev 2.0 MOTOROLA Bit ...
Page 133
... CCR Write: Reset: V — Overflow flag The CPU sets the overflow flag when a two's complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag. MC68HC908AZ60A — Rev 2.0 MOTOROLA Bit Loaded with vector from $FFFE and $FFFF Figure 8-5 ...
Page 134
... After any reset, the interrupt mask is set and can only be cleared by the clear interrupt mask software instruction (CLI). Technical Data 134 1 = Carry between bits 3 and carry between bits 3 and Interrupts disabled 0 = Interrupts enabled Central Processor Unit (CPU) MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 135
... Arithmetic/logic unit (ALU) The ALU performs the arithmetic and logic operations defined by the instruction set. Refer to the CPU08 Reference Manual (Motorola document number CPU08RM/AD) for a description of the instructions and addressing modes and more detail about CPU architecture. MC68HC908AZ60A — Rev 2.0 ...
Page 136
... After exit from STOP mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set. Disables the CPU clock Break Module Central Processor Unit (CPU) (BRK). The program MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 137
... ASL ,X ASL opr,SP ASR opr ASRA ASRX Arithmetic Shift Right ASR opr,X ASR opr,X ASR opr,SP MC68HC908AZ60A — Rev 2.0 MOTOROLA provides a summary of the M68HC08 instruction set. Table 8-1. Instruction Set Summary Description A ← (A) + (M) + (C) A ← (A) + (M) SP ← (SP) + (16 « H:X ← (H:X) + (16 « ...
Page 138
... SP1 SP2 – – – – – – REL – – – – – – REL – – – – – – REL – – – – – – REL MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 139
... Branch Never BRSET Branch if Bit Set n,opr,rel BSET n,opr Set Bit MC68HC908AZ60A — Rev 2.0 MOTOROLA Description PC ← (PC rel ? ( ← (PC rel ? ( ← (PC rel ? ( ← (PC rel ? ( ← (PC rel ? ( ← (PC rel PC ← ...
Page 140
... IMM 65 3 ii+1 DIR IMM DIR EXT IX2 E3 4 ↕ – – ↕ ↕ ↕ ff IX1 SP1 SP2 MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 141
... JMP ,X JSR opr JSR opr JSR opr,X Jump to Subroutine JSR opr,X JSR ,X MC68HC908AZ60A — Rev 2.0 MOTOROLA Description ( ← (A) – ← (M) – ← (X) – ← (PC rel ? (result) ≠ ← (PC rel ? (result) ≠ ← (PC rel ? (result) ≠ ← ...
Page 142
... INH DIR INH 1 50 INH 1 ↕ – – ↕ ↕ ↕ 60 IX1 SP1 – – – – – – INH 9D 1 – – – – – – INH 62 3 MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 143
... Subtract with Carry SBC opr,X SBC ,X SBC opr,SP SBC opr,SP SEC Set Carry Bit MC68HC908AZ60A — Rev 2.0 MOTOROLA Description A ← (A) | (M) Push (A); SP ← (SP) – 1 Push (H); SP ← (SP) – 1 Push (X); SP ← (SP) – ← (SP + 1); Pull ( ← (SP + 1); Pull ( ← ...
Page 144
... INH 97 1 – – – – – – INH DIR INH 1 5D INH 1 0 – – ↕ ↕ – 6D IX1 SP1 – – – – – – INH 95 2 MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 145
... IX1+Indexed, 8-bit offset, post increment addressing mode? IX2Indexed, 16-bit offset addressing mode: MMemory location↕ N Negative bit— 8.9 Opcode Map The opcode map is provided in MC68HC908AZ60A — Rev 2.0 MOTOROLA Description A ← (X) (SP) ← (H:X) – 1 Any bit Operand (one or two bytes) Program counter ...
Page 146
... Central Processor Unit (CPU) Technical Data 146 Central Processor Unit (CPU) MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 147
... MC68HC908AZ60A — Rev 2.0 MOTOROLA Introduction 148 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . 150 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Clock Startup from POR or LVI Reset . . . . . . . . . . . . . . 151 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . 151 Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . .152 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Active Resets from Internal Sources . . . . . . . . . . . . . . . 153 Power-On Reset ...
Page 148
... Internal clock control Master reset control, including power-on reset (POR) and computer operating properly (COP) timeout Interrupt control: – Acknowledge timing – Arbitration control timing – Vector address generation CPU enable/disable timing System Integration Module (SIM) 9-1. Figure 9 summary of MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 149
... RESET PIN LOGIC SIM RESET STATUS REGISTER Register Name SIM Break Status Register (SBSR) SIM Reset Status Register (SRSR) SIM Break Flag Control Register (SBFCR) MC68HC908AZ60A — Rev 2.0 MOTOROLA STOP/WAIT CONTROL SIM COUNTER ÷ 2 CLOCK CLOCK GENERATORS CONTROL POR CONTROL MASTER ...
Page 150
... Signal from the Power-On Reset Module to the SIM IRST Internal Reset Signal R/W Read/Write Signal on page 169). Clock Generator Module (CGM) System Integration Module (SIM) SRSR SBFCR $FE01 $FE03 Description Figure 9-3. This clock can come Clock on page 169). MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 151
... CGMXCLK cycles. See 164. In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode. MC68HC908AZ60A — Rev 2.0 MOTOROLA CGMXCLK CLOCK A CGMOUT ÷ 2 ...
Page 152
... Illegal opcode Illegal address on page 165). Table 9-3. PIN Bit Set Timing Reset Type Number of Cycles Required to Set PIN POR/LVI All others System Integration Module (SIM) SIM Counter on page SIM Table 9-3 for details. Figure 4163 (4096 + ( MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 153
... The COP reset is asynchronous to the bus clock. The active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the MCU. CGMXCLK MC68HC908AZ60A — Rev 2.0 MOTOROLA Figure 9-4. External Reset Timing IRST RST PULLED LOW BY MCU RST ...
Page 154
... CGMXCLK cycles to allow stabilization of the oscillator. The RST pin is driven low during the oscillator stabilization time. The POR bit of the SIM reset status register (SRSR) is set and all other bits in the register are cleared. System Integration Module (SIM) INTERNAL RESET MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 155
... Illegal Address Reset An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register SRSR) and MC68HC908AZ60A — Rev 2.0 MOTOROLA 4096 32 32 CYCLES CYCLES Figure 9-7 ...
Page 156
... At power-on, the POR circuit asserts the signal PORRST. Once the SIM Technical Data 156 voltage falls to the V voltage. The LVI bit in the SIM reset LVII . Another sixty-four CGMXCLK cycles later, the LVIR on page 229. System Integration Module (SIM) MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 157
... Program Exception Control Normal, sequential program execution can be changed in three different ways: • • • MC68HC908AZ60A — Rev 2.0 MOTOROLA Active Resets from Internal Sources Interrupts – Maskable hardware CPU interrupts – Non-maskable software interrupt instruction (SWI) Reset Break interrupts System Integration Module (SIM) ...
Page 158
... PC – 1[7:0] R/W Technical Data 158 Figure 9-8 shows interrupt entry timing. SP – – – – – 1[15: CCR . Figure 9-8 Interrupt Entry System Integration Module (SIM) Figure Figure VECT H VECT L START ADDR V DATA H V DATA L OPCODE MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 159
... YES (AS MANY INTERRUPTS AS EXIST ON CHIP) MC68HC908AZ60A — Rev 2.0 MOTOROLA FROM RESET YES BREAK INTERRUPT? I BIT SET BIT SET? NO YES IRQ1 INTERRUPT? NO LOAD PC WITH INTERRUPT VECTOR. FETCH NEXT INSTRUCTION. YES SWI INSTRUCTION? NO YES RTI UNSTACK CPU REGISTERS. INSTRUCTION? NO Figure 9-9. Interrupt Processing ...
Page 160
... H register and then restore it prior to exiting the routine. Technical Data 160 SP – – – – 1 [7:0] PC – 1 [15:8] Figure 9-10. Interrupt Recovery System Integration Module (SIM OPCODE OPERAND Figure 9-11 MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 161
... NOTE: A software interrupt pushes PC onto the stack. A software interrupt does not push PC – hardware interrupt does. 9.6.2 Reset All reset sources always have higher priority than interrupts and cannot be arbitrated. MC68HC908AZ60A — Rev 2.0 MOTOROLA CLI LDA #$FF INT1 PSHH PULH RTI ...
Page 162
... The operation of each of these modes is described below. Both STOP and WAIT clear the interrupt mask (I) in the condition code register, allowing interrupts to occur. Technical Data 162 on page 203. The SIM puts the CPU into the break System Integration Module (SIM) MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 163
... If the COP disable bit, COPD, in the configuration register is logic 0, then the computer operating properly module (COP) is enabled and remains active in wait mode. R/W EXITSTOPWAIT NOTE: EXITSTOPWAIT = MC68HC908AZ60A — Rev 2.0 MOTOROLA Figure 9-12 IAB WAIT ADDR WAIT ADDR + 1 IDB PREVIOUS DATA NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction ...
Page 164
... It is then used to time the recovery period. Technical Data 164 32 Cycles IAB $6E0B IDB $A6 $A6 $A6 RST Figure 9-14. Wait Recovery from Internal Reset Figure 9-15 shows stop mode entry timing. System Integration Module (SIM) 32 Cycles RST VCT H RST VCT L MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 165
... CGMXCLK INT/BREAK IAB Figure 9-16. Stop Mode Recovery from Interrupt or Break 9.8 SIM Registers The SIM has three memory mapped registers. MC68HC908AZ60A — Rev 2.0 MOTOROLA IAB STOP ADDR STOP ADDR + 1 IDB PREVIOUS DATA R/W NOTE: Previous data can be operand data or the STOP opcode, depending on the last ...
Page 166
... See if wait mode was exited by break RETURNLO is not zero, ; then just decrement low byte. ; Else deal with high byte, too. ; Point to WAIT/STOP opcode. ; Restore H register. System Integration Module (SIM Bit See Note 0 NOTE: Writing a logic 0 clears BW MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 167
... PIN — External Reset Bit COP — Computer Operating Properly Reset Bit ILOP — Illegal Opcode Reset Bit ILAD — Illegal Address Reset Bit (opcode fetches only) LVI — Low-Voltage Inhibit Reset Bit MC68HC908AZ60A — Rev 2.0 MOTOROLA $FE01 Bit POR ...
Page 168
... Technical Data 168 $FE03 Bit BCFE Reserved Figure 9-19. SIM Break Flag Control Register (SBFCR Status bits clearable during break 0 = Status bits not clearable during break System Integration Module (SIM Bit MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 169
... MC68HC908AZ60A — Rev 2.0 MOTOROLA Introduction 170 Features 170 Functional Description .171 Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . 171 Phase-Locked Loop Circuit (PLL 173 Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Acquisition and Tracking Modes Manual and Automatic PLL Bandwidth Modes Programming the PLL Special Programming Exceptions Base Clock Selector Circuit . . . . . . . . . . . . . . . . . . . . . . 179 CGM External Connections ...
Page 170
... Phase-Locked Loop with Output Frequency in Integer Multiples of the Crystal Reference Programmable Hardware Voltage-Controlled Oscillator (VCO) for Low-Jitter Operation Automatic Bandwidth Control Mode for Low-Jitter Operation Automatic Frequency Lock Detector CPU Interrupt on Entry or Exit from Locked Condition Clock Generator Module (CGM) MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 171
... Connect the external clock to the OSC1 pin and let the OSC2 pin float. MC68HC908AZ60A — Rev 2.0 MOTOROLA Crystal oscillator circuit — The crystal oscillator circuit generates the constant crystal frequency clock, CGMXCLK. Phase-locked loop (PLL) — The PLL generates the programmable VCO frequency clock CGMVCLK. Base clock selector circuit — ...
Page 172
... FILTER OSCILLATOR PLL ANALOG BANDWIDTH INTERRUPT CONTROL CONTROL AUTO ACQ PLLIE PLLF MUL7–MUL4 CGMVCLK FREQUENCY DIVIDER Figure 10-1. CGM Block Diagram Clock Generator Module (CGM) CGMXCLK A CGMOUT *When CGMOUT = B PTC3 MONITOR MODE USER MODE CGMINT MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 173
... The PLL is a frequency generator that can operate in either acquisition mode or tracking mode, depending on the accuracy of the output frequency. The PLL can change between acquisition and tracking modes either automatically or manually. 10.4.2.1 Circuits The PLL consists of these circuits: • • • MC68HC908AZ60A — Rev 2.0 MOTOROLA Bit PLLF PLLIE PLLON ...
Page 174
... Acquisition and Tracking Modes . The circuit determines the mode of the PLL and the CGMRDV Clock Generator Module (CGM) CGMVRS is equal to the nominal center-of- NOM , and is fed to the PLL through . CGMVCLK for more on page 175. The value MC68HC908AZ60A — Rev 2.0 MOTOROLA . . , ...
Page 175
... See MC68HC908AZ60A — Rev 2.0 MOTOROLA Acquisition mode — In acquisition mode, the filter can make large frequency corrections to the VCO. This mode is used at PLL startup or when the PLL has suffered a severe noise hit and the VCO frequency is far off the desired frequency ...
Page 176
... PLL as the clock source to CGMOUT (BCS = 1). The LOCK bit is disabled. CPU interrupts from the CGM are disabled. Clock Generator Module (CGM) Acquisition and on page on page 530. PLL Control and busmax on page 530), after , after entering tracking mode al MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 177
... Choose the desired bus frequency Calculate the desired VCO frequency Using a reference frequency Calculate the VCO frequency, f MC68HC908AZ60A — Rev 2.0 MOTOROLA Table 10-2. Variable Definitions Variable f Desired Bus Clock Frequency BUSDES f ...
Page 178
... In the lower four bits of the PLL programming register (PPG), program the binary equivalent of L. Clock Generator Module (CGM) , and compare f with BUS BUS = 8 MHz or another f . RCLK , calculate the VCO linear NOM f CGMVCLK ----------------------- - f NOM = 7 . The CGMVRS NOM f NOM ≤ . --------------- - 2 MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 179
... PLL, so that the PLL would be disabled and the crystal clock would be forced as the source of the base clock. MC68HC908AZ60A — Rev 2.0 MOTOROLA A 0 value for N is interpreted the same as a value value for L disables the PLL and prevents its selection as the source for the base clock ...
Page 180
... Series resistor, R (optional may not be required for all ranges of operation, S also shows the external components for the PLL: Bypass capacitor, C BYP Filter capacitor Acquisition/Lock Time Specifications Clock Generator Module (CGM) Figure 10-3 shows only the on page 190 for MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 181
... The CGMXFC pin is required by the loop filter to filter out phase corrections. A small external capacitor is connected to this pin. NOTE: To prevent noise problems, C CGMXFC pin as possible with minimum routing distances and no routing of other signals across the C MC68HC908AZ60A — Rev 2.0 MOTOROLA SIMOSCEN * ...
Page 182
... PLL. Connect the pin to the same voltage potential as the V carefully for maximum noise immunity and place bypass DDA ) and comes directly from the crystal oscillator CGMXCLK Figure 10-3 shows only the logical relation of CGMXCLK to Clock Generator Module (CGM) pin. DD MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 183
... LOCK bit toggles, setting the PLL flag, PLLF. When the AUTO bit in the PLL bandwidth control register (PBWC) is clear, PLLIE cannot be written and reads as logic 0. Reset clears the PLLIE bit. MC68HC908AZ60A — Rev 2.0 MOTOROLA PLL control register (PCTL) PLL bandwidth control register (PBWC) PLL programming register (PPG) $001C ...
Page 184
... Change in lock condition change in lock condition 1 = PLL PLL off on page 179. Reset and the STOP instruction 1 = CGMVCLK divided by two drives CGMOUT 0 = CGMXCLK divided by two drives CGMOUT Clock Generator Module (CGM) Base Clock Selector Circuit Base MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 185
... Address: Read: Write: Reset: MC68HC908AZ60A — Rev 2.0 MOTOROLA Base Clock Selector Circuit Selects automatic or manual (software-controlled) bandwidth control mode Indicates when the PLL is locked In automatic bandwidth control mode, indicates when the PLL is in acquisition or tracking mode In manual operation, forces the PLL into acquisition or tracking ...
Page 186
... Technical Data 186 1 = Automatic bandwidth control 0 = Manual bandwidth control 1 = VCO frequency correct or locked 0 = VCO frequency incorrect or unlocked 1 = Tracking mode 0 = Acquisition mode 1 = Crystal reference not active 0 = Crystal reference active Clock Generator Module (CGM) MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 187
... These read/write bits control the modulo feedback divider that selects the VCO frequency multiplier, N. (See Programming the PLL select bits configures the modulo feedback divider the same as a value of $1. Reset initializes these bits give a default multiply value of 6. MC68HC908AZ60A — Rev 2.0 MOTOROLA $001E Bit MUL7 ...
Page 188
... Special Programming Exceptions Base Clock Selector Circuit Clock Generator Module (CGM) VCO Frequency Multiplier ( Programming the PLL on page on page 183.) VRS7–VRS4 cannot on page 179. A value of on page 179 and on page 179 for more MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 189
... PLL without turning it off. Applications that require the PLL to wake the MCU from wait mode also can deselect the PLL output without turning off the PLL. MC68HC908AZ60A — Rev 2.0 MOTOROLA Clock Generator Module (CGM) Clock Generator Module (CGM) Interrupts ...
Page 190
... In a PLL, the step input occurs when the PLL is turned on or when it suffers a noise hit. The tolerance is usually specified as a percent of the Technical Data 190 Clock Generator Module (CGM) Break Module (BRK) on MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 191
... PLL. Therefore, the definitions for acquisition and lock times for this module are: • • MC68HC908AZ60A — Rev 2.0 MOTOROLA Acquisition time the time the PLL takes to reduce the error acq between the actual output frequency and the desired output frequency to less than the tracking mode entry tolerance, ∆ ...
Page 192
... LOCK bit becomes set in the PLL bandwidth control register (PBWC). (See Bandwidth Modes on page 175). CGMRDV Choosing a Filter Capacitor Clock Generator Module (CGM) Manual and Automatic PLL (please reference Figure 10-1). . CGMXCLK on page 193. . The DDA MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 193
... Reaction Time Calculation The actual acquisition and lock times can be calculated using the equations below. These equations yield nominal values under the following conditions: MC68HC908AZ60A — Rev 2.0 MOTOROLA Parametric Influences on Reaction Time , is critical to the stability and reaction F C ...
Page 194
... DDA ------------ - K ACQ 4 ----------- - K TRK + t ACQ AL Manual on page 175). A certain , before exiting acquisition TRK , is required to ascertain TRK . Therefore, the Lock /f , and the ACQ CGMRDV /f TRK CGMRDV MC68HC908AZ60A — Rev 2.0 MOTOROLA . Also, ...
Page 195
... This is considered sufficient for all such device to device variation. Motorola recommends measuring the lock time of the application system by utilizing dedicated software, running in FLASH, EEPROM or RAM. This should toggle a port pin when the PLL is first configured and switched on, then again when it goes from acquisition to lock mode and finally again when the PLL lock bit is set ...
Page 196
... Clock Generator Module (CGM) Technical Data 196 Clock Generator Module (CGM) MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 197
... NOTE: If the LVI module and the LVI reset signal are enabled, a reset occurs when V MC68HC908AZ60A — Rev 2.0 MOTOROLA Introduction 197 Functional Description .197 Resets caused by the LVI module Power to the LVI module ...
Page 198
... LVI enabled during stop mode 0 = LVI disabled during stop mode current will be higher page 229 LVI module resets enabled 0 = LVI module resets disabled Configuration Register (CONFIG-1) . TRIPR Bit 0 SSREC COPL STOP COPD Low Voltage Low MC68HC908AZ60A — Rev 2.0 MOTOROLA ...
Page 199
... ROM code request submitted. The enable/disable logic is not necessarily identical in all parts of the AS and AZ families doubt, check with your local field applications representative. MC68HC908AZ60A — Rev 2.0 MOTOROLA 1 = LVI module power enabled 0 = LVI module power disabled on page 164 Stop mode recovery after 32 CGMXCLK cycles 0 = Stop mode recovery after 4096 CGMXCLK cycles on page 223) ...
Page 200
... Configuration Register (CONFIG-1) Technical Data 200 Configuration Register (CONFIG-1) MC68HC908AZ60A — Rev 2.0 MOTOROLA ...