MC68L11E1FN2 Motorola, MC68L11E1FN2 Datasheet
MC68L11E1FN2
Related parts for MC68L11E1FN2
MC68L11E1FN2 Summary of contents
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... M68HC11 Microcontrollers WWW.MOTOROLA.COM/SEMICONDUCTORS M68HC11E Family Technical Data M68HC11E/D Rev. 4, 7/2002 ...
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...
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... The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Motorola and the Stylized M Logo are registered trademarks of Motorola, Inc. DigitalDNA is a trademark of Motorola, Inc. http://www.motorola.com/semiconductors/ © Motorola, Inc., 2002 ...
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Sr‰v†v‚ÃCv†‡‚…’ Revision Date Level 4.4.3.1 System Configuration Register description May, 2001 3.1 Added 11.22 EPROM Characteristics June, 2001 3.2 following the table December, 7.8.2 Serial Communications Control Register 1 3.3 2001 (M) description corrected 11.8 MC68L11E9/E20 DC Electrical Characteristics changed ...
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... Section 8. Serial Peripheral Interface (SPI 165 Section 9. Timing System 177 Section 10. Analog-to-Digital (A/D) Converter . . . . . . . 209 Section 11. Electrical Characteristics . . . . . . . . . . . . . . 221 Section 12. Mechanical Data . . . . . . . . . . . . . . . . . . . . . 253 Section 13. Ordering Information . . . . . . . . . . . . . . . . . 261 Appendix A. Development Support . . . . . . . . . . . . . . . . 269 Appendix B. EVBU Schematic . . . . . . . . . . . . . . . . . . . . 275 MC68HC11E Family — Rev. 4 MOTOROLA List of Sections List of Sections Technical Data 5 ...
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... MC68HC711E9 Devices with PCbug11 on the M68HC711E9PGMR . . . . . . . . . . . . . . . . . . . 323 EB188 — Enabling the Security Feature on M68HC811E2 Devices with PCbug11 on the M68HC711E9PGMR . . . . . . . . . . . . . . . . . . . 327 EB296 — Programming MC68HC711E9 Devices with PCbug11 and the M68HC11EVBU . . . . . . . . . 331 Technical Data 6 MC68HC11E Family — Rev. 4 List of Sections MOTOROLA ...
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... MC68HC11E Family — Rev. 4 MOTOROLA Section 1. General Description Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Section 2. Pin Descriptions Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 V and RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Crystal Driver and External Clock Input (XTAL and EXTAL E-Clock Output ( Interrupt Request (IRQ Non-Maskable Interrupt (XIRQ/V MODA and MODB (MODA/LIR and MODB/V ...
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... Carry/Borrow ( Overflow ( Zero ( .51 Negative ( Interrupt Mask ( Half Carry ( .52 X Interrupt Mask ( .52 STOP Disable ( Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Opcodes and Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Immediate Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Indexed Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Instruction Set .56 Table of Contents MC68HC11E Family — Rev. 4 MOTOROLA ...
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... MC68HC11E Family — Rev. 4 MOTOROLA Section 4. Operating Modes and On-Chip Memory Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Single-Chip Mode Expanded Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Bootstrap Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Memory Map RAM and Input/Output Mapping Mode Selection System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 System Configuration Register . . . . . . . . . . . . . . . . . . . . 86 RAM and I/O Mapping Register . . . . . . . . . . . . . . . . . . . .89 System Configuration Options Register . . . . . . . . . . . . . . 91 EPROM/OTPROM ...
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... Interrupt Recognition and Register Stacking . . . . . . . . . . . 122 Non-Maskable Interrupt Request (XIRQ .123 Illegal Opcode Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Software Interrupt (SWI 124 Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Reset and Interrupt Processing . . . . . . . . . . . . . . . . . . . . . 124 Low-Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 Table of Contents MC68HC11E Family — Rev. 4 MOTOROLA ...
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... MC68HC11E Family — Rev. 4 MOTOROLA Section 6. Parallel Input/Output (I/O) Ports Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Port 134 Port 136 Port 136 Port 138 Port 139 Handshake Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Parallel I/O Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Section 7. Serial Communications Interface (SCI) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Transmit Operation ...
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... Timer Output Compare Registers . . . . . . . . . . . . . . . . . . . 187 Timer Compare Force Register . . . . . . . . . . . . . . . . . . . . . 190 Output Compare Mask Register 191 Output Compare Data Register . . . . . . . . . . . . . . . . . . . . . 192 Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Timer Control Register 194 Timer Interrupt Mask 1 Register 195 Timer Interrupt Flag 1 Register . . . . . . . . . . . . . . . . . . . . . 196 Table of Contents MC68HC11E Family — Rev. 4 MOTOROLA ...
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... A/D Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . 218 10.11 A/D Converter Result Registers . . . . . . . . . . . . . . . . . . . . . . .220 MC68HC11E Family — Rev. 4 MOTOROLA Timer Interrupt Mask 2 Register 196 Timer Interrupt Flag Register 198 Real-Time Interrupt (RTI 199 Timer Interrupt Mask Register 200 Timer Interrupt Flag Register 201 Pulse Accumulator Control Register . . . . . . . . . . . . . . . . . 202 Computer Operating Properly (COP) Watchdog Function ...
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... Extended Voltage Devices . . . . . . . . . . . . . . . . . . . . . 222 Functional Operating Range 223 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 224 Supply Currents and Power Dissipation . . . . . . . . . . . . . . . . . 225 MC68L11E9/E20 DC Electrical Characteristics . . . . . . . . . . . 226 MC68L11E9/E20 Supply Currents and Power Dissipation 227 Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 241 Interface Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 247 Table of Contents MC68HC11E Family — Rev. 4 MOTOROLA ...
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... Extended Voltage Device Ordering Information (3.0 Vdc to 5.5 Vdc 267 Appendix A. Development Support Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 Motorola M68HC11 E-Series Development Tools . . . . . . . . .270 EVS — Evaluation System . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 Motorola Modular Development System (MMDS11 271 SPGMR11 — Serial Programmer for M68HC11 MCUs . . . . .273 Appendix B. EVBU Schematic ...
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... Devices with PCbug11 on the M68HC711E9PGMR 323 EB188 — Enabling the Security Feature on M68HC811E2 Devices with PCbug11 on the M68HC711E9PGMR . . . . . . . . . 327 EB296 — Programming MC68HC711E9 Devices with PCbug11 and the M68HC11EVBU . . . . . . . . . . . . . . . . . . . 331 Technical Data 16 AN1060 EB184 EB188 EB296 Table of Contents MC68HC11E Family — Rev. 4 MOTOROLA ...
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... MC68HC11E Family — Rev. 4 MOTOROLA Title M68HC11 E-Series Block Diagram . . . . . . . . . . . . . . . . . . . . 26 Pin Assignments for 52-Pin PLCC and CLCC . . . . . . . . . . . . 28 Pin Assignments for 64-Pin QFP . . . . . . . . . . . . . . . . . . . . . . 29 Pin Assignments for 52-Pin TQFP . . . . . . . . . . . . . . . . . . . . . 30 Pin Assignments for 56-Pin SDIP Pin Assignments for 48-Pin DIP (MC68HC811E2 External Reset Circuit External Reset Circuit with Delay ...
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... SCI Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 149 Serial Communications Data Register (SCDR 152 Serial Communications Control Register 1 (SCCR1 153 Serial Communications Control Register 2 (SCCR2 154 Serial Communications Status Register (SCSR .155 Baud Rate Register (BAUD 157 List of Figures Page MC68HC11E Family — Rev. 4 MOTOROLA ...
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... MC68HC11E Family — Rev. 4 MOTOROLA Title SCI Baud Rate Generator Block Diagram . . . . . . . . . . . . . . 160 MC68HC(7)11E20 SCI Baud Rate Generator Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 161 Interrupt Source Resolution Within SCI . . . . . . . . . . . . . . . . 163 SPI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 SPI Transfer Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Serial Peripheral Control Register (SPCR .173 Serial Peripheral Status Register (SPSR) ...
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... WAIT Recovery from Interrupt Timing Diagram . . . . . . . . . . 233 Interrupt Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 Port Read Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Port Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Simple Input Strobe Timing Diagram . . . . . . . . . . . . . . . . . .237 (STRA Enables Output Buffer 239 EVBU Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 276 List of Figures Page MC68HC11E Family — Rev. 4 MOTOROLA ...
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... MC68HC11E Family — Rev. 4 MOTOROLA Title Port Signal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Reset Vector Comparison .50 Instruction Set .57 Hardware Mode Select Summary Write Access Limited Registers . . . . . . . . . . . . . . . . . . . . . . . .85 EEPROM Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 RAM Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 EEPROM Block Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 EEPROM Block Protect in MC68HC811E2 MCUs . . . . . . . . .100 EEPROM Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 COP Timer Rate Select ...
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... List of Tables Table 9-3 9-4 9-5 9-6 9-7 10-1 Converter Channel Assignments . . . . . . . . . . . . . . . . . . . . . . 216 10-2 A/D Converter Channel Selection 219 Technical Data 22 Title Timer Output Compare Actions . . . . . . . . . . . . . . . . . . . . . . .194 Timer Prescale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 RTI Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Pulse Accumulator Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Pulse Accumulator Edge Control . . . . . . . . . . . . . . . . . . . . . . 205 List of Tables Page MC68HC11E Family — Rev. 4 MOTOROLA ...
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... E-series MCUs is identical. A fully static design and high-density complementary metal-oxide semiconductor (HCMOS) fabrication process allow the E-series devices to operate at frequencies from 3 MHz to dc with very low power consumption. MC68HC11E Family — Rev. 4 MOTOROLA Section 1. General Description Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Random-access memory (RAM) ...
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... Four output compare (OC) channels – One additional channel, selectable as fourth IC or fifth OC 8-bit pulse accumulator Real-time interrupt circuit Computer operating properly (COP) watchdog system 38 general-purpose input/output (I/O) pins: – 16 bidirectional I/O pins – 11 input-only pins – 11 output-only pins General Description MC68HC11E Family — Rev. 4 MOTOROLA ...
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... See Differences among devices are noted in the table accompanying Figure MC68HC11E Family — Rev. 4 MOTOROLA Several packaging options: – 52-pin plastic-leaded chip carrier (PLCC) – 52-pin windowed ceramic leaded chip carrier (CLCC) – 52-pin plastic thin quad flat pack (TQFP) – ...
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... A/D CONVERTER CONTROL PORT D PORT E RAM ROM EPROM EEPROM 512 — — — 512 — — 512 512 12 K — 512 512 — 512 768 20 K — 512 768 — 512 256 — — 2048 MC68HC11E Family — Rev. 4 MOTOROLA ...
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... Contents 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.13.1 2.13.2 2.13.3 2.13.4 2.13.5 MC68HC11E Family — Rev. 4 MOTOROLA Section 2. Pin Descriptions Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 V and RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Crystal Driver and External Clock Input (XTAL and EXTAL E-Clock Output ( Interrupt Request (IRQ Non-Maskable Interrupt (XIRQ/V MODA and MODB (MODA/LIR and MODB/V V and STRA/AS ...
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... V applies only to devices with EPROM/OTPROM. PPE Figure 2-1. Pin Assignments for 52-Pin PLCC and CLCC Pin Descriptions 2-1, Figure 2-2, Figure 2-3, 46 PE5/AN5 PE1/AN1 45 44 PE4/AN4 43 PE0/AN0 42 PB0/ADDR8 PB1/ADDR9 41 40 PB2/ADDR10 PB3/ADDR11 39 PB4/ADDR12 38 37 PB5/ADDR13 36 PB6/ADDR14 PB7/ADDR15 35 34 PA0/IC3 MC68HC11E Family — Rev. 4 MOTOROLA ...
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... MC68HC11E Family — Rev. 4 MOTOROLA 1 PA0/IC3 PB7/ADDR15 5 PB6/ADDR14 6 PB5/ADDR13 7 PB4/ADDR12 8 M68HC11 E SERIES PB3/ADDR11 9 PB2/ADDR10 10 11 PB1/ADDR9 12 PB0/ADDR8 PE0/AN0 13 PE4/AN4 14 PE1/AN1 15 PE5/AN5 applies only to devices with EPROM/OTPROM. PPE Figure 2-2. Pin Assignments for 64-Pin QFP Pin Descriptions Pin Descriptions ...
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... PE0/AN0 10 11 PE4/AN4 12 PE1/AN1 PE5/AN5 applies only to devices with EPROM/OTPROM. PPE Figure 2-3. Pin Assignments for 52-Pin TQFP Pin Descriptions PD0/RxD 39 IRQ 38 XIRQ PPE 36 RESET 35 PC7/ADDR7/DATA7 PC6/ADDR6/DATA6 34 PC5/ADDR5/DATA5 33 32 PC4/ADDR4/DATA4 31 PC3/ADDR3/DATA3 PC2/ADDR2/DATA2 30 PC1/ADDR1/DATA1 29 28 PC0/ADDR0/DATA0 27 XTAL MC68HC11E Family — Rev. 4 MOTOROLA ...
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... MC68HC11E Family — Rev. 4 MOTOROLA MODB/V STBY 2 MODA/LIR 3 STRA/ STRB/R/W 6 EXTAL 7 XTAL 8 PC0/ADDR0/DATA0 9 PC1/ADDR1/DATA1 10 PC2/ADDR2/DATA2 11 PC3/ADDR3/DATA3 12 PC4/ADDR4/DATA4 13 PC5/ADDR5/DATA5 14 PC6/ADDR6/DATA6 M68HC11 E SERIES 15 PC7/ADDR7/DATA7 16 RESET 17 * XIRQ/V PPE 18 IRQ 19 PD0/RxD PD1/TxD 22 PD2/MISO 23 PD3/MOSI 24 PD4/SCK 25 PD5/ applies only to devices with EPROM/OTPROM. ...
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... Pin Descriptions PD5/ PD4/SCK PD3/MOSI 45 44 PD2/MISO PD1/TxD 43 42 PD0/RxD IRQ 41 40 XIRQ RESET 39 38 PC7/ADDR7/DATA7 37 PC6/ADDR6/DATA6 36 PC5/ADDR5/DATA5 35 PC4/ADDR4/DATA4 34 PC3/ADDR3/DATA3 PC2/ADDR2/DATA2 33 PC1/ADDR1/DATA1 32 PC0/ADDR0/DATA0 31 30 XTAL 29 EXTAL 28 STRB/R STRA/AS 25 MODA/LIR and the power MC68HC11E Family — Rev. 4 MOTOROLA ...
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... MCU as possible. Bypass requirements vary, depending on how heavily the MCU pins are loaded. MANUAL RESET SWITCH 4.7 k OPTIONAL POWER-ON DELAY AND MANUAL RESET SWITCH Figure 2-7. External Reset Circuit with Delay MC68HC11E Family — Rev. 4 MOTOROLA RESET MC34(0/1)64 GND 3 Figure 2-6 ...
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... EEPROM array is not being used. Presently, there are several economical ways to solve this problem. For example, two good external components for LVI reset are: 1. The Seiko S0854HN (or other S805 series devices): 2. The Motorola MC34064: Refer to Technical Data 34 falls below the minimum operating voltage level, reset must DD — ...
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... In all cases, use caution around the oscillator pins. Load capacitances shown in the oscillator circuit are specified by the crystal manufacturer and should include all stray layout capacitances. Refer to MC68HC11E Family — Rev. 4 MOTOROLA Crystal Driver and External Clock Input (XTAL and EXTAL) Figure 2-8 and Figure 2-9 ...
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... NOTE: IRQ must be configured for level-sensitive operation if there is more than one source of IRQ interrupt. Technical Data PPE . XIRQ is often used as a power loss detect interrupt. DD Pin Descriptions MC68HC11E Family — Rev. 4 MOTOROLA ...
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... V allows RAM contents to be retained without V MCU. Reset must be driven low before V low until V MC68HC11E Family — Rev. 4 MOTOROLA MODA and MODB (MODA/LIR and MODB/VSTBY) is the input for the 12-volt nominal programming voltage required Single-chip mode Expanded mode ...
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... single-chip mode, STRA performs an input handshake (strobe input) function. In the expanded multiplexed mode, AS provides an address strobe function. Section 4. Operating Modes and On-Chip for further information. Pin Descriptions . RL and Memory. Section 6. Parallel MC68HC11E Family — Rev. 4 MOTOROLA ...
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... Bits DDRA7 and DDRA3 located in PACTL register control data direction for PA7 and PA3, respectively. All other port A pins are fixed as either input or output. MC68HC11E Family — Rev. 4 MOTOROLA Section 4. Operating Modes and for more information about IRVNE (internal read Table 2-1 ...
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... PA2/IC1 PA3/OC5/IC4/OC1 PA4/OC4/OC1 PA5/OC3/OC1 PA6/OC2/OC1 PA7/PAI/OC1 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR0/DATA0 ADDR1/DATA1 ADDR2/DATA2 ADDR3/DATA3 ADDR4/DATA4 ADDR5/DATA5 ADDR6/DATA6 ADDR7/DATA7 PD0/RxD PD1/TxD PD2/MISO PD3/MOSI PD4/SCK PD5/SS AS R/W PE0/AN0 PE1/AN1 PE3/AN2 PE3/AN3 PE4/AN4 PE5/AN5 PE6/AN6 PE7/AN7 MC68HC11E Family — Rev. 4 MOTOROLA ...
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... During each MCU cycle, bits 15–8 of the address bus are output on the PB7–PB0 pins. The PORTB register is treated as an external address in expanded modes. MC68HC11E Family — Rev. 4 MOTOROLA Section 6. Parallel Input/Output (I/O) Pin Descriptions Pin Descriptions Port Signals Ports ...
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... When a port C bit is at logic level driven low by the N-channel driver. When a port C bit is at logic level 1, the associated pin has high-impedance, as neither the N-channel nor the P-channel devices are active. for additional information about port C Pin Descriptions Section 6. MC68HC11E Family — Rev. 4 MOTOROLA ...
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... MC68HC11E Family — Rev. 4 MOTOROLA PD0 is the receive data input (RxD) signal for the SCI. PD1 is the transmit data output (TxD) signal for the SCI. PD5–PD2 are dedicated to the SPI: – ...
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... Pin Descriptions Technical Data 44 MC68HC11E Family — Rev. 4 Pin Descriptions MOTOROLA ...
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... MC68HC11E Family — Rev. 4 MOTOROLA Section 3. Central Processor Unit (CPU) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Accumulators A, B, and Index Register X (IX Index Register Y (IY Stack Pointer (SP Program Counter (PC .50 Condition Code Register (CCR Carry/Borrow ( Overflow ( Zero ( .51 Negative ( Interrupt Mask (I) ...
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... The seven registers, discussed in the following paragraphs, are shown in Technical Data 46 Central processor unit (CPU) architecture Data types Addressing modes Instruction set Special operations such as subroutine calls and interrupts Central Processor Unit (CPU) Figure 3-1. MC68HC11E Family — Rev. 4 MOTOROLA ...
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... For some instructions, these two accumulators are treated as a single double-byte (16-bit) accumulator called accumulator D. Although most instructions can use accumulators interchangeably, these exceptions apply: • • MC68HC11E Family — Rev. 4 MOTOROLA ...
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... The add, subtract, and compare instructions associated with both A and B (ABA, SBA, and CBA) only operate in one direction, making it important to plan ahead to ensure that the correct operand is in the correct accumulator. for further information. Figure 3-2 Central Processor Unit (CPU summary of SP MC68HC11E Family — Rev. 4 MOTOROLA ...
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... When the subroutine is finished, a return-from-subroutine (RTS) instruction is executed. The RTS pulls the previously stacked return address from the stack and loads it into the program counter. Execution then continues at this recovered return address. MC68HC11E Family — Rev. 4 MOTOROLA RTI, RETURN FROM INTERRUPT STACK 7 0 SP– ...
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... See Normal Test or Boot Technical Data 50 Table 3-1. Table 3-1. Reset Vector Comparison Mode POR or RESET Pin $FFFE, F $BFFE, F Central Processor Unit (CPU) Clock Monitor COP Watchdog $FFFC, D $FFFA, B $BFFC, D $BFFA, B MC68HC11E Family — Rev. 4 MOTOROLA ...
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... A few operations (INX, DEX, INY, and DEY) affect the Z bit and no other condition flags. For these operations, only = and MC68HC11E Family — Rev. 4 MOTOROLA Five condition code indicators ( and H), Two interrupt masking bits (IRQ and XIRQ) A stop disable bit (S) ...
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... RTI instruction is normally executed, causing the registers to be restored to the values that were present before the interrupt occurred. The X interrupt mask bit is set only by Technical Data 52 Section 5. Resets and Central Processor Unit (CPU) Interrupts. MC68HC11E Family — Rev. 4 MOTOROLA ...
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... CPU. Several opcodes are required to provide each instruction with a range of addressing capabilities. Only 256 opcodes would be available if the range of values were restricted to the number able to be expressed in 8-bit binary numbers. MC68HC11E Family — Rev. 4 MOTOROLA Central Processor Unit (CPU) Central Processor Unit (CPU) Data Types Technical Data ...
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... There are 2-, 3-, and 4- (if prebyte is required) byte immediate instructions. The effective address is the address of the byte following the instruction. Technical Data 54 Immediate Direct Extended Indexed Inherent Relative Central Processor Unit (CPU) MC68HC11E Family — Rev. 4 MOTOROLA ...
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... Operations that use only the index registers or accumulators, as well as control instructions with no arguments, are included in this addressing mode. These are 1- or 2-byte instructions. MC68HC11E Family — Rev. 4 MOTOROLA Central Processor Unit (CPU) Central Processor Unit (CPU) Addressing Modes Technical Data ...
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... For each instruction, the table shows the operand construction, the number of machine code bytes, and execution time in CPU E-clock cycles. Technical Data 56 Table 3-2, which shows all the M68HC11 instructions in all Central Processor Unit (CPU) MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 57
... Arithmetic Shift Right b7 ASRA Arithmetic Shift Right A b7 ASRB Arithmetic Shift Right B b7 BCC (rel) Branch if Carry ? Clear BCLR (opr) Clear Bit(s) M • (mm) (msk) MC68HC11E Family — Rev. 4 MOTOROLA Addressing Instruction Mode Opcode A INH 1B IX INH 3A IY INH IMM 89 A ...
Page 58
... MC68HC11E Family — Rev. 4 MOTOROLA C — — — — — — — — — — — — — — — — — — — — ...
Page 59
... M with Memory FDIV Fractional Divide IDIV Integer Divide INC (opr) Increment Memory Byte INCA Increment Accumulator A MC68HC11E Family — Rev. 4 MOTOROLA Addressing Instruction Mode Opcode B IMM C1 B DIR D1 B EXT F1 B IND IND ...
Page 60
... MC68HC11E Family — Rev. 4 MOTOROLA C — — — — — — — — — — — — ...
Page 61
... C b7 ROLB Rotate Left ROR (opr) Rotate Right b7 RORA Rotate Right A b7 RORB Rotate Right B b7 RTI Return from See Figure 3–2 Interrupt MC68HC11E Family — Rev. 4 MOTOROLA Addressing Instruction Mode Opcode B INH INH INH 3D M EXT ...
Page 62
... MC68HC11E Family — Rev. 4 MOTOROLA C — 1 — — — — — — — — — — — — ...
Page 63
... Is pushed onto stack • Boolean AND + Arithmetic addition symbol except where used as inclusive-OR symbol in Boolean formula Exclusive-OR Multiply : Concatenation – Arithmetic subtraction symbol or negation symbol (two’s complement) MC68HC11E Family — Rev. 4 MOTOROLA Addressing Instruction Mode Opcode Operand INH 00 A INH 07 EXT 7D ...
Page 64
... Central Processor Unit (CPU) Technical Data 64 Central Processor Unit (CPU) MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 65
... MC68HC11E Family — Rev. 4 MOTOROLA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Single-Chip Mode Expanded Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Bootstrap Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Memory Map RAM and Input/Output Mapping Mode Selection System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 System Configuration Register . . . . . . . . . . . . . . . . . . . . 86 RAM and I/O Mapping Register . . . . . . . . . . . . . . . . . . . .89 System Configuration Options Register . . . . . . . . . . . . . . 91 EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Programming an Individual EPROM Address . . . . . . . . . . . 93 Programming the EPROM with Downloaded Data ...
Page 66
... Expanded mode, however, allows access to external memory. Bootstrap, a variation of the single-chip mode special mode that executes a bootloader program in an internal bootstrap ROM. Test is a special mode that allows privileged access to internal resources. Operating Modes and On-Chip Memory MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 67
... E clock and the inverted R/W signal. 4.3.3 Test Mode Test mode, a variation of the expanded mode, is primarily used during Motorola’s internal production testing; however accessible for programming the configuration (CONFIG) register, programming calibration data into electrically erasable, programmable read-only memory (EEPROM), and supporting emulation and debugging during development. MC68HC11E Family — ...
Page 68
... Operating Modes and On-Chip Memory ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 HC373 Q1 D1 ADDR7 D2 Q2 ADDR6 D3 Q3 ADDR5 Q4 D4 ADDR4 Q5 D5 ADDR3 D6 Q6 ADDR2 Q7 D7 ADDR1 Q8 D8 ADDR0 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 69
... INIT register. If RAM and registers are mapped to the same boundary, the first 64 bytes of RAM will be inaccessible. Refer to assignments. Reset states shown are for single-chip mode only. MC68HC11E Family — Rev. 4 MOTOROLA 4-4, Figure 4-5, and Figure 4-4, Figure ...
Page 70
... EXT B600 512 BYTES EEPROM B7FF BOOT BF00 EXT ROM BFFF NORMAL FFC0 MODES INTERRUPT FFFF VECTORS SPECIAL TEST Operating Modes and On-Chip Memory BFC0 SPECIAL MODES INTERRUPT VECTORS BFFF BFC0 SPECIAL MODES INTERRUPT VECTORS BFFF MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 71
... EXT $B600 EXT $D000 $FFFF SINGLE EXPANDED CHIP * 20 Kbytes ROM/EPROM are contained in two segments of 8 Kbytes and 12 Kbytes each. Figure 4-5. Memory Map for MC68HC(7)11E20 MC68HC11E Family — Rev. 4 MOTOROLA EXT EXT EXT BOOTSTRAP SPECIAL TEST EXT EXT EXT EXT BOOTSTRAP ...
Page 72
... INTERRUPT VECTORS BFFF BFFF 2048 BYTES EEPROM F800 NORMAL FFC0 MODES INTERRUPT FFFF FFFF VECTORS PA4 PA3 PA2 PA1 OIN PLS EGA Reserved U = Unaffected MC68HC11E Family — Rev. 4 MOTOROLA Bit 0 PA0 I R INVB 1 ...
Page 73
... See page 138. Port E Data Register $100A (PORTE) See page 139. Timer Compare Force $100B Register (CFORC) See page 190. Figure 4-7. Register and Control Bit Assignments (Sheet MC68HC11E Family — Rev. 4 MOTOROLA Bit Read: PC7 PC6 PC5 Write: Reset: Read: ...
Page 74
... Bit 3 Bit 2 Bit Bit 11 Bit 10 Bit 9 Bit 4 Bit 3 Bit 2 Bit 1 Bit 11 Bit 10 Bit 9 Bit 4 Bit 3 Bit 2 Bit 1 Bit 11 Bit 10 Bit Reserved U = Unaffected MC68HC11E Family — Rev. 4 MOTOROLA Bit Bit 8 0 Bit 0 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 ...
Page 75
... Timer Output Compare 4 $101C Register High (TOC4H) See page 189. Timer Output Compare 4 $101D Register Low (TOC4L) See page 189. Figure 4-7. Register and Control Bit Assignments (Sheet MC68HC11E Family — Rev. 4 MOTOROLA Bit Read: Bit 7 Bit 6 Bit 5 Write: Reset: ...
Page 76
... OC4I I4/O5I IC1I IC2I I4/O5F IC1F IC2F PAII PR1 PAIF DDRA3 I4/O5 RTR1 Reserved U = Unaffected MC68HC11E Family — Rev. 4 MOTOROLA Bit 0 Bit 8 1 Bit 0 1 OL5 0 EDG3A 0 IC3I 0 IC3F 0 PR0 0 0 RTR0 0 ...
Page 77
... See page 154. Serial Communications Status $102E Register (SCSR) See page 155. 1. SCP2 adds 39 to SCI prescaler and is present only in MC68HC(7)11E20. Figure 4-7. Register and Control Bit Assignments (Sheet MC68HC11E Family — Rev. 4 MOTOROLA Bit Read: Bit 7 Bit 6 Bit 5 ...
Page 78
... Bit 3 Bit 2 Bit 1 Bit 4 Bit 3 Bit 2 Bit 1 Bit 4 Bit 3 Bit 2 Bit 1 Bit 4 Bit 3 Bit 2 Bit 1 BPRT3 BPRT2 BPRT1 EXROW Reserved U = Unaffected MC68HC11E Family — Rev. 4 MOTOROLA Bit 0 R0/T0 CA Bit 0 Bit 0 Bit 0 Bit 0 BPRT0 1 PGM 0 R ...
Page 79
... See page 87. 1. Can be written only once in first 64 cycles out of reset in normal modes or at any time during special modes. 2. MC68HC711E9 only 3. MC68HC811E2 only Figure 4-7. Register and Control Bit Assignments (Sheet MC68HC11E Family — Rev. 4 MOTOROLA Bit Read: ...
Page 80
... V to maintain RAM contents, reset must be held low whenever V is below normal operating level. Refer to Interrupts. Operating Modes and On-Chip Memory pin can supply RAM STBY pin may STBY . used DD STBY DD Section 5. Resets and MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 81
... CONFIG) determine the location of the 2048 bytes of EEPROM and are present only on the MC68HC811E2. Refer to 4.4.3.1 System Configuration Register MC68HC811E2 CONFIG register. EEPROM can be programmed or erased by software and an on-chip charge pump, allowing EEPROM changes using the single V MC68HC11E Family — Rev. 4 MOTOROLA V DD MAX 690 V DD ...
Page 82
... Reset Mode MODA 1 0 Single chip 1 1 Expanded 0 0 Bootstrap 0 1 Special test Section 5. Resets and Operating Modes and On-Chip Memory Control Bits in HPRIO (Latched at Reset) RBOOT SMOD MDA Interrupts. MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 83
... MODA pin at the rising edge of reset. These two bits can be read at any time. They can be written anytime in special modes. MDA can be written only once in normal modes. SMOD cannot be set once it has been cleared. MC68HC11E Family — Rev. 4 MOTOROLA $103C Bit ...
Page 84
... IRVNE Out E Clock Out of Reset of Reset Section 5. Resets and Operating Modes and On-Chip Memory IRV Out IRVNE IRVNE Can of Reset Affects Only Be Written Off E Once Off IRV Once Off E Once On IRV Once Interrupts. MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 85
... Highest priority I-bit interrupt and $x03C miscellaneous (HPRIO) $x03D RAM and I/O map register (INIT) MC68HC11E Family — Rev. 4 MOTOROLA lists registers that can be written only once after reset or that Register Name Operating Modes and On-Chip Memory Operating Modes and On-Chip Memory Memory Map ...
Page 86
... To take full advantage of the MCU’s functionality, customers can program the CONFIG register in bootstrap mode. This can be accomplished by setting the mode pins to logic 0 and downloading a small program to internal RAM. For more information, Motorola application note AN1060 entitled included at the back of this document. The downloadable talker will consist of: • ...
Page 87
... U indicates a previously programmed bit. U(L) indicates that the bit resets to the logic level held in the latch prior to reset, but the function of COP is controlled by the DISR bit in TEST1 register. Figure 4-11. MC68HC811E2 System Configuration Register (CONFIG) MC68HC11E Family — Rev. 4 MOTOROLA $103F Bit ...
Page 88
... Interrupts. MC68HC11E Family — Rev. 4 MOTOROLA 4-3. ...
Page 89
... RAM in the memory map. RAM can be positioned at the beginning of any 4-Kbyte page in the memory map initialized to address $0000 out of reset. Refer to MC68HC11E Family — Rev. 4 MOTOROLA 0 = ROM disabled from the memory map 1 = ROM present in the memory map 0 = EEPROM removed from the memory map ...
Page 90
... MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 91
... EEPROM use. CSEL also selects the clock source for the A/D converter, a function discussed in IRQE — Configure IRQ for Edge-Sensitive Only Operation Bit Refer to DLY — Enable Oscillator Startup Delay Bit MC68HC11E Family — Rev. 4 MOTOROLA $1039 Bit (1) ADPU ...
Page 92
... The MC68HC711E9 devices contain 12 Kbytes of on-chip EPROM (OTPROM in non-windowed package). The MC68HC711E20 has 20 Kbytes of EPROM (OTPROM in non-windowed package). The MC68HC711E32 has 32 Kbytes of EPROM (OTPROM in non-windowed package). Operating Modes and On-Chip Memory Interrupts. 15 before it enters the COP Interrupts. ). Normal programming is PPE MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 93
... This example applies to all devices with EPROM/OTPROM except for the MC68HC711E20. This example applies only to MC68HC711E20. MC68HC11E Family — Rev. 4 MOTOROLA Programming an individual EPROM address Programming the EPROM with downloaded data The ROMON bit set in the CONFIG register The 12-volt nominal programming voltage present on the ...
Page 94
... EPROM array. After the last byte to be programmed is sent and the corresponding verification data is returned, the programming operation is terminated by resetting the MCU. For more information, Motorola application note AN1060 entitled M68HC11 Bootstrap Mode document. 4.5.3 EPROM and EEPROM Programming Control Register ...
Page 95
... ELAT can be written any time except when EPGM = 1; then the write to ELAT is disabled. For the MC68HC711E9: BYTE — Byte/Other EEPROM Erase Mode Bit Refer to ROW — Row/All EEPROM Erase Mode Bit Refer to MC68HC11E Family — Rev. 4 MOTOROLA $103B Bit (1) ODD EVEN ...
Page 96
... EXCOL Unimplemented Figure 4-15. MC68HC711E20 EPROM Programming Control Register (EPROG EPROM array configured for normal programming 1 = Program two bytes with the same data Operating Modes and On-Chip Memory EXROW MC68HC11E Family — Rev. 4 MOTOROLA Bit 0 PGM 0 ...
Page 97
... These bits allow selection of either gate stress or drain stress test modes. They can be read and written only in special modes and always read 0 in normal modes. MC68HC11E Family — Rev. 4 MOTOROLA 0 = EPROM/OTPROM address and data bus configured for normal reads 1 = EPROM/OTPROM address and data bus configured for ...
Page 98
... OPTION register is 0, the E clock is Technical Data Programming voltage to EPROM array disconnected 1 = Programming voltage to EPROM array connected uses MOS capacitors, which are relatively small in DD and the frequency of the driving clock. The DD Operating Modes and On-Chip Memory MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 99
... BPROT can be written repeatedly. Address ranges for protected areas of EEPROM differ significantly for the MC68HC811E2. Refer to Address: Read: Write: Reset: Bits [7:5] — Unimplemented Always read 0 MC68HC11E Family — Rev. 4 MOTOROLA Figure $1035 Bit PTCON Unimplemented Figure 4-16 ...
Page 100
... EE[3:0] in CONFIG register. Refer to Figure 4-13. Operating Modes and On-Chip Memory Table 4-6 and Table 4-7. Block Size 32 bytes 64 bytes 128 bytes 288 bytes Block Size (1) 512 bytes (1) 512 bytes (1) 512 bytes (1) 512 bytes MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 101
... For MC68HC711E9, ELAT and EELAT are mutually exclusive and cannot both equal 1. BYTE — Byte/Other EEPROM Erase Mode Bit This bit overrides the ROW bit. ROW — Row/All EEPROM Erase Mode Bit If BYTE is 1, ROW has no meaning. MC68HC11E Family — Rev. 4 MOTOROLA $103B Bit (1) ODD ...
Page 102
... STAB $103B Turn on programming voltage JSR DLY10 Delay 10 ms CLR $103B Turn off high voltage and set to READ mode Operating Modes and On-Chip Memory Action Bulk erase (entire array) Row erase (16 bytes) Byte erase Byte erase MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 103
... EEPROM Bulk Erase This is an example of how to bulk erase the entire EEPROM. The CONFIG register is not affected in this example. 4.6.1.4 EEPROM Row Erase This example shows how to perform a fast erase of large sections of EEPROM. MC68HC11E Family — Rev. 4 MOTOROLA BULKE LDAB #$06 EELAT = 1, ERASE = 1 STAB $103B ...
Page 104
... STAB 0,X Write any data to address to be erased LDAB #$17 BYTE = 1, ERASE = 1, EELAT = 1, EPGM = 1 STAB $103B Turn on high voltage JSR DLY10 Delay 10 ms CLR $103B Turn off high voltage and set to READ mode Operating Modes and On-Chip Memory MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 105
... For further information, these engineering bulletins have been included at the back of this data book: • • MC68HC11E Family — Rev. 4 MOTOROLA Section 12. Mechanical Data for the exact part number. EB183 — Enabling the Security Feature on the MC68HC711E9 Devices with PCbug11 on the M68HC711E9PGMR EB188 — ...
Page 106
... Operating Modes and On-Chip Memory Technical Data 106 Operating Modes and On-Chip Memory MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 107
... MC68HC11E Family — Rev. 4 MOTOROLA Section 5. Resets and Interrupts Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Resets 108 Power-On Reset (POR 109 External Reset (RESET 109 Computer Operating Properly (COP) Reset . . . . . . . . . . . . 110 Clock Monitor Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 System Configuration Options Register . . . . . . . . . . . . . . . 112 Configuration Control Register . . . . . . . . . . . . . . . . . . . . . . 113 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Central Processor Unit (CPU) ...
Page 108
... Technical Data 108 Low-Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 Power-on reset (POR) External reset (RESET) Computer operating properly (COP) reset Clock monitor reset Resets and Interrupts MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 109
... Do not connect an external resistor capacitor (RC) power-up delay circuit to the reset pin of M68HC11 devices because the circuit charge time constant can cause the device to misinterpret the type of reset that occurred. MC68HC11E Family — Rev. 4 MOTOROLA generates a power-on reset (POR), which is DD (internal clock cycle) delay after cyc cyc Circuit ...
Page 110
... XTAL = 8.0 MHz XTAL = 12.0 MHz Timeout – 0 ms, + 16.4 ms – 0 ms, + 10.9 ms 16.384 ms 65.536 ms 262.14 ms 1.049 s 2.0 MHz Resets and Interrupts Table 5-1. After reset, these XTAL = 16.0 MHz Timeout Timeout – 0 ms, + 8.2 ms 10.923 ms 8.19 ms 43.691 ms 32.8 ms 174.76 ms 131 ms 699.05 ms 524 ms 3.0 MHz 4.0 MHz MC68HC11E Family — Rev. 4 MOTOROLA 15 ...
Page 111
... An E-clock frequency below 10 kHz is detected as a clock monitor error. An E-clock frequency of 200 kHz or more prevents clock monitor errors. Using the clock monitor function when the E-clock is below 200 kHz is not recommended. MC68HC11E Family — Rev. 4 MOTOROLA $103A Bit ...
Page 112
... Section 10. Analog-to-Digital (A/D) Section 10. Analog-to-Digital (A/ IRQ is configured for level-sensitive operation IRQ is configured for edge-sensitive-only operation. Section 4. Operating Modes and On-Chip Memory Resets and Interrupts (1) (1) CME CR1 Converter. Converter. Converter. MC68HC11E Family — Rev. 4 MOTOROLA Bit 0 (1) CR0 0 and ...
Page 113
... Read: Write: Reset: EE[3:0] — EEPROM Mapping Bits EE[3:0] apply only to MC68HC811E2. Refer to Modes and On-Chip NOSEC — Security Mode Disable Bit Refer to MC68HC11E Family — Rev. 4 MOTOROLA 0 = Clock monitor circuit disabled 1 = Slow or stopped clocks cause reset Table 5-1 $103F Bit EE3 EE2 ...
Page 114
... Table 5-2. Reset Cause, Reset Vector, and Operating Mode Cause of Reset POR or RESET pin Clock monitor failure COP Watchdog Timeout Resets and Interrupts Memory. Memory. 5-2. Normal Mode Special Test Vector or Bootstrap $FFFE, FFFF $BFFE, $BFFF $FFFC, FFFD $BFFC, $BFFD $FFFA, FFFB $BFFA, $BFFB MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 115
... The I4/O5 bit in the PACTL register is cleared to configure the I4/O5 function as OC5; however, the OM5:OL5 control bits in the TCTL1 register are clear so OC5 does not control the PA3 pin. MC68HC11E Family — Rev. 4 MOTOROLA Memory. Resets and Interrupts Resets and Interrupts Effects of Reset Section 4 ...
Page 116
... The RDRF, IDLE, OR, NF, FE, PF, and RAF receive-related status bits in the SCI control register 2 (SCCR2) are cleared. Technical Data 116 Resets and Interrupts MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 117
... Resets and interrupts have a hardware priority that determines which reset or interrupt is serviced first when simultaneous requests occur. Any maskable interrupt can be given priority over other maskable interrupts. MC68HC11E Family — Rev. 4 MOTOROLA Section 4. Operating Modes and On-Chip Memory Resets and Interrupts Resets and Interrupts ...
Page 118
... Any one of these interrupts can be assigned the highest maskable interrupt priority by writing the appropriate value to the PSEL bits in the HPRIO register. Otherwise, the priority arrangement remains the same. An interrupt that is assigned highest priority is still subject to global Technical Data 118 Figure 5-7) Resets and Interrupts MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 119
... At all other times this bit is clear and cannot be written. Refer to for more information. SMOD — Special Mode Select Bit This bit reflects the inverse of the MODB input pin at the rising edge of reset. Refer to Memory MC68HC11E Family — Rev. 4 MOTOROLA $103C Bit Read: (1) (1) ...
Page 120
... Timer input capture Timer output compare Timer output compare Timer output compare Timer output compare Timer input capture 4/output compare 5 Resets and Interrupts Section 4. for more information. MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 121
... XIRQ pin. Refer to assignments for each source. Vector Address FFC0, C1 – FFD4, D5 Reserved MC68HC11E Family — Rev. 4 MOTOROLA Table 5-4, which shows the interrupt sources and vector Table 5-4. Interrupt and Reset Vector Assignments Interrupt Source FFD6, D7 SCI serial system • ...
Page 122
... Section 3. Central Processor Unit Table 5-5. Stacking Order on Entry to Interrupts Memory Location SP SP–1 SP–2 SP–3 SP–4 SP–5 SP–6 SP–7 SP–8 Resets and Interrupts Table 5-5. After the CCR (CPU). CPU Registers PCL PCH IYL IYH IXL IXH ACCA ACCB CCR MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 123
... The stack grows until the system crashes. The illegal opcode trap mechanism works for all unimplemented opcodes on all four opcode map pages. The address stacked as the MC68HC11E Family — Rev. 4 MOTOROLA Resets and Interrupts Resets and Interrupts Interrupts ...
Page 124
... SCI subsystem. Technical Data 124 and Figure 5-6 illustrate the reset and interrupt process. illustrates how the CPU begins from a reset and how interrupt Figure 5-5 and illustrates interrupt priorities. Resets and Interrupts Figure 5 expansion Figure 5-7 MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 125
... DELAY 4064 E CYCLES LOAD PROGRAM COUNTER WITH CONTENTS OF $FFFE, $FFFF (VECTOR FETCH) Figure 5-5. Processing Flow Out of Reset (Sheet MC68HC11E Family — Rev. 4 MOTOROLA EXTERNAL RESET CLOCK MONITOR FAIL (WITH CME = 1) LOAD PROGRAM COUNTER WITH CONTENTS OF $FFFC, $FFFD (VECTOR FETCH) ...
Page 126
... RESTORE CPU REGISTERS EXECUTE THIS FROM STACK INSTRUCTION 1A Resets and Interrupts STACK CPU REGISTERS STACK CPU REGISTERS ANY N INTERRUPT PENDING? Y SET BIT I IN CCR RESOLVE INTERRUPT PRIORITY AND FETCH VECTOR FOR HIGHEST PENDING SOURCE SEE FIGURE 5–2 MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 127
... HIGHEST PRIORITY INTERRUPT ? NO IRQ ? NO RTII = IC1I = IC2I = IC3I = OC1I = Figure 5-6. Interrupt Priority Resolution (Sheet MC68HC11E Family — Rev. 4 MOTOROLA YES YES XIRQ PIN LOW ? NO YES YES YES YES REAL-TIME INTERRUPT ? NO YES YES TIMER IC1F ? NO YES ...
Page 128
... N Y FLAG FETCH VECTOR PAOVF = 1 $FFDC, $FFDD N Y FLAG FETCH VECTOR PAIF = 1? $FFDA, $FFDB N FLAGS Y FETCH VECTOR SPIF = 1? OR $FFD8, $FFD9 MODF = 1? N FETCH VECTOR $FFD6, $FFD7 FETCH VECTOR $FFF2, $FFF3 Resets and Interrupts 2B END MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 129
... Wait mode suspends processing and reduces power consumption to an intermediate level. Stop mode turns off all on-chip clocks and reduces power consumption to an absolute minimum while retaining the contents of the entire RAM array. MC68HC11E Family — Rev. 4 MOTOROLA Y RIE = ...
Page 130
... To exit stop and resume normal processing, a logic low level must be applied to one of the external interrupts (IRQ or XIRQ the RESET pin. A pending edge-triggered IRQ can also bring the CPU out of stop. Technical Data 130 Resets and Interrupts MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 131
... DLY control bit, but does not apply to a reset while the clocks are running. MC68HC11E Family — Rev. 4 MOTOROLA power is maintained. The CPU state and I/O pin levels are static and Resets and Interrupts Resets and Interrupts ...
Page 132
... Resets and Interrupts Technical Data 132 Resets and Interrupts MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 133
... I/O lines, depending on the operating mode. Refer to summary of the ports and their shared functions. Port Port A Port B Port C Port D Port E MC68HC11E Family — Rev. 4 MOTOROLA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Port 134 Port 136 Port 136 Port 138 Port 139 Handshake Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Parallel I/O Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Table 6-1 ...
Page 134
... PAI OC2 OC3 OC4 OC1 OC1 OC1 OC1 I = Indeterminate after reset Figure 6-1. Port A Data Register (PORTA) Parallel Input/Output (I/O) Ports Bit 0 PA3 PA2 PA1 PA0 IC4/OC5 IC1 IC2 IC3 OC1 — — — MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 135
... DDRA3 — Data Direction for Port A Bit 3 This bit is overridden if an output compare function is configured to control the PA3 pin. I4/O5 — Input Capture 4/Output Compare 5 Bit Refer to RTR[1:0] — RTI Interrupt Rate Select Bits Refer to MC68HC11E Family — Rev. 4 MOTOROLA $1026 Bit DDRA7 PAEWN PAMOD ...
Page 136
... Figure 6-4. Port C Data Register (PORTC) Parallel Input/Output (I/O) Ports Bit 0 PB3 PB2 PB1 PB0 ADDR11 ADDR10 ADDR9 ADDR8 Bit 0 PC3 PC2 PC1 PC0 ADDR3 ADDR2 ADDR1 ADDR0 DATA3 DATA2 DATA1 DATA0 MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 137
... STAF flag (following a read of PIOC with STAF set). Address: Read: Write: Reset: DDRC[7:0] — Port C Data Direction Bits In handshake output mode, DDRC bits select the 3-stated output option (DDCx = 1). MC68HC11E Family — Rev. 4 MOTOROLA $1005 Bit PCL7 PCL6 PCL5 Indeterminate after reset Figure 6-5 ...
Page 138
... Unimplemented Figure 6-8. Port D Data Direction Register (DDRD Input 1 = Output Parallel Input/Output (I/O) Ports Bit 0 PD3 PD2 PD1 PD0 PD3 PD2 PD1 PD0 MOSI MISO Tx RxD Bit 0 DDRD3 DDRD2 DDRD1 DDRD0 MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 139
... C latch (PORTCL) register on each assertion of the STRA input. STRA edge select, flag, and interrupt enable bits are located in the PIOC register. Any or all of the port C lines can still be used as general-purpose I/O while in strobed input mode. MC68HC11E Family — Rev. 4 MOTOROLA $100A Bit ...
Page 140
... STRB signal. The 3-state mode variation does not allow part of port used for static inputs while other port C pins are being used for handshake outputs. Refer to the Register Technical Data 140 for further information. Parallel Input/Output (I/O) Ports 6.9 Parallel I/O Control MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 141
... STAI — Strobe A Interrupt Enable Mask Bit CWOM — Port C Wired-OR Mode Bit (affects all eight port C pins customary to have an external pullup resistor on lines that are driven by open-drain devices. HNDS — Handshake Mode Bit MC68HC11E Family — Rev. 4 MOTOROLA Table 6-2 shows a summary of handshake operations. $1002 Bit 7 6 ...
Page 142
... Pulsed handshake (Strobe B pulses high for two E-clock cycles STRA falling edge selected, high level activates port C outputs (output handshake STRA rising edge selected, low level activates port C outputs (output handshake Active level is logic Active level is logic 1. Parallel Input/Output (I/O) Ports MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 143
... PORTCL Full- Read output PIOC with hand- STAF = 1 1 shake then write mode PORTCL MC68HC11E Family — Rev. 4 MOTOROLA Table 6-2. Parallel I/O Control PLS EGA STRB active level STRB active pulse STRB 0 active level ...
Page 144
... Parallel Input/Output (I/O) Ports Technical Data 144 Parallel Input/Output (I/O) Ports MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 145
... M68HC11 E series of microcontrollers. It has a standard non-return-to-zero (NRZ) format (one start bit , eight or nine data bits, and one stop bit). Several baud rates are available. The SCI MC68HC11E Family — Rev. 4 MOTOROLA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Transmit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 Receive Operation ...
Page 146
... TxD as long as transmission is in Technical Data 146 7.8.5 Baud Rate Register. message of each character consists of a start bit, a character of eight or nine data bits, and a stop bit. some multiple number of frames Serial Communications Interface (SCI) Figure 7-8 MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 147
... BIT Tx SHIFT REGISTER H ( SCCR1 SCI CONTROL 1 SCI Rx SCI INTERRUPT REQUESTS REQUEST Note: Refer to Figure B-1. EVBU Schematic Diagram Figure 7-1. SCI Transmitter Block Diagram MC68HC11E Family — Rev. 4 MOTOROLA WRITE ONLY SCDR Tx BUFFER FORCE PIN DIRECTION (OUT) TRANSMITTER CONTROL LOGIC ...
Page 148
... During idle-line wakeup, a sleeping receiver awakens as soon as the RxD line becomes idle. In the address-mark wakeup, logic 1 in the most significant bit (MSB character wakes up all sleeping receivers. Technical Data 148 Idle-line wakeup Address-mark wakeup Serial Communications Interface (SCI) Figure 7-2. MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 149
... PIN BUFFER PD0 AND CONTROL RxD SCCR1 SCI CONTROL 1 SCI Tx SCI INTERRUPT REQUESTS REQUEST Note: Refer to Figure B-1. EVBU Schematic Diagram Figure 7-2. SCI Receiver Block Diagram MC68HC11E Family — Rev. 4 MOTOROLA 16 DATA RECOVERY DISABLE DRIVER RE M WAKEUP LOGIC SCSR SCI STATUS 1 RDRF RIE ...
Page 150
... RWU gets cleared before the stop bit for that frame is serially received. This type of wakeup allows messages to include gaps of idle time, unlike the idle-line method, but Technical Data 150 Serial Communications Interface (SCI) MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 151
... SCDR until it is cleared. The FE bit is cleared when the SCSR is read (with FE equal to 1) followed by a read of the SCDR. MC68HC11E Family — Rev. 4 MOTOROLA Serial Communications Interface (SCI) Serial Communications Interface (SCI) SCI Error Detection Technical Data ...
Page 152
... The receive data register when it is read The transmit data register when it is written $102F Bit R7/T7 R6/T6 R5/T5 R4/T4 Indeterminate after reset Figure 7-3. Serial Communications Data Register (SCDR) Serial Communications Interface (SCI) Register, Figure 7-8, and R3/T3 R2/T2 R1/T1 MC68HC11E Family — Rev. 4 MOTOROLA Bit 0 R0/T0 ...
Page 153
... If M bit is set, T8 stores the ninth bit in the transmit data character. Bit 5 — Unimplemented Always reads 0 M — Mode Bit (select character format) WAKE — Wakeup by Address Mark/Idle Bit Bits [2:0] — Unimplemented Always read 0 MC68HC11E Family — Rev. 4 MOTOROLA $102C Bit ...
Page 154
... SCI interrupt requested when RDRF flag or the OR status flag is set 0 = IDLE interrupts disabled 1 = SCI interrupt requested when IDLE status flag is set 0 = Transmitter disabled 1 = Transmitter enabled 0 = Receiver disabled 1 = Receiver enabled Serial Communications Interface (SCI Bit RWU SBK MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 155
... TDRE — Transmit Data Register Empty Flag This flag is set when SCDR is empty. Clear the TDRE flag by reading SCSR with TDRE set and then writing to SCDR. MC68HC11E Family — Rev. 4 MOTOROLA 0 = Normal SCI receiver 1 = Wakeup enabled and receiver interrupts inhibited 0 = Break generator off ...
Page 156
... Clear NF by reading SCSR with NF set and then reading SCDR. Technical Data 156 0 = Transmitter busy 1 = Transmitter idle 0 = SCDR empty 1 = SCDR full 0 = RxD line active 1 = RxD line idle overrun 1 = Overrun detected 0 = Unanimous decision 1 = Noise detected Serial Communications Interface (SCI) MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 157
... NOTE: SCP2 applies to MC68HC(7)11E20 only. When SCP2 = 1, SCP[1:0] must equal 0s. Any other values for SCP[1:0] are not decoded in the prescaler and the results are unpredictable. Refer to Figure MC68HC11E Family — Rev. 4 MOTOROLA 0 = Stop bit detected 1 = Zero detected $102B Bit ...
Page 158
... MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 159
... The prescaler select bits determine the highest baud rate. The rate select bits determine additional divide by two stages to arrive at the receiver timing (RT) clock rate. The baud rate clock is the result of dividing the RT clock by 16. MC68HC11E Family — Rev. 4 MOTOROLA Figure 7-8 and Figure 7-9 illustrate the SCI baud rate timing chain. ...
Page 160
... OSCILLATOR AND CLOCK GENERATOR ( 4) XTAL Figure 7-8. SCI Baud Rate Generator Block Diagram Serial Communications Interface (SCI) INTERNAL BUS CLOCK (PH2 SCP[1:0] 0:0 0:1 1:0 1:1 SCR[2:0] 0:0:0 0:0:1 0:1:0 0:1:1 16 1:0:0 SCI TRANSMIT 1:0:1 BAUD RATE (1X) 1:1:0 1:1:1 SCI RECEIVE BAUD RATE (16X) MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 161
... TDRE and TC flags are normally set when the transmitter is first enabled (TE set to 1). The TDRE flag indicates there is room in the transmit queue to store another data character in the TDR. The TIE bit is the local MC68HC11E Family — Rev. 4 MOTOROLA EXTAL OSCILLATOR AND ...
Page 162
... The RxD line is idle if it has constantly been at logic 1 for a full character time. The IDLE flag is set only after the RxD line has been Technical Data 162 Figure Serial Communications Interface (SCI) 7-10, which shows SCI interrupt MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 163
... RxD remains idle. VALID SCI REQUEST MC68HC11E Family — Rev. 4 MOTOROLA BEGIN Y FLAG RDRF = RIE = TDRE = 1? TIE = IDLE = 1? ILIE = Figure 7-10 ...
Page 164
... Serial Communications Interface (SCI) Technical Data 164 Serial Communications Interface (SCI) MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 165
... MC68HC11E Family — Rev. 4 MOTOROLA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 SPI Transfer Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Clock Phase and Polarity Controls . . . . . . . . . . . . . . . . . . . . . 169 SPI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Master In/Slave Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Master Out/Slave 170 Serial Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Slave Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 SPI System Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172 Serial Peripheral Control Register ...
Page 166
... The SPI control block represents those functions that control the SPI system through the serial peripheral control register (SPCR). Technical Data 166 Frequency synthesizers Liquid crystal display (LCD) drivers Analog-to-digital (A/D) converter subsystems Other microprocessors Serial Peripheral Interface (SPI) MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 167
... INTERNAL MCU CLOCK DIVIDER SELECT SPI CONTROL SPI STATUS REGISTER SPI INTERRUPT REQUEST MC68HC11E Family — Rev. 4 MOTOROLA Figure 8-1, which shows the SPI block diagram. MSB LSB 8--BIT SHIFT REGISTER READ DATA BUFFER CLOCK CLOCK LOGIC MSTR SPE SPI CONTROL REGISTER ...
Page 168
... SS NEGATED Technical Data 168 8- MSB SLAVE CPHA = 1 TRANSFER IN PROGRESS MASTER TRANSFER IN PROGRESS SLAVE CPHA = 0 TRANSFER IN PROGRESS Figure 8-2. SPI Transfer Format Serial Peripheral Interface (SPI LSB 2 1 LSB 4 5 MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 169
... SPI logic and becomes a general-purpose input. All SPI input lines are forced to act as inputs regardless of the state of the corresponding DDR bits in DDRD register. MC68HC11E Family — Rev. 4 MOTOROLA Master in/slave out (MISO) Master out/slave in (MOSI) Serial clock (SCK) Slave select (SS) ...
Page 170
... The SS line of the master must be held high goes low, a mode fault error flag (MODF) is set in the serial peripheral status register (SPSR). To disable the mode fault circuit, write bit 5 of the port D data Technical Data 170 Serial Peripheral Interface (SPI) MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 171
... The amount of damage possible depends on the length of time both devices attempt to act as master. MC68HC11E Family — Rev. 4 MOTOROLA as long as only CPHA = 1 clock mode is used. SS Serial Peripheral Interface (SPI) Serial Peripheral Interface (SPI) ...
Page 172
... The three SPI registers are: • • • These registers provide control, status, and data storage functions. Technical Data 172 Serial peripheral control register (SPCR) Serial peripheral status register (SPSR) Serial peripheral data register (SPDR) Serial Peripheral Interface (SPI) MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 173
... SS input. DWOM — Port D Wired-OR Mode Bit DWOM affects all port D pins. MSTR — Master Mode Select Bit It is customary to have an external pullup resistor on lines that are driven by open-drain devices. MC68HC11E Family — Rev. 4 MOTOROLA $1028 Bit SPIE SPE ...
Page 174
... MHz (Baud MHz (Baud) 1.0 MHz 500 kHz 125 kHz 62.5 kHz Serial Peripheral Interface (SPI) Figure 8-2 and Figure 8-2 Controls. 8-1. Frequency at Frequency MHz (Baud) 1.5 MHz 2 MHz 750 kHz 1 MHz 187.5 kHz 250 kHz 93.8 kHz 125 kHz MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 175
... Select Bit 5 — Unimplemented Always reads 0 MODF — Mode Fault Bit To clear the MODF bit, read the SPSR (with MODF set), then write to the SPCR. Refer to Bits [3:0] — Unimplemented Always read 0 MC68HC11E Family — Rev. 4 MOTOROLA $1029 Bit SPIF WCOL 0 0 ...
Page 176
... SPI is double buffered in and single buffered out. Technical Data 176 $102A Bit Bit 7 Bit 6 Bit 5 Bit 4 Indeterminate after reset Figure 8-5. Serial Peripheral Data I/O Register (SPDR) Serial Peripheral Interface (SPI Bit 0 Bit 3 Bit 2 Bit 1 Bit 0 MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 177
... MC68HC11E Family — Rev. 4 MOTOROLA Section 9. Timing System Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Timer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 Timer Control Register 183 Timer Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . 184 Timer Input Capture 4/Output Compare 5 Register . . . . . . 186 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Timer Output Compare Registers . . . . . . . . . . . . . . . . . . . 187 Timer Compare Force Register . . . . . . . . . . . . . . . . . . . . . 190 Output Compare Mask Register ...
Page 178
... The real-time interrupt (RTI programmable periodic interrupt circuit that permits pacing the execution of software routines by selecting one of four interrupt rates. Technical Data 178 Figure 9-1. MC68HC11E Family — Rev. 4 Timing System MOTOROLA ...
Page 179
... SPR[1:0] PRESCALER ( 13) SCP[1: PRESCALER ( 16) PR[1:0] TCNT IC/OC * SCP2 present on MC68HC(7)11E20 only MC68HC11E Family — Rev. 4 MOTOROLA PRESCALER ( 1, 2, 4,....128 SCR[2:0] SCP2 PRESCALER (÷ RTR[1: PRESCALER ( 1, 4, 16, 64) CR[1:0] TOF FF1 ...
Page 180
... The Timing System 12.0 MHz Other Rates 3.0 MHz (E) 333 ns (1/E) (E/1) 333 ns 16 21.845 ms (E/2 ) (E/4) 1.333 s 18 87.381 ms (E/2 ) (E/8) 2.667 s 19 174.76 ms (E/2 ) (E/16) 5.333 s 20 349.52 ms (E/2 ) MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 181
... LATCH TIC1 (HI) TIC1 (LO) CLK 16-BIT LATCH TIC2 (HI) TIC2 (LO) 16-BIT LATCH CLK TIC3 (HI) TIC3 (LO) Figure 9-2. Capture/Compare Block Diagram MC68HC11E Family — Rev. 4 MOTOROLA TCNT (HI) TCNT (LO) 16-BIT FREE-RUNNING COUNTER TAPS FOR RTI, COP WATCHDOG, AND PULSE ACCUMULATOR OC1F FOC1 OC2F FOC2 OC3F ...
Page 182
... I4/O5 being cleared. If the DDRA3 bit is set (configuring PA3 as an output), and IC4 is enabled, then writes to PA3 cause edges on the pin Technical Data 182 Pulse accumulator control register (PACTL) Timer control 2 register (TCTL2) Timer interrupt mask 1 register (TMSK1) Timer interrupt flag 2 register (TFLG1) Timing System MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 183
... EDGxB and EDGxA — Input Capture Edge Control Bits There are four pairs of these bits. Each pair is cleared reset and must be encoded to configure the corresponding input capture edge detector circuit. IC4 functions only if the I4/O5 bit in the PACTL register is set. Refer to MC68HC11E Family — Rev. 4 MOTOROLA $1021 Bit ...
Page 184
... Indeterminate after reset Bit Bit 7 Bit 6 Bit 5 Bit 4 Indeterminate after reset Figure 9-4. Timer Input Capture 1 Register Pair (TIC1) Timing System Address: $1010 Bit 0 Bit 11 Bit 10 Bit 9 Bit 8 Address: $1011 Bit 0 Bit 3 Bit 2 Bit 1 Bit 0 MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 185
... Register name: Timer Input Capture 2 Register (Low) Read: Write: Reset: Register name: Timer Input Capture 3 Register (High) Read: Write: Reset: Register name: Timer Input Capture 3 Register (Low) Read: Write: Reset: MC68HC11E Family — Rev. 4 MOTOROLA Bit Bit 15 Bit 14 Bit 13 Bit 12 Indeterminate after reset Bit Bit 7 ...
Page 186
... Bit Figure 9-7. Timer Input Capture 4/Output Compare 5 Register Pair (TI4/O5) Timing System 9.8 Pulse Accumulator. Address: $101E Bit 0 Bit 11 Bit 10 Bit 9 Bit Address: $101F Bit 0 Bit 3 Bit 2 Bit 1 Bit MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 187
... All output compare registers are 16-bit read-write. Each is initialized to $FFFF at reset output compare register is not used for an output compare function, it can be used as a storage location. A write to the MC68HC11E Family — Rev. 4 MOTOROLA Timing System Timing System Output Compare Technical Data ...
Page 188
... Bit 11 Bit 10 Bit 9 Bit Address: $1017 Bit 0 Bit 3 Bit 2 Bit 1 Bit Address: $1018 Bit 0 Bit 11 Bit 10 Bit 9 Bit Address: $1019 Bit 0 Bit 3 Bit 2 Bit 1 Bit MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 189
... Register name: Timer Output Compare 3 Register (Low) Read: Write: Reset: Register name: Timer Output Compare 4 Register (High) Read: Write: Reset: Register name: Timer Output Compare 4 Register (Low) Read: Write: Reset: MC68HC11E Family — Rev. 4 MOTOROLA Bit Bit 15 Bit 14 Bit Bit ...
Page 190
... Bits [2:0] — Unimplemented Always read 0 Technical Data 190 $100B Bit FOC1 FOC2 FOC3 FOC4 Unimplemented Figure 9-12. Timer Compare Force Register (CFORC Not affected 1 = Output x action occurs Timing System Bit 0 FOC5 MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 191
... Use OC1M with OC1 to specify the bits of port A that are affected by a successful OC1 compare. The bits of the OC1M register correspond to PA[7:3]. Address: Read: Write: Reset: OC1M[7:3] — Output Compare Masks Bits [2:0] — Unimplemented Always read 0 MC68HC11E Family — Rev. 4 MOTOROLA $100C Bit OC1M7 OC1M6 OC1M5 OC1M4 0 0 ...
Page 192
... If OC1Mx is set, data in OC1Dx is output to port A bit x on successful OC1 compares. Bits [2:0] — Unimplemented Always read 0 Technical Data 192 $100D Bit OC1D7 OC1D6 OC1D5 OC1D4 Unimplemented Figure 9-14. Output Compare 1 Data Register (OC1D) Timing System Bit 0 OC1D3 MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 193
... MSB read cycle. Register name: Timer Counter Register (High) Read: Write: Reset: Register name: Timer Counter Register (Low) Read: Write: Reset: MC68HC11E Family — Rev. 4 MOTOROLA Address: $100E Bit Bit 15 Bit 14 Bit 13 Bit 12 0 ...
Page 194
... Timer disconnected from output pin logic 0 1 Toggle OCx output line 1 0 Clear OCx output line Set OCx output line to 1 Timing System Bit 0 OM4 OL4 OM5 OL5 for the coding. MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 195
... If the ICxI enable bit is set when the ICxF flag bit is set, a hardware interrupt sequence is requested. NOTE: Bits in TMSK1 correspond bit for bit with flag bits in TFLG1. Bits in TMSK1 enable the corresponding interrupt sources. MC68HC11E Family — Rev. 4 MOTOROLA $1022 Bit OC1I ...
Page 196
... Figure 9-18. Timer Interrupt Flag 1 Register (TFLG1) $1024 Bit TOI RTII PAOVI PAII Unimplemented Figure 9-19. Timer Interrupt Mask 2 Register (TMSK2) Timing System Bit 0 I4/O5F IC1F IC2F IC3F Bit 0 PR1 PR0 MC68HC11E Family — Rev. 4 MOTOROLA ...
Page 197
... NOTE: Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Bits in TMSK2 enable the corresponding interrupt sources. MC68HC11E Family — Rev. 4 MOTOROLA 0 = TOF interrupts disabled 1 = Interrupt requested when TOF is set to 1 9.6 Real-Time Interrupt 9.8.3 Pulse Accumulator Status and Interrupt 9 ...
Page 198
... Bits [3:0] — Unimplemented Always read 0 Technical Data 198 $1025 Bit TOF RTIF PAOVF PAIF Unimplemented Figure 9-20. Timer Interrupt Flag 2 Register (TFLG2) 9.6 Real-Time Interrupt 9.8 Pulse Accumulator. 9.8 Pulse Accumulator. Timing System (RTI). MC68HC11E Family — Rev. 4 MOTOROLA Bit 0 0 ...
Page 199
... Every timeout causes the RTIF bit in TFLG2 to be set, and if RTII is set, an interrupt request is generated. After reset, one entire RTI period elapses before the RTIF is set for the first time. Refer to the Interrupt Mask 2 9.6.3 Pulse Accumulator Control MC68HC11E Family — Rev. 4 MOTOROLA Table 9-5. RTI Rates MHz MHz 0 0 2.731 ms 4 ...
Page 200
... Figure 9-21. Timer Interrupt Mask 2 Register (TMSK2 TOF interrupts disabled 1 = Interrupt requested when TOF is set RTIF interrupts disabled 1 = Interrupt requested when RTIF set to 1 9.8 Pulse Accumulator. 9.8 Pulse Accumulator. Table 9-4. Timing System Bit 0 PR1 PR0 MC68HC11E Family — Rev. 4 MOTOROLA ...