MC68L11F1CPU3 Motorola, MC68L11F1CPU3 Datasheet
MC68L11F1CPU3
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... PLCC (MC68HC11F1 only), 64-Pin QFP (MC68HC11FC0 only), and 80-pin TQFP pack- age options This document contains information on a new product. Specifications and information herein are subject to change without notice. © MOTOROLA INC., 1997 Order this document by MC68HC11FTS/D MC68HC11F1 ...
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... C 3 MHz MHz – MHz MC Order Number MC68HC11F1PU5 MC68HC11F1CPU2 MC68HC11F1CPU3 MC68HC11F1CPU4 MC68HC11F1CPU5 MC68HC11F1VPU2 MC68HC11F1VPU3 MC68HC11F1VPU4 MC68HC11F1MPU2 MC68HC11F1MPU3 MC68HC11F1MPU4 MC68HC11F1FN5 MC68HC11F1CFN2 MC68HC11F1CFN3 MC68HC11F1CFN4 MC68HC11F1CFN5 MC68HC11F1VFN2 MC68HC11F1VFN3 MC68HC11F1VFN4 MC68HC11F1MFN2 MC68HC11F1MFN3 MC68HC11F1MFN4 MC Order Number MC68L11F1FN3 MC68L11F1CFN3 MC68L11F1PU3 MC68L11F1CPU3 MC68HC11F1/FC0 MC68HC11FTS/D ...
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... Frequency 4 MHz MC68HC11FC0CFU4 – MHz MC68HC11FC0CFU5 MHz MC68HC11FC0FU6 4 MHz MC68HC11FC0CPU4 – MHz MC68HC11FC0CPU5 MHz MC68HC11FC0PU6 Temperature Frequency 3 MHz MC68L11FC0FU3 4 MHz MC68L11FC0FU4 – MHz MC68L11FC0PU3 4 MHz MC68L11FC0PU4 MC Order Number MC Order Number MOTOROLA 3 ...
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... SPI Block Diagram ....................................................................................................................49 10.2 SPI Registers ............................................................................................................................50 11 Analog-to-Digital Converter 11.1 Input Pins ..................................................................................................................................54 11.2 Conversion Sequence ...............................................................................................................54 11.3 A/D Registers ............................................................................................................................55 12 Main Timer 12.1 Timer Operation ........................................................................................................................57 12.2 Timer Registers .........................................................................................................................59 13 Pulse Accumulator 13.1 Pulse Accumulator Block Diagram ............................................................................................64 13.2 Pulse Accumulator Registers ....................................................................................................64 MOTOROLA 4 TABLE OF CONTENTS Page MC68HC11F1/FC0 MC68HC11FTS/D ...
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... TI4O5 .................. Timer Input Capture 4/Output Compare 5 ....................$101E, $101F ..............60 TIC1–TIC3........... Timer Input Capture ......................................................$1010–$1015 ..............60 TMSK1 ................ Timer Interrupt Mask 1 ..................................................$1022 ..........................61 TMSK2 ................ Timer Interrupt Mask 2 ..................................................$1024 ................... 62 TOC1–TOC4 ....... Timer Output Compare .................................................$1016–$101D ..............60 MC68HC11F1/FC0 MC68HC11FTS/D REGISTER INDEX Address Page , , MOTOROLA 5 ...
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... PA7 OC2/OC1 PA6 OC3/OC1 PA5 OC4/OC1 PA4 IC4/OC5/OC1 PA3 IC3 PA2 IC2 PA1 IC1 PA0 ADDRESS BUS PORT B Figure 1 MC68HC11F1 Block Diagram MOTOROLA 6 XTAL EXTAL IRQ XIRQ RESET 4XOUT OSCILLATOR CLOCK INTERRUPT LOGIC LOGIC PULSE COP ACCUMULATOR TIMER SYSTEM PERIODIC INTERRUPT ...
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... CORE DATA BUS PORT C PORT F DDRC MODB / MODA / V LIR STBY MODE CONTROL PG7 CSPROG PG6 CSGEN CSIO1 PG5 CSIO2 PG4 PG3 PG2 PG1 PG0 CHIP SELECTS WAIT RxD PD0 SCI TxD PD1 MISO PD2 MOSI PD3 SCK PD4 SS PD5 SPI MOTOROLA 7 ...
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... PC4/DATA4 14 PC5/DATA5 15 PC6/DATA6 PC7/DATA7 16 17 RESET 18 XIRQ 19 IRQ 20 PG7/CSPROG 21 PG6/CSGEN 22 PG5/CSIO1 23 PG4/CSIO2 24 PG3 25 PG2 26 PG1 Figure 3 MC68HC11F1 68-Pin PLCC Pin Assignments MOTOROLA MC68HC11F1 PE4/AN4 PE0/AN0 PF0/ADDR0 PF1/ADDR1 PF2/ADDR2 PF3/ADDR3 PF4/ADDR4 PF5/ADDR5 PF6/ADDR6 PF7/ADDR7 ...
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... PF4/ADDR4 13 PF3/ADDR3 14 PF2/ADDR2 15 PF1/ADDR1 16 PF0/ADDR0 17 PE0/AN0 18 PE4/AN4 Figure 4 Pin Assignments for the MC68HC11F1 80-Pin QFP MC68HC11F1/FC0 MC68HC11FTS/D MC68HC11F1 PG1 58 PG2 57 PG3 56 PG4/CSIO2 55 PG5/CSIO1 54 PG6/CSGEN 53 PG7/CSPROG IRQ 52 51 XIRQ 50 RESET 49 PC7/DATA7 48 PC6/DATA6 47 PC5/DATA5 46 PC4/DATA4 45 PC3/DATA3 44 PC2/DATA2 43 PC1/DATA1 MOTOROLA 9 ...
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... PB4/ADDR12 PB3/ADDR11 4 PB2/ADDR10 5 PB1/ADDR9 6 PB0/ADDR8 7 PF7/ADDR7 8 PF6/ADDR6 9 10 PF5/ADDR5 PF4/ADDR4 11 PF3/ADDR3 12 13 PF2/ADDR2 PF1/ADDR1 14 PF0/ADDR0 Figure 5 MC68HC11FC0 64-Pin QFP Pin Assignments MOTOROLA 10 MC68HC11FC0 48 PG2 47 PG3 PG4/CSIO2 46 45 PG5/CSIO1 44 PG6/CSGEN PG7/CSPROG 43 42 IRQ XIRQ 41 RESET 40 PC7/DATA7 39 38 PC6/DATA6 PC5/DATA5 37 PC4/DATA4 36 ...
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... PF4/ADDR4 13 PF3/ADDR3 14 PF2/ADDR2 15 PF1/ADDR1 16 PF0/ADDR0 PE4 Figure 6 MC68HC11FC0 80-Pin TQFP Pin Assignments MC68HC11F1/FC0 MC68HC11FTS/D MC68HC11FC0 60 NC PG1 59 58 PG2 57 PG3 56 PG4/CSIO0 55 PG5/CSIO1 54 PG6/CSGEN 53 PG7/CSPROG 52 IRQ XIRQ 51 50 RESET 49 PC7/DATA7 48 PC6/DATA6 47 PC5/DATA5 46 PC4/DATA4 45 PC3/DATA3 44 PC2/DATA2 43 PC1/DATA1 MOTOROLA 11 ...
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... In expanded and test modes, R/W indicates the direction of transfers on the external data bus. V and These pins provide the reference voltage for the analog-to-digital converter. Use bypass capacitors to minimize noise on these signals. Any noise on V accuracy. These pins are not present on the MC68HC11FC0. MOTOROLA 12 is ground. SS and V will directly affect A ...
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... Port 8-bit output-only port. In single-chip mode, port F pins are general-purpose output pins PF[7:0]. In expanded mode, port F pins act as the low-order address outputs ADDR[7:0]. Port G Pins Port 8-bit general-purpose I/O port. When enabled, four chip select signals are alternate functions of PG[7:4]. PG[1:0] are not available on the 64-pin MC68HC11FC0. MC68HC11F1/FC0 MC68HC11FTS/D NOTE NOTE MOTOROLA 13 ...
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... Bit 7 6 $101C Bit 15 14 $101D Bit 7 6 $101E Bit 15 14 $101F Bit 7 6 $1020 OM2 OL2 OM3 $1021 EDG4B EDG4A EDG1B MOTOROLA PA5 PA4 PA3 PA2 DDA4 DDA3 DDA2 PG4 PG3 PG2 DDG4 DDG3 DDG2 PB5 PB4 PB3 ...
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... Bit 0 ADR4 BPRT1 BPRT0 BPROT Reserved Reserved 0 0 OPT2 CR1 CR0 OPTION 1 Bit 0 COPRST EELAT EEPGM PPROG PSEL1 PSEL0 HPRIO REG1 REG0 INIT FCOP 0 TEST1 1 EEON CONFIG Reserved Reserved PSTHA PSTHB CSSTRH PSIZA PSIZB CSCTL 0 0 CSGADR GSIZB GSIZC CSGSIZ MOTOROLA 15 ...
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... OL2 OM3 $1021 EDG4B EDG4A EDG1B $1022 OC1I OC2I OC3I $1023 OC1F OC2F OC3F $1024 TOI RTII PAOVI $1025 TOF RTIF PAOVF MOTOROLA PA5 PA4 PA3 PA2 DDA4 DDA3 DDA2 PG4 PG3 PG2 DDG4 DDG3 DDG2 PB5 PB4 PB3 ...
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... RWU SBK SCCR2 FE 0 SCSR 1 Bit 0 SCDR Reserved Reserved 0 0 OPT2 CR1 CR0 OPTION 1 Bit 0 COPRST Reserved PSEL1 PSEL0 HPRIO REG1 REG0 INIT FCOP 0 TEST1 0 0 CONFIG Reserved Reserved PSTHA PSTHB CSSTRH PSIZA PSIZB CSCTL 0 0 CSGADR GSIZB GSIZC CSGSIZ MOTOROLA 17 ...
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... ROM. In this mode, the user can download a program into on-chip RAM through the serial communica- tion interface (SCI). Special test mode, a variation of expanded mode, is primarily used during Motorola’s internal production testing, but can support emulation and debugging during program development. ...
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... SPECIAL SPECIAL BOOTSTRAP TEST MODA = 0 MODA = 1 MODB = 0 MODB = 0 x000 1 1024 BYTES RAM x3FF y000 2 96-BYTE REGISTER FILE y05F $BFC0 SPECIAL 256 BYTES BOOTSTRAP MODE ROM INTERRUPT 3 VECTORS $BFFF 4 RESERVED $FFC0 512 NORMAL BYTES MODE 5 EEPROM INTERRUPT VECTORS $FFFF MOTOROLA 19 ...
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... The register block can be remapped to $0000, $2000, or $3000, depending on the value contained in REG[1:0] in the INIT register. 4.3 System Initialization Registers HPRIO — Highest Priority Interrupt and Miscellaneous Bit 7 6 RBOOT SMOD MDA RESET MOTOROLA 20 — — — — EXTERNAL — — — — EXTERNAL — — — — — — ...
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... RAM1 RAM0 NOTE Table 9 Register Block Location REG[1:0] Register Block Address 0 0 $0000 – $005F 0 1 $1000 – $105F 1 0 $2000 – $205F 1 1 $3000 – $305F SMOD MDA $x03D 1 Bit 0 REG1 REG0 0 1 MOTOROLA 21 ...
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... OPT2 — System Configuration Option Register 2 Bit 7 6 GWOM CWOM RESET 0 0 GWOM — Port G Wired-OR Mode Option Refer to 7.8 Parallel I/O Registers, page 36. MOTOROLA RAM1 RAM0 REG3 REG4 NOTE Location REG[3:0] $0000-$03FF ...
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... STOP instruction and rewritten to one after recovery from STOP. FCME should be kept cleared if the user intends to use the STOP instruction. CR[1:0] — COP Timer Rate Select Refer to 5.2 Reset and Interrupt Registers, page 27. MC68HC11F1/FC0 MC68HC11FTS IRQE* DLY* CME FCME $x039 1 Bit 0 CR1* CR0 MOTOROLA 23 ...
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... FCOP — Force COP Watchdog Failure 0 = Normal operation 1 = Generate an immediate COP failure reset. Note that the NOCOP bit in the CONFIG register must be cleared (COP enabled) in order to force the reset. Bit 0 — Not implemented. Reads always return zero and writes have no effect. MOTOROLA ...
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... SCI data register precisely these two steps that are required to clear the RDRF flag further instructions are necessary. 5.1 Interrupt Sources The following table summarizes the interrupt sources, vector addresses, masks, and flag bits. MC68HC11F1/FC0 MC68HC11FTS/D MOTOROLA 25 ...
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... Bits [7:6], [4:2] Refer to 4.3 System Initialization Registers, page 23, and 11.3 A/D Registers, page 56. IRQE — IRQ Select Edge Sensitive Only 0 = Low level recognition 1 = Falling edge recognition MOTOROLA 26 Interrupt Source CCR Mask Reserved 5 ...
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... Reserved (Default to IRQ) IRQ (External Pin) Real-Time Interrupt Timer Input Capture 1 Timer Input Capture 2 Timer Input Capture 3 CR[1: CR[1: 524.288 ms 2.097 s 262.144 ms 1.049 s 174.763 ms 699.051 ms 131.072 ms 524.288 ms 104.858 ms 419.430 ms 87.381 ms 349.525 $x03A 1 Bit $x03C 1 Bit 0 PSEL1 PSEL0 0 1 MOTOROLA 27 ...
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... RESET U U Bits 7:3, 1:0 — See 6.2 EEPROM Registers, page 30. NOCOP — COP System Disable 0 = COP enabled (forces reset on time-out COP disabled (does not force reset on time-out) MOTOROLA 28 Interrupt Source Promoted Timer Output Compare 1 Timer Output Compare 2 Timer Output Compare 3 Timer Output Compare 4 ...
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... MC68HC11F1/FC0 MC68HC11FTS/D NOTE PTCON BPRT3 BPRT2 Block Protected Block Size $xEE0–xFFF 288 Bytes $xE60–xEDF 128 Bytes $xE20–xE5F 64 Bytes $xE00–xE1F 32 Bytes NOTE $x035 1 Bit 0 BPRT1 BPRT0 1 1 MOTOROLA 29 ...
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... EEPROM is forced to $FE00 – $FFFF, regardless of the state of these bits. On factory-fresh devices, EE[3:0] = $0. Bit 3 — Not implemented. Reads always return one and writes have no effect. NOCOP — COP System Disable 0 = COP enabled (forces reset on time-out COP disabled (does not force reset on time-out) MOTOROLA ...
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... BULKE LDAB #$06 STAB $103B MC68HC11F1/FC0 MC68HC11FTS/D EELAT=1, EEPGM=0 Set EELAT bit Store data to EEPROM address EELAT=1, EEPGM=1 Turn on programming voltage Delay 10 ms Turn off high voltage and set to READ mode ERASE=1, EELAT=1, EEPGM=0 Set EELAT bit MOTOROLA 31 ...
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... The new value will not take effect until after the next reset se- quence. 1. Erase the CONFIG register. 2. Program the new value to the CONFIG address. 3. Initiate reset. MOTOROLA 32 Store any data to any EEPROM address EELAT=1, EEPGM=1 Turn on programming voltage ...
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... PE7 and PE0 are not available on the 80-pin MC68HC11FC0. PE7, PE4, and PE0 are not available on the 64-pin MC68HC11FC0. 7.6 Port F Port eight-bit output-only port. In single-chip mode, port F pins are general-purpose output pins PF[7:0]. In expanded mode, port F pins act as low-order address outputs ADDR[7:0]. MC68HC11F1/FC0 MC68HC11FTS/D NOTE MOTOROLA 33 ...
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... For DDRx bits input and 1 = output. PORTG — Port G Data Register Bit 7 6 PG7 PG6 RESET Alternate CSPROG CSGEN Function: *These bits are not present on the 64-pin QFP version of the MC68HC11FC0 Indeterminate value MOTOROLA 34 NOTE PA5 PA4 PA3 PA2 OC3 OC4 ...
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... DATA3 DATA2 DDC5 DDC4 DDC3 DDC2 $x003 1 Bit 0 DDG1 DDG0 0 0 $x004 1 Bit 0 PB1 PB0 0 0 ADDR9 ADDR8 $x005 PF1 PF0 0 0 ADDR1 ADDR0 $x006 1 Bit 0 PC1 PC0 DATA1 DATA0 $x007 1 Bit 0 DDC1 DDC0 0 0 MOTOROLA 35 ...
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... OPT2 — System Configuration Option Register 2 Bit 7 6 GWOM CWOM RESET 0 0 GWOM — Port G Wired-OR Mode Option This bit affects all port G pins together Port G outputs are normal CMOS outputs 1 = Port G outputs act as open-drain outputs MOTOROLA PD5 PD4 PD3 PD2 ...
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... CLK4X — 4XCLK Output Enable Refer to 4.3 System Initialization Registers, page 23 LIRDV — Load Instruction Register Driven Refer to 4.3 System Initialization Registers, page 23 Bits — Not implemented. Reads always return zero and writes have no effect. SPRBYP — Refer to 10.2 SPI Registers, page 52. MC68HC11F1/FC0 MC68HC11FTS/D MOTOROLA 37 ...
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... IO1SA, IOS1B — I/O Chip-Select 1 Clock Stretch IO2SA, IO2SB — I/O Chip-Select 2 Clock Stretch GSTHA, GSTHB — General-Purpose Chip-Select Clock Stretch PSTHA, PSSTHB — Program Chip-Select Clock Stretch Each pair of bits selects the number of clock cycles of stretch for the corresponding chip select. MOTOROLA ...
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... Cycle Cycles Cycles IO2PL GCSPR PCSEN — Table 17 Chip Select Priorities GCSPR = 1 On-Chip Registers On-Chip RAM Bootloader ROM 1 1 On-Chip EEPROM I/O Chip Selects General-Purpose Chip Select Program Chip Select $x05D 1 Bit 0 PSIZA PSIZB 0 0 MOTOROLA 39 ...
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... IO1AV — I/O Chip-Select 1 Address Valid 0 = CSIO1 is valid during E-clock valid time (E-clock high CSIO1 is valid during address valid time IO2AV — I/O Chip-Select 2 Address Valid 0 = CSIO2 is valid during E-clock valid time (E-clock high CSIO2 is valid during address valid time MOTOROLA 40 PSIZB Size 0 64 Kbytes ...
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... CSGEN is valid during address valid time GSIZ[A:C] — Block Size for CSGEN Refer to Table 20 for bit values. Table 20 General-Purpose Chip Select Size Control MC68HC11F1/FC0 MC68HC11FTS/D GSIZ[A:C] Address Size 000 64 Kbytes 001 32 Kbytes 010 16 Kbytes 011 8 Kbytes 100 4 Kbytes 101 2 Kbytes 110 1 Kbyte 111 0 Kbytes (disabled) MOTOROLA 41 ...
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... SCDR Tx BUFFER BAUD RATE CLOCK 10 (11) - BIT Tx SHIFT REGISTER H ( SCCR1 SCI CONTROL 1 SCI Rx SCI INTERRUPT QUESTS REQUEST Figure 9 SCI Transmitter Block Diagram MOTOROLA 42 (WRITE ONLY FORCE PIN DIRECTION (OUT) TRANSMITTER CONTROL LOGIC SCSR1 SCI STATUS 1 TDRE TIE ...
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... REQUEST Figure 10 SCI Receiver Block Diagram MC68HC11F1/FC0 MC68HC11FTS/D 16 DATA RECOVERY SCSR1 SCI STATUS 1 RDRF RIE IDLE ILIE OR RIE SCCR2 SCI CONTROL 2 10 (11) - BIT Rx SHIFT REGISTER ALL MSB ONES SCDR Rx BUFFER (READ ONLY) INTERNAL DATA BUS MOTOROLA 43 ...
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... The result of these two dividers in series is the 16X receiver baud rate clock. The SCR[2:0] bits are not affected by reset and can be changed at any time. They should not be changed, however, when an SCI transfer is in progress. MOTOROLA 44 5 ...
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... EXTAL OSCILLATOR AND CLOCK GENERATOR XTAL ( 4) Figure 11 SCI Baud Rate Generator Block Diagram MC68HC11F1/FC0 MC68HC11FTS/D INTERNAL BUS CLOCK (PH2 X00 001 SCR[2:0] 0:0:0 2 0:0:1 2 0:1:0 2 0:1:1 2 1:0:0 2 1:0:1 2 1:1:0 2 1:1 X10 X11 101 SCI Receive Baud Rate (16x) SCI Transmit Baud Rate (1x) MOTOROLA 45 ...
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... SCI interrupt requested when IDLE status flag is set TE — Transmitter Enable When TE goes from zero to one, one unit of idle character time (logic one) is queued as a preamble Transmitter disabled 1 = Transmitter enabled RE — Receiver Enable 0 = Receiver disabled 1 = Receiver enabled MOTOROLA ...
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... FE — Framing Error FE is set when a zero is detected where a stop bit was expected. Clear the FE flag by reading SCSR with FE set and then reading SCDR Stop bit detected 1 = Zero detected MC68HC11F1/FC0 MC68HC11FTS RDRF IDLE $x02E 1 Bit MOTOROLA 47 ...
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... SCDR — Serial Communications Data Register Bit 7 6 Bit 7 6 RESET Indeterminate value Reading SCDR retrieves the last byte received in the receive data buffer. Writing to SCDR loads the transmit data buffer with the next byte to be transmitted. MOTOROLA ...
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... SPRBYP MC68HC11F1/FC0 MC68HC11FTS/D SPI STATUS REGISTER SPIE SPI SPE CONTROL MSTR SPR0 SPR1 CLOCK LOGIC MSB LSB 8-BIT SHIFT REGISTER READ DATA BUFFER Figure 12 SPI Block Diagram SPI INTERRUPT REQUEST SS PD5 M SCK PD4 S S MOSI PD3 M M MISO PD2 S MOTOROLA 49 ...
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... The CPHA bit selects one of two clocking protocols. Refer to Figure 13. SCK CYCLE # 1 (FOR REFERENCE) SCK (CPOL = 0) SCK (CPOL = 1) SAMPLE INPUT (CPHA = 0) DATA OUT MSB SAMPLE INPUT (CPHA = 1) DATA OUT MSB SS (TO SLAVE) Figure 13 SPI Data Clock Timing Diagram MOTOROLA DWOM MSTR CPOL CPHA ...
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... Mbps 250 kbps 1.25 Mbps 312.5 kbps 1.5 Mbps 375 kbps E/4 E/16 NOTE MODF SPR[1: 31.25 kbps 62.5 kbps 93.75 kbps 125 kbps 156.25 kbps 187.5 kbps E/32 $x029 1 Bit $x02A 1 Bit 0 1 Bit 0 MOTOROLA 51 ...
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... Enable SPI baud rate counter 1 = Bypass SPI baud rate counter When the SPI baud rate counter is bypassed, the SPI can transmit at a maximum master mode baud rate equal to the E-clock frequency. SPRBYP is present only on the MC68HC11FC0 and overrides the setting of SPR[1:0] in SPCR. MOTOROLA ...
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... AN7 ADR1 A/D RESULT 1 ADR2 A/D RESULT 2 Figure 14 A/D Converter Block Diagram MC68HC11F1/FC0 MC68HC11FTS/D NOTE 8-BIT CAPACITIVE DAC WITH SAMPLE AND HOLD SUCCESSIVE APPROXIMATION REGISTER AND CONTROL ADCTL A/D CONTROL RESULT REGISTER INTERFACE ADR3 A/D RESULT INTERNAL DATA BUS ADR4 A/D RESULT 4 EA9 A/D BLOCK MOTOROLA 53 ...
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... Figure 16 shows the timing of a typical sequence. Synchronization is referenced to the system E clock. E CLOCK 12 E CYCLES SAMPLE ANALOG INPUT CONVERT FIRST CONVERT SECOND CHANNEL, UPDATE CHANNEL, UPDATE 0 ADR1 32 MOTOROLA 54 + ~12V – ~0.7V DUMMY N-CHANNEL OUTPUT DEVICE MSB BIT 6 BIT 5 BIT 4 BIT 3 4 ...
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... I I Channel Signal Result in ADRx if MULT = 1 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Reserved )/ Reserved $x030 1 Bit ADR1 ADR2 ADR3 ADR4 ADR1 ADR2 ADR3 ADR4 ADR1–ADR4 ADR1 ADR2 ADR3 ADR4 MOTOROLA 55 ...
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... ADPU — A/D Power A/D powered down 1 = A/D powered up CSEL — Clock Select 0 = A/D and EEPROM use system E-Clock 1 = A/D and EEPROM use internal RC clock Bits [5:0] — Refer to 4.3 System Initialization Registers, page 23. MOTOROLA ...
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... Overflow 524.288 ms 16.000 s 1.049 s 262.144 ms 8.000 s 524.288 ms 174.763 ms 5.333 s 349.525 ms 131.072 ms 4.000 s 262.144 ms 104.858 ms 3.200 s 209.715 ms 87.381 ms 2.667 s 174.763 16 RTR[1: 65.536 ms 32.768 ms 21.845 ms 16.384 ms 13.107 ms 10.923 RTR[1: 2.097 s 1.049 s 699.051 ms 524.288 ms 419.430 ms 349.525 MOTOROLA 57 ...
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... LATCH CLK TIC2 (HI) TIC2 (LO) 16-BIT LATCH CLK TIC3 (HI) TIC3 (LO) NOTE: Registers that control port A action include DDRA, OC1M, OC1D, PACTL, TCTL1 and TCTL2. MOTOROLA 58 TCNT (HI) TCNT (LO) TOI 16-BIT FREE RUNNING TOF COUNTER OC1I OC1F FOC1 OC2I OC2F FOC2 OC3I ...
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... FOC5 OC1M4 OC1M3 OC1D4 OC1D3 $x00B 1 Bit $x00C 1 Bit $x00D 1 Bit $x00E, $x00F 9 Bit 8 High 1 Bit 0 Low 0 0 MOTOROLA 59 ...
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... OM2–OM5 — Output Mode OL2–OL5 — Output Level Each OMx–OLx bit pair determines the output action taken on the corresponding OCx pin after a suc- cessful compare, as shown in Table 29. OC5 functions only if the I4/O5 bit in the PACTL register is cleared. MOTOROLA ...
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... Capture on rising edges only 0 Capture on falling edges only 1 Capture on any edge OC3I OC4I I4/O5I IC1I OC3F OC4F I4/O5F IC1F $x021 1 Bit 0 EDG3B EDG3A 0 0 $x022 1 Bit 0 IC2I IC3I 0 0 $x023 1 Bit 0 IC2F IC3F 0 0 MOTOROLA 61 ...
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... TMSK2, the bits of TFLG2 allow the timer subsystem to operate in either a polled or interrupt driven system. Each bit of TFLG2 corresponds to a bit in TMSK2 in the same position. Bits in TFLG2 are cleared by writing a one to the corresponding bit positions. TOF — Timer Overflow Flag Set when TCNT rolls over from $FFFF to $0000. MOTOROLA ...
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... Any MC68HC11F1/FC0 MC68HC11FTS PEDGE 0 I4/ RTR [1: RTR [1: 16.384 ms 32.768 ms 8.192 ms 16.384 ms 5.461 ms 10.923 ms 4.096 ms 8.192 ms 3.277 ms 6.554 ms 2.731 ms 5.461 $x026 1 Bit 0 RTR1 RTR0 0 0 RTR [1: 65.536 ms 32.768 ms 21.845 ms 16.384 ms 13.107 ms 10.923 MOTOROLA 63 ...
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... Pulse Accumulator Registers TMSK2 — Timer Interrupt Mask 2 Bit 7 6 TOI RTII RESET Bits [7:4] in TMSK2 correspond bit for bit with flag bits in TFLG2. Setting any of these bits enables the corresponding interrupt source. MOTOROLA 64 TMSK2 INTERRUPT ENABLES 2:1 MUX PACTL CONTROL ...
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... PEDGE — Pulse Accumulator Edge Control This bit has different meanings depending on the state of the PAMOD bit, as shown in Table 33. MC68HC11F1/FC0 MC68HC11FTS PAIF PEDGE 0 I4/ $x025 1 Bit $x026 1 Bit 0 RTR1 RTR0 0 0 MOTOROLA 65 ...
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... The PACNT is readable even if PAI is not active in gated time accumulation mode. The counter is not affected by reset and can be read or written at any time. Counting is synchronized to the internal PH2 clock so that incrementing and reading occur during opposite half cycles. MOTOROLA 66 Action on Clock 0 PAI falling edge increments the counter ...
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... MC68HC11F1/FC0 MC68HC11FTS/D MOTOROLA 67 ...
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... Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur ...