UPD485505G-25 NEC, UPD485505G-25 Datasheet
UPD485505G-25
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UPD485505G-25 Summary of contents
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... The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. M10059EJ7V0DSJ1 (7th edition) ...
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Pin Configuration (Marking side) 24-pin plastic SOP (11.43 mm (450 OUT0 D 2 OUT1 D 3 OUT2 D 4 OUT3 RE 5 RSTR 6 GND 7 RCK OUT4 D 10 OUT5 D 11 OUT6 D ...
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Block Diagram WCK D IN0 D IN1 D IN2 D IN3 D IN4 D IN5 D IN6 D IN7 WE RSTR Write Address Pointer Memory Cell Array 40,384 bits (5,048 words by 8 bits) Read Address Pointer Data Sheet M10059EJ7V0DS00 ...
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Input/Output Pin Function Pin I/O Pin Pin Symbol Number Name Data IN0 | Input IN7 Out Data OUT0 | Output OUT7 19 ...
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... After power up, the PD485505 requires the initialization of internal circuits because the read and write address pointers are not defined at that time necessary to satisfy setup requirements and hold times as measured from the rising edge of WCK and RCK, and then input the RSTW and RSTR signals to initialize the circuit. ...
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Operation-related Restriction Following restriction exists to read data written in a write cycle. Read the written data after an elapse of 1/2 write cycle + not satisfied, the output data may undefined. WAR Figure 2.1 Delay ...
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Electrical Specifications All voltages are referenced to GND. Absolute Maximum Ratings Parameter Voltage on any pin relative to GND Supply voltage Output current Operating ambient temperature Storage temperature Note –3.0 V MIN. (Pulse width = 10 ns) Caution Exposing ...
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AC Characteristics (Recommended Operating Conditions unless otherwise noted) Parameter Write clock cycle time Write clock pulse width Write clock precharge time Read clock cycle time Read clock pulse width Read clock precharge time Access time Write data-read delay time Output ...
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Notes 1. AC measurements assume Characteristics test condition Input Timing Specification 3 Output Timing Specification High impedance Output Loads for Timing OUT 1 Input timing reference ...
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Write Cycle Timing Chart Cycle n Cycle n+1 t WCK t WCP WCK (Input) t WCW WE (Input (Input) (n) IN Remark RSTW = “H” level Read Cycle Timing Chart Cycle n Cycle n+1 t ...
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Write Reset Cycle Timing Chart (WE = Active) Cycle n WCK (Input RN1 RS RSTW (Input) WE (Input) “L” Level t DS (n–1) D (Input) IN Note In write reset cycle, reset operation is executed even without a ...
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Read Reset Cycle Timing Chart (RE = Active) Cycle n RCK (Input RN1 RSTR (Input) RE (Input) “L” Level t AC (n–1) D (Output) (n) OUT Note In read reset cycle, reset operation is executed even without ...
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Application 4 Delay Line PD485505 easily allows (5,048 bits) delay line (see Figure 4.1). Figure 4 Delay Line Circuit 40 MHz Clock WCK Data Input Figure 4 ...
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Bit Delay It is possible to make delay read from the write data with the PD485505. (1) Perform a reset operation in the cycle proportionate to the delay length. (Figure 4.3) (2) Shift the input timing of write ...
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Figure 4.4 n-Bit Delay Line Timing Chart (2) t WCK t RCK Cycle 0 Cycle 1 Write Read t t WCW WCP t t RCW RCP WCK/RCK (Input RSTW (Input) RSTR t DS (Input ...
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Double-speed Conversion Figure 4.6 shows an example timing chart of double-speed and twice reading operation (f 2 cycle) for a write operation (f = 5,048 cycle). W Caution The read operation collide with the write operation on the same ...
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Package Drawing 24-PIN PLASTIC SOP (11.43 mm (450 NOTE Each lead centerline is located within 0. its true position (T.P.) at maximum material condition. 13 detail of ...
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Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the PD485505. Type of Surface Mount Device PD485505G: 24-pin plastic SOP (11.43 mm (450)) 7. Example of Stamping Letter E in the fifth character position in ...
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... HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry ...
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... NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others ...