UPB1009K-E1 NEC, UPB1009K-E1 Datasheet
UPB1009K-E1
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UPB1009K-E1 Summary of contents
Page 1
... MHz, f REFin : On-chip switchable frequency divider (1/N = 100, 3/256, 9/1024, 65/4096) : On-chip 4-bit A/D converter : On-chip VCO tank circuit and 2ndIF filter : V = 2 26.0 mA TYP 3 100 44-pin plastic QFN UPB1009K = 4.092 MHz 2ndIFin = 62.980 MHz 2.556 MHz 1stIFin 2ndIFin ...
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... PB1009K-E1 44-pin plastic QFN Remark To order evaluation samples, contact your nearby sales office. Part number for sample order: 2 Supplying Form • wide embossed taping • Pin 1 indicates pull-out direction of tape • Qty 1.5 kpcs/reel, Dry pack specification µ PB1009K UPB1009K ...
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... MIX AGC LPF RF ÷25 ÷N PLL Tank Cont. MS1 MS2 TCXO µ PB1009K’s internal functions on the system. UPB1009K CG Package (dB) 44-pin plastic QFN New Device 100 to 36-pin plastic QFN 120 100 to 36-pin plastic QFN Available 120 36-pin plastic QFN 2ndIF = 4 ...
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... CC LNAGND 43 PreAmp LNAin – 4bit ADC Pwdctrl Logic V LPF GC OSC 1stMIX GNDana – 21 DCOFFin + – 20 DCOFFout 19 2ndIFin IFamp 18 2ndIFout 1/4 17 IFGND 16 CLKout 15 PLLGND PLL PD Fref 14 PLLV 13 Refin 12 MS2 UPB1009K CC ...
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... Connect a bypass capacitor to this pin to reduce the high-frequency impedance. 41 1stIFout Output pin of RF mixer. Insert an IFSAW filter between this pin and pin 37. The VCO oscillation signal can be monitored on this pin. Internal Equivalent Circuit Gibert Cell 4 Bias 5 UPB1009K ...
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... PLLGND Ground pin of PLL. 16 CLKout Clock (f TCXO 6 MS1 : L TCXO : 16.368, MS2 : L 16.384 MHz MS1 : L TCXO : 19.2 MHz MS2 : H MS1 : H TCXO : 14.4 MHz MS2 : L MS1 : H TCXO : 26 MHz MS2 : 0.45 mA). sink source ) output pin (IC test pin). UPB1009K Internal Equivalent Circuit ...
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... LoGND Ground pin of VCO. 17 IFGND Ground pin of IF block. 18 2ndIFout Output pin of IF amplifier. 38 1stIFin Input pin of second IF mixer. 39 IFV Power supply voltage pin of IF block. CC Internal Equivalent Circuit 7 8 µ PB1009K Bias 17 UPB1009K VCO out VCO cont 18 7 ...
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... Digital signal output pins LSB = D0, MSB = SCKin Sampling clock signal input pin. 32 AGCin AGC control pulse signal input pin. 33 AGCout AGC control signal output pin. 8 UPB1009K Internal Equivalent Circuit 24 19 1.8 kΩ inv ...
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... Ground pin for power control logic. 36 PD1 Low : 37 PD2 0 to 0.3 (V) High : − 0 (V) CC PD1 : L Sleep mode PD2 : L (all circuits off). PD1 : L Warm-up mode PD2 : H (PLL on). PD1 : H Calibration mode PD2 : L (PLL + IF + ADC on). PD1 : H Active mode PD2 : H (all circuits on). UPB1009K Internal Equivalent Circuit ...
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... REFin f REFout V 0 IL1 − 0 IH1 IL2 − 0 IH2 CC UPB1009K Ratings 3.6 100 Note 266 −40 to +85 −55 to +125 TYP. MAX. 3.0 3.3 +25 +85 − 1 575.42 − − 61.38/62.98 − − 4.092/2.556 − TCXO − 0.3 − ...
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... ADC) PD1 PD2 OFF H L OFF L L OFF Test Conditions 1/N Phase Comparison Frequency PD1 PD2 L L 1/100 L H 3/256 H L 9/1024 H H 65/4096 UPB1009K IF Block PLL Block OFF ON OFF OFF 16.368 MHz 16.384 MHz 19.2 MHz 14.4 MHz 26 MHz 11 ...
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... MHz, 1 576.42 MHz 3LNA RFin Z Calculated from S-parameter where input inLNA DC cut capacitance = 1 nF, output load L = 100 n, and DC cut capacitance = 1 nF outLNA ana → GNDana) in the sleep mode, and the sleep mode DD µ and GND maximum. DD UPB1009K MIN. TYP. MAX. Unit 1.3 2.2 3.5 mA 10.5 13.0 15.5 mA 18.0 22.0 25 ...
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... V = 0.5 V 3IF 1stIFin1 AGC f = 61.38 MHz V = 1.5 V 1stIFin2 AGC f = 65.472 MHz V 2ndLO = 2.5 V AGC Z Calculated from S-parameter where input inIF DC cut capacitance = 1 nF and output DC cut capacitance = 100 nF outIF UPB1009K MIN. TYP. MAX. = 61.38 MHz 1stIF 2.0 2.5 3.0 14.0 16.1 19.0 − 12.8 16.0 −4.0 −0.8 − −29.0 −25.5 − −19.0 − ...
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... REFin KV Center frequency VT When PLL is Locked ∆ C/N 10 kHz I CC5 fs INL DC characteristics IF = 5.17 MHz 20.48 MHz IF = 5.17 MHz 20.48 MHz ENOB = (SINAD−1.763)/6. 5.17 MHz 20.48 MHz Second-degree to fifth-degree distortion components UPB1009K MIN. TYP. MAX. Unit 8.0 9.5 10.6 mA −0.55 −0.45 −0.35 mA 0.35 0.45 0.55 mA −0.3 − − − ...
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... Sampling Delay ds (Aperture Delay) T Output Hold Time oh SampleN+3 SampleN+2 SampleN+4 T clk N+1 N+2 : Analog signal sampling timing Test Conditions MIN. TYP. − pF 19.2 MHz L clk − − 2 UPB1009K SampleN+5 N+3 MAX. Unit − − 1.5 clock − − − ...
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... Note The output data is undefined from the start of the power-down operation to the 7.5th clock from the falling edge of the clock at which the power-down operation is cleared. 16 µ PB1009K is undefined for 7.5 clocks after the power-down signal is Note N undefined UPB1009K N+1 N+1 : Analog signal sampling timing ...
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... TYPICAL CHARACTERISTICS (T ⎯ IC TOTAL CHARACTERISTICS ⎯ TOTAL CIRCUIT CURRENT vs. SUPPLY VOLTAGE +85˚ +25˚C –40˚ 0.5 1.0 1.5 2.0 2.5 Supply Voltage V CC Remark The graphs indicate nominal characteristics. = +25° 3.0 V, unless otherwise specified 3.0 3.5 4.0 (V) UPB1009K 17 ...
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... Frequency f (MHz) Remark The graphs indicate nominal characteristics. 18 –20 –10 0 (dBm +85˚C A +25˚C –40˚C 1 585 1 595 1 605 1 615 UPB1009K PREAMP GAIN vs. FREQUENCY –10 –20 –30 –40 300 500 100 700 900 1 100 1 300 1 500 Frequency f (MHz) PREAMP IM CHARACTERISTICS 0 – ...
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... Frequency f (MHz) Remark The graphs indicate nominal characteristics. –15 –5 5 (dBm +85˚C A +25˚C –40˚ UPB1009K RF MIX IM CHARACTERISTICS 0 –10 –20 –30 –40 –50 –60 T –70 –80 –50 –45 –40 –35 –30 –25 –20 –15 –10 Input Power P ...
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... Remark The graphs indicate nominal characteristics. 20 +25˚C –40˚C –65 –60 –55 –50 (dBm 2.0 2.5 3.0 3.5 (V) AGC UPB1009K IF IM CHARACTERISTICS 10 0 –10 –20 –30 –40 –50 –60 –75 –70 –65 –60 Input Power P (dBm CONVERSION VOLTAGE GAIN vs. 2ndIF FREQUENCY ...
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... Remark The graphs indicate nominal characteristics. 1 800 1 900 (MHz) Mkr1 = 10.0 kHz Ref = –10 dBm Span 100 kHz Center = 1.637 GHz Res BW 1 kHz Mkr1 = 10.0 kHz Span 100 kHz UPB1009K Mkr1 = 10.0 kHz Atten 5 dB Noise –81.92 dB/Hz Span 100 kHz VBW 1 kHz Sweep 300 ms (401 pts) 21 ...
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... Remark The graphs indicate nominal characteristics. 22 +10 = +25˚C –10 –20 –40.9 dBc –30 –40 –50 –60 –70 – +85˚C –42.1 dBc UPB1009K T = –40˚ SNR = 25.4 dB SINAD = 25.3 dBc SFDR = 41.1 dB ENOB = 3.91 bit THD = –40.4 dBc ANALOG INPUT FREQUENCY (MHz ...
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... V LPF GC 1/4 PLL PD OSC 1stMIX kΩ 100 UPB1009K V 100 100 kΩ – 21 100 nF 100 kΩ + – DCOFFout Ω 19 100 nF 18 100 nF 2 kΩ 100 nF ...
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... Sampling Signal Input CPout 20 AGC Input MS2 21 AGC Control Voltage Output REFin 22 PD1 Output (Default onboard : GND) PD1 CLKout 23 PD1 Output (Default on board : V 2ndIFout 24 1stIF Input 2ndIFin 25 1stIF Output DCOFFout UPB1009K Pin Name DCOFFin SCKin AGCin AGCout ) PD2 CC 1stIFin 1stIFout ...
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... LPF 1stMIX OSC PreAmp kΩ 4.7 nH 100 nF 500 MS1 MS2 UPB1009K V 100 – – IFamp 18 1 PLL Fref ...
Page 26
... Pin 1 Pin 6.2±0.2 6.0±0.2 Caution The island pins located on the corners are needed to fabricate products in our plant, but do not serve any other function. Consequently the island pins should not be soldered and should remain non-connection pins. 26 UPB1009K (Bottom View) 0.18±0.05 0.55±0.2 0.4 ...
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... UPB1009K Condition Symbol IR260 VP215 WS260 HS350 12/04/2003 A Business Partner of NEC Compound Semiconductor Devices, Ltd. 27 ...