ADSP-21366 Analog Devices, ADSP-21366 Datasheet
ADSP-21366
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ADSP-21366 Summary of contents
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... On-chip memory—3M bit of on-chip SRAM and a dedicated 4M bit of on-chip mask-programmable ROM Code compatible with all other members of the SHARC family The ADSP-21365/ADSP-21366 is available with a 333 MHz core instruction rate and unique audiocentric peripherals such as the digital audio interface, S/PDIF transceiver, ® ...
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... Transfers between memory and core at a sustained 5.4G bytes/s bandwidth at 333 MHz core instruction rate INPUT/OUTPUT FEATURES DMA controller supports: 25 DMA channels for transfers between ADSP-21365/ADSP-21366 internal memory and a variety of peripherals 32-bit DMA transfers at peripheral clock speed, in parallel with full-speed processor execution Asynchronous parallel port provides access to asynchronous ...
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... Preliminary Technical Data CONTENTS Summary 1 Key Features—Processor Core ..................................2 Input/Output Features ............................................2 Dedicated Audio Components ..................................2 General Description ..................................................4 ADSP-21365/ADSP-21366 Family Core Architecture .....4 ADSP-21365/ADSP-21366 Memory and I/O Interface Fea- tures ................................................................6 Development Tools ................................................9 Additional Information ......................................... 11 Pin Function Descriptions ........................................ 12 Address Data Pins as FLAGs .................................. 15 Address/Data Modes ............................................ 15 Boot Modes ........................................................ 15 Core Instruction Rate to CLKIN Ratio Modes ...
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... Many other SRU configura- tions are possible. 1.5 ns 6.0 ns ADSP-21365/ADSP-21366 FAMILY CORE ARCHITECTURE 13.5 ns The ADSP-21365/ADSP-21366 are code-compatible at the 23.9 ns assembly level with the ADSP-2126x, ADSP-21160 and 10.5 ns ADSP-21161, and with the first generation ADSP-2106x 16.3 ns SHARC processors. The ADSP-21365/ADSP-21366 shares architectural features with the ADSP-2126x and ADSP-2116x SIMD SHARC processors, as detailed in the following sections ...
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... FFT butterfly processing. Data Address Generators With Zero-Overhead Hardware Circular Buffer Support The ADSP-21365/ADSP-21366’s two data address generators (DAGs) are used for indirect addressing and implementing cir- cular data buffers in hardware. Circular buffers allow efficient programming of delay lines and other data structures required Rev ...
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... I/O processor single cycle. The ADSP-21365/ADSP-21366’s, SRAM can be configured as a maximum of 96K words of 32-bit data, 192K words of 16-bit data, 64K words of 48-bit instructions (or 40-bit data), or com- binations of different word sizes up to three megabits ...
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... SPI port, six flag out- puts and six flag inputs, and three timers. The IDP provides an additional input path to the ADSP-21365/ADSP-21366 core, configurable as either eight channels of I seven channels plus a single 20-bit wide synchronous parallel data acquisition port. Each data channel has its own DMA channel that is independent from the processor’ ...
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... The processors contain two serial peripheral interface ports (SPIs). The SPI is an industry-standard synchronous serial link, enabling the ADSP-21365/ADSP-21366 SPI-compatible port to communicate with other SPI-compatible devices. The SPI con- sists of two data pins, one device select pin, and one clock pin full-duplex synchronous serial interface, supporting both master and slave modes ...
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... Preliminary Technical Data Timers The ADSP-21365/ADSP-21366 each have a total of four timers: a core timer that can generate periodic software interrupts and three general purpose timers that can generate periodic inter- rupts and be independently set to operate in one of three modes: • Pulse waveform generation mode • ...
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... ADSP-21365/ADSP-21366 translation of C/C++ code to DSP assembly. The SHARC has architectural features that improve the efficiency of compiled C/C++ code. The VisualDSP++ debugger has a number of important fea- tures. Data visualization is enhanced by a plotting package that offers a significant level of flexibility. This graphical representa- tion of user data enables the programmer to quickly determine the performance of an algorithm ...
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... EZ-KIT Lite board enables high speed, non- intrusive emulation. ADDITIONAL INFORMATION This data sheet provides a general overview of the ADSP-21365/ADSP-21366 architecture and functionality. For detailed information on the ADSP-2136x family core architec- ture and instruction set, refer to the ADSP-2136x SHARC Processor Hardware Reference for the ADSP-21362/3/4/5/6 Pro- cessors and the ADSP-2136x SHARC Processor Programming Reference ...
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... T = three-state, (pd) = pull-down resis- tor, (pu) = pull-up resistor. Function Parallel Port Address/Data. The ADSP-21365/ADSP-21366 parallel port and its corre- sponding DMA unit output addresses and data for peripherals on these multiplexed pins. The multiplex state is determined by the ALE pin. The parallel port can operate in either 8-bit or 16-bit mode. Each AD pin has a 22.5 kΩ ...
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... SPI interaction, any of the master processor’s flag pins can be used to drive the SPIDS signal on the SPI slave device. SPI Master Out Slave In. If the ADSP-21365/ADSP-21366 is configured as a master, the MOSI pin becomes a data transmit (output) pin, transmitting output data. If the processor is configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving input data ...
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... Test Data Output (JTAG). Serial scan output of the boundary scan path. Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held low for proper operation of the ADSP-21365/ADSP-21366. TRST has a 22.5 kΩ internal pull-up resistor. Emulation Status. Must be connected to the processor’s JTAG emulators target board connector only. EMU has a 22.5 kΩ ...
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... FLAG6 CLKCFG1–0 FLAG7 AD15–8 Function A23–16 A7–0 A15–8 D15–8 Rev. PrC | Page May 2005 ADSP-21365/ADSP-21366 Booting Mode SPI Slave Boot SPI Master Boot Parallel Port boot via EPROM Timing Specifications 18. Core to CLKIN Ratio 6:1 32:1 16:1 and ...
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... ADSP-21365/ADSP-21366 ADSP-21365/ADSP-21366 SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS 1 Parameter V Internal (Core) Supply Voltage DDINT A Analog (PLL) Supply Voltage VDD V External (I/O) Supply Voltage DDEXT 2 V High Level Input Voltage @ Low Level Input Voltage @ High Level Input Voltage @ V IH_CLKIN V Low Level Input Voltage @ V ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-21365/ADSP-21366 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... ADSP-21365/ADSP-21366 TIMING SPECIFICATIONS The ADSP-21365/ADSP-21366’s internal clock (a multiple of CLKIN) provides the clock signal for timing internal memory, processor core, serial ports, and parallel port (as required for read/write strobes in asynchronous access mode). During reset, program the ratio between the processor’s internal clock fre- quency and external (CLKIN) clock frequency with the CLKCFG1– ...
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... Table 12. If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time, resulting in 4097 t RSTVDD t IVDDEVDD t CLKVDD t CLKRST t PLLRST Figure 6. Power-Up Sequencing Rev. PrC | Page May 2005 ADSP-21365/ADSP-21366 Min Max 0 –50 200 0 200 4096t + ...
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... ADSP-21365/ADSP-21366 Clock Input Table 11. Clock Input Parameter Timing Requirements t CLKIN Period CK t CLKIN Width Low CKL t CLKIN Width High CKH t CLKIN Rise/Fall (0.4 V–2.0 V) CKRF 3 t CCLK Period CCLK 1 Applies only for CLKCFG1– and default values for PLL control bits in PMCTL. ...
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... IRQ1, and IRQ2 interrupts. Table 13. Interrupts Parameter Timing Requirement t IRQx Pulse Width IPW Min WRST Figure 9. Reset Min 2 × t PCLK DAI20-1 FLAG2-0 (IRQ2-0) t IPW Figure 10. Interrupts Rev. PrC | Page May 2005 ADSP-21365/ADSP-21366 Max Unit SRST Max Unit +2 ns ...
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... ADSP-21365/ADSP-21366 Core Timer The following timing specification applies to FLAG3 when it is configured as the core timer (CTIMER). Table 14. Core Timer Parameter Switching Characteristic t CTIMER Pulse Width WCTIM FLAG3 (CTIMER) Timer PWM_OUT Cycle Timing The following timing specification applies to Timer0, Timer1, and Timer2 in PWM_OUT (pulse width modulation) mode. ...
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... Delay DAI Pin Input Valid to DAI Output Valid DPIO Min 2 t PCLK t PWI Figure 13. Timer Width Capture Timing Min 1.5 DAI_Pn DAI_Pm t DPIO Figure 14. DAI Pin to Pin Direct Routing Rev. PrC | Page May 2005 ADSP-21365/ADSP-21366 Max Unit 31 2(2 – PCLK Max Unit 10 ns ...
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... ADSP-21365/ADSP-21366 Precision Clock Generator (Direct Pin Routing) This timing is only valid when the SRU is configured such that the precision clock generator (PCG) takes its inputs directly from the DAI pins (via pin buffers) and sends its outputs directly to the DAI pins. For the other cases, where the PCG’s Table 18 ...
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... FLAG3–0 IN Pulse Width FIPW Switching Characteristic t FLAG3–0 OUT Pulse Width FOPW DAI_P20-1 (FLAG3-0 (DATA31-0) DAI_P20-1 (FLAG3-0 (DATA31-0) for Min 2 × × FIPW ) OUT t FOPW Figure 16. Flags Rev. PrC | Page May 2005 ADSP-21365/ADSP-21366 Max Unit + 3 ns PCLK – PCLK ...
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... ADSP-21365/ADSP-21366 Memory Read—Parallel Port Use these specifications for asynchronous interfacing to memo- ries (and memory-mapped peripherals) when the ADSP-21365/ADSP-21366 is accessing external memory space. Table 20. 8-Bit Memory Read Cycle Parameter Timing Requirements 1 t AD7–0 Data Setup Before RD High DRS t AD7–0 Data Hold After RD High ...
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... VALID DATA VALID ADDRESS RD 0, ONLY ONE PULSE OCCURS BETWEEN ALE CYCLES. RD PULSES OCCUR BETWEEN ALE CYCLES. FOR COMPLETE INFORMATION, Figure 18. Read Cycle for 16-Bit Memory Timing Rev. PrC | Page May 2005 ADSP-21365/ADSP-21366 Min Max 3 × t – 2 PCLK t – 2.5 PCLK 2 × ...
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... ADSP-21365/ADSP-21366 Memory Write—Parallel Port Use these specifications for asynchronous interfacing to memo- ries (and memory-mapped peripherals) when the ADSP-21365/ADSP-21366 is accessing external memory space. Table 22. 8-Bit Memory Write Cycle Parameter Switching Characteristics: t ALE Pulse Width ALEW 1 t AD15–0 Address Setup Before ALE Deasserted ...
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... ADDRESS t DWS WR 0, ONLY ONE PULSE OCCURS BETWEEN ALE CYCLES. WR PULSES OCCUR BETWEEN ALE CYCLES. FOR COMPLETE INFORMATION, Figure 20. Write Cycle for 16-Bit Memory Timing Rev. PrC | Page May 2005 ADSP-21365/ADSP-21366 Min Max 2 × t – 2 PCLK t – 2.5 PCLK 2 × t – 3.8 PCLK ...
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... ADSP-21365/ADSP-21366 Serial Ports To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width. Table 24. Serial Ports—External Clock ...
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... SAMPLE DRIVE t t SFSE/I HFSE/I t DDTE/I t DDTENFS t HDTE/I 1ST BIT t DDTLFSE DATA CHANNEL A/B) ARE ROUTED TO THE DAI_P20-1 PINS 1 Figure 21. External Late Frame Sync Rev. PrC | Page May 2005 ADSP-21365/ADSP-21366 Max Unit Max Unit 2ND BIT 2ND BIT ...
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... ADSP-21365/ADSP-21366 DATA RECEIVE—INTERNAL CLOCK DRIVE EDGE t SCLKIW DAI_P20-1 (SCLK) t DFSI t HOFSI DAI_P20-1 (FS) DAI_P20-1 (DATA CHANNEL A/B) NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE. DATA TRANSMIT—INTERNAL CLOCK DRIVE EDGE t SCLKIW DAI_P20-1 ...
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... DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins. DAI_P20-1 (SCLK) DAI_P20-1 (FS) DAI_P20-1 (SDATA) Table 28. IDP Min SAMPLE EDGE t IPDCLK t IPDCLKW t t SISFS SIHFS t t SISD SIHD Figure 23. IDP Master Timing Rev. PrC | Page May 2005 ADSP-21365/ADSP-21366 Max Unit ...
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... ADSP-21365/ADSP-21366 Parallel Data Acquisition Port (PDAP) The timing requirements for the PDAP are provided in Table 29. PDAP is the parallel mode operation of Channel 0 of the IDP. For details on the operation of the IDP, see the IDP chapter of the ADSP-2136x SHARC Processor Hardware Refer- ence for the ADSP-21362/3/4/5/6 Processors. Note that the most Table 29 ...
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... SAMPLE EDGE t SRCCLK t SRCCLKW t t SRCSFS SRCHFS t t SRCSD SRCHD Figure 26. SRC Serial Input Port Timing Rev. PrC | Page May 2005 ADSP-21365/ADSP-21366 Max Unit 16 (2 – – PCLK 16 (2 – PCLK Max Unit ...
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... ADSP-21365/ADSP-21366 Sample Rate Converter—Serial Output Port For the serial output port, the frame-sync is an input and it should meet setup and hold times with regard to SCLK on the output port. The serial data output, SDATA, has a hold time Table 32. SRC, Serial Output Port ...
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... LSB+2 LSB+1 LSB MSB MSB-1 2 Figure 29. I S-Justified Mode LSB+1 LSB MSB MSB-1 MSB-2 Figure 30. Left-Justified Mode Rev. PrC | Page May 2005 ADSP-21365/ADSP-21366 RIGHT CHANNEL MSB MSB-1 MSB-2 LSB+2 LSB+1 LSB MSB-2 LSB+2 LSB+1 LSB RIGHT CHANNEL LSB+2 LSB+1 LSB ...
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... ADSP-21365/ADSP-21366 SPDIF Transmitter Input Data Timing The timing requirements for the Input Port are given in Table 33. Input Signals (SCLK, FS, SDATA) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifica- tions provided below are valid at the DAI_P20–1 pins. ...
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... SCLK frequency where FS = the frequency of LRCLK. DAI_P20-1 (DATA CHANNEL A/B) Min –2 –2 38 DRIVE EDGE t SCLKIW DAI_P20-1 (SCLK) t DFSI t HOFSI DAI_P20-1 (FS) t DDTI t HDTI Figure 32. SPDIF Receiver Internal Digital PLL Mode Timing Rev. PrC | Page May 2005 ADSP-21365/ADSP-21366 Max Unit SAMPLE EDGE ...
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... ADSP-21365/ADSP-21366 SPI Interface—Master The ADSP-21365/ADSP-21366 contains two SPI ports. The pri- mary has dedicated pins and the secondary is available through the DAI. The timing provided in Table 36 to both. Table 36. SPI Interface Protocol—Master Switching and Timing Specifications Parameter Timing Requirements ...
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... Reference for the ADSP-21362/3/4/5/6 Processors, “Serial Peripheral Interface Port” chapter. Min 4 × × × × × × × × t Rev. PrC | Page May 2005 ADSP-21365/ADSP-21366 Max Unit – PCLK – PCLK – PCLK ns PCLK PCLK ns PCLK ...
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... ADSP-21365/ADSP-21366 SPIDS (INPUT SPICLK ( (INPUT SPICLK ( (INPUT MISO (OUTPUT) t CPHASE = MOSI (INPUT MISO MSB (OUTPUT) CPHASE = 0 ...
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... SYSTEM INPUTS SYSTEM OUTPUTS Min TCK t t STAP HTAP t DTDO t t SSYS HSYS t DSYS Figure 35. IEEE 1149.1 JTAG Test Access Port Rev. PrC | Page May 2005 ADSP-21365/ADSP-21366 Max Unit ÷ ...
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... ADSP-21365/ADSP-21366 OUTPUT DRIVE CURRENTS Figure 36 shows typical I-V characteristics for the output driv- ers of the ADSP-21365/ADSP-21366. The curves represent the current drive capability of the output drivers as a function of output voltage 3.11V, 125°C 0 -10 3.11V, 125°C - -30 3.47V, -45° ...
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... LOAD CAPACITANCE (pF) Figure 41. Typical Output Delay or Hold vs. Load Capacitance (at Ambient Temperature) THERMAL CHARACTERISTICS The ADSP-21365/ADSP-21366 processor is rated for perfor- mance over the temperature range specified in Operating Conditions on page 16. Table 39 through Table 42 airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6 and the junction-to- board measurement complies with JESD51-8 ...
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... ADSP-21365/ADSP-21366 Table 42. Thermal Characteristics for 144-Lead Integrated Heat Sink (INT–HS) LQFP (With heat slug soldered to PCB) Parameter Condition θ Airflow = 0 m/s JA θ Airflow = 1 m/s JMA θ Airflow = 2 m/s JMA θ JC Ψ Airflow = 0 m/s JT Ψ Airflow = 1 m/s JMT Ψ Airflow = 2 m/s JMT Typical Unit 16.50 °C/W 15.14 ° ...
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... Preliminary Technical Data 136-BALL BGA PIN CONFIGURATIONS The following table shows the ADSP-21365/ADSP-21366’s pin names and their default function after reset (in parentheses). Table 43. 136-Ball Mini-BGA Pin Assignments Ball Name Ball No. Ball Name CLKCFG0 A01 CLKCFG1 XTAL A02 GND TMS A03 ...
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... ADSP-21365/ADSP-21366 Table 43. 136-Ball Mini-BGA Pin Assignments (Continued) Ball Name Ball No. Ball Name AD5 J01 AD3 AD4 J02 V DDINT GND J04 GND GND J05 GND GND J06 GND GND J09 GND GND J10 GND GND J11 GND V J13 GND DDINT DAI_P16 (SD4B) ...
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... DDINT VDD GND V A I/O SIGNALS DDEXT VSS * USE THE CENTER BLOCK OF GROUND PINS TO PROVIDE THERMAL PATHWAYS TO YOUR PRINTED CIRCUIT BOARD’S GROUND PLANE. Rev. PrC | Page May 2005 ADSP-21365/ADSP-21366 ...
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... ADSP-21365/ADSP-21366 144-LEAD LQFP PIN CONFIGURATIONS The following table shows the ADSP-21365/ADSP-21366’s pin names and their default function after reset (in parentheses). Table 44. 144-Lead LQFP Pin Assignments Pin Name Pin No. Pin Name DDINT DDINT CLKCFG0 2 GND CLKCFG1 3 RD BOOTCFG0 4 ALE BOOTCFG1 ...
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... Preliminary Technical Data PACKAGE DIMENSIONS The ADSP-21365/ADSP-21366 is available in a 136-ball Mini- BGA package and a 144-lead integrated heat sink LQFP package. 12.00 BSC SQ PIN A1 INDICATOR TOP VIEW 1.70 MAX 1. DIMENSIONS ARE IN MILIMETERS (MM). 2. THE ACTUAL POSITION OF THE BALL GRID IS WITHIN 0. ITS IDEAL POSITION RELATIVE TO THE PACKAGE EDGES ...
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... ADSP-21365/ADSP-21366 0.27 0.22 TYP 0.17 SEATING PLANE 0.08 MAX (LEAD COPLANARITY) 0.15 0.05 1.45 0.75 1.40 0.60 TYP 1.35 0.45 1.60 MAX DE TAIL A NOTES: 1. DIMENSIONS ARE IN MILLIMETERS AND COMPLY WITH JEDEC STANDARD MS-026-BFB-HD. 2. ACTUAL POSITION O F EACH LEAD IS WITHIN 0.08 OF ITS IDEAL PO SITIO N, WHEN MEASURED IN THE LATERAL DIRECTION. 3. CENTER DIMENSIONS ARE NOMINAL. 4. HEATSLUG IS COINCIDENT WI TH BOTTO M SURFACE AND DOES NOT PROTRUDE BEYOND IT ...
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... Preliminary Technical Data ORDERING GUIDE Analog Devices offers a wide variety of audio algorithms and combinations to run on the ADSP-21365/ADSP-21366 proces- sor. These products are sold as part of a chipset, bundled with necessary application software under special part numbers. For a complete list, visit our website at www.analog.com/SHARC. ...
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... ADSP-21365/ADSP-21366 Rev. PrC | Page May 2005 Preliminary Technical Data ...
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... Preliminary Technical Data Rev. PrC | Page May 2005 ADSP-21365/ADSP-21366 ...
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... ADSP-21365/ADSP-21366 © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Rev. PrC | Page May 2005 Preliminary Technical Data ...
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