ADV7179 Analog Devices, ADV7179 Datasheet
ADV7179
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ADV7179 Summary of contents
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... FILTER REAL-TIME CONTROL MPU PORT CIRCUIT SCLOCK SDATA ALSB SCRESET/RTC Figure 1. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.326.8703 ADV7174/ADV7179 2 C® compatible and fast 10-BIT L DAC A (PIN 29) DAC T YUV RBG 10 10-BIT P ...
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... ADV7174/ADV7179 TABLE OF CONTENTS Specifications..................................................................................... 4 2.8 V Specifications ...................................................................... 4 2.8 V Timing Specifications ........................................................ 5 3.3 V Specifications ...................................................................... 6 3.3 V Timing Specifications ........................................................ 7 Absolute Maximum Ratings............................................................ 9 ESD Caution.................................................................................. 9 Pin Configuration and Function Descriptions........................... 10 General Description ....................................................................... 11 Data Path Description................................................................ 11 Internal Filter Response............................................................. 11 Typical Performance Characteristics ........................................... 13 Features ............................................................................................ 16 Color Bar Generation ................................................................ 16 Square Pixel Mode...................................................................... 16 Color Signal Control ...
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... Change to Figure 55 ........................................................................39 Change to Figure 79 ........................................................................48 Changed Ordering Guide Temperature Specifications ..............52 Updated Outline Dimensions........................................................52 10/02—Revision 0: Initial Version NTSC Waveforms (without Pedestal) ......................................46 PAL Waveforms ........................................................................... Waveforms.........................................................................48 Appendix 7—Optional Output Filter ...........................................49 Appendix 8—Recommended Register Values.............................50 Outline Dimensions........................................................................52 Ordering Guide ...........................................................................52 Rev Page ADV7174/ADV7179 ...
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... ADV7174/ADV7179 SPECIFICATIONS 2.8 V SPECIFICATIONS 1.235 150 Ω. All specifications T AA REF SET Table 1. Parameter STATIC PERFORMANCE 2 Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity Differential Nonlinearity 2 DIGITAL INPUTS Input High Voltage, V INH Input Low Voltage, V INL Input Current Input Capacitance, C ...
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... Teletext Port consists of the following: Teletext Output: TTXREQ Teletext Input: TTX unless otherwise noted. MIN MAX 1 Conditions After this period the first clock is generated Relevant for repeated start condition Rev Page ADV7174/ADV7179 Min Typ Max Unit 0 400 kHz 0.6 µs 1.3 µs 0.6 µ ...
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... ADV7174/ADV7179 3.3 V SPECIFICATIONS 3.0 V–3 1.235 REF SET Table 3. Parameter 3 STATIC PERFORMANCE Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity Differential Nonlinearity 3 DIGITAL INPUTS Input High Voltage, V INH Input Low Voltage, V INL 3, 4 Input Current Input Capacitance DIGITAL OUTPUTS ...
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... Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition. 6 See Figure 60. = 150 Ω. All specifications MIN MAX 1 Conditions After this period, the first clock is generated Relevant for repeated start condition Rev Page ADV7174/ADV7179 2 , unless otherwise noted. Min Typ Max 0 400 0.6 1.3 0.6 0.6 ...
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... ADV7174/ADV7179 SDATA SCLOCK CLOCK HSYNC, CONTROL FIELD/VSYNC, I/PS S BLANK PIXEL INPUT DATA HSYNC, CONTROL FIELD/VSYNC, O/PS BLANK TTXREQ t 16 CLOCK TTX 4 CLOCK CYCLES Figure 2. MPU Port Timing Diagram Figure 3. Pixel and Control Data Timing Diagram ...
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... This is a stress + 0 rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability AA Rev Page ADV7174/ADV7179 ...
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... TTL Address Input. This signal sets up the LSB of the MPU address. RESET I This input resets the on-chip timing generator and sets the ADV7174/ADV7179 into default mode. This is NTSC operation, Timing Slave Mode 0, 8-bit operation, 2× composite out signals. DACs A, B, and C are enabled. TTX I Teletext Data ...
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... The ADV7174/ADV7179 modes are set up over a 2-wire serial 2 bidirectional port (I C compatible) with two slave addresses. The ADV7174/ADV7179 is packaged in a 40-lead 6 mm × LFCSP package. DATA PATH DESCRIPTION For PAL B/D/G/H/I/M/N and NTSC M and N modes, YCrCb 4:2:2 data is input via the CCIR-656 compatible pixel port MHz data rate ...
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... ADV7174/ADV7179 Table 7. Luminance Internal Filter Specifications Filter Type Filter Selection MR04 MR03 MR02 Low-Pass (NTSC) Low-Pass (PAL) Notch (NTSC Notch (PATL Extended (SSAF) CIF QCIF Table 8. Chrominance Internal Filter Specifications Filter Type Filter Selection ...
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... Rev Page ADV7174/ADV7179 FREQUENCY (MHz) Figure 9. PAL Notch Luma Filter FREQUENCY (MHz) Figure 10. Extended Mode (SSAF) Luma Filter ...
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... ADV7174/ADV7179 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) Figure 12. QCIF Luma Filter 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) Figure 13. 1.3 MHz Low-Pass Chroma Filter 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) Figure 14 ...
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... FREQUENCY (MHz) Figure 18. QCIF Chroma Filter 12 Rev Page ADV7174/ADV7179 ...
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... SUBCARRIER RESET Together with the SCRESET/RTC pin and Bits MR22 and MR21 of Mode Register 2, the ADV7174/ADV7179 can be used in subcarrier reset mode. The subcarrier resets to Field 0 at the start of the following field when a low-to-high transition occurs on this input pin. ...
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... RTC TIME SLOT: 01 NOT USED IN THE ADV7174/ADV7179 NOTES 1 F PLL INCREMENT IS 22 BITS LONG, VALUE LOADED INTO ADV7174/ADV7179 PLL INCREMENT BITS 21:0 PLUS BITS 0:9 OF THE SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD SC BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS OF THE ADV7174/ADV7179. 2 SEQUENCE BIT ...
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... ADV7174/ADV7179 ANALOG VIDEO INPUT PIXELS Y NTSC/PAL M SYSTEM (525 LlNES/60Hz) PAL SYSTEM (625 LINES/50Hz) END OF ACTIVE DISPLAY 522 523 524 525 DISPLAY 260 261 262 263 264 H V ODD FIELD F EAV CODE ...
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... EVEN FIELD F ANALOG VIDEO Figure 23. Timing Mode 0 Data Transitions (Master Mode) VERTICAL BLANK VERTICAL BLANK 318 314 315 316 317 319 Figure 22. Timing Mode 0 (PAL Master Mode) Rev Page ADV7174/ADV7179 DISPLAY DISPLAY 335 336 320 334 ...
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... ADV7174/ADV7179 Mode 1: Slave Option HSYNC , BLANK , FIELD (Timing Register 0 TR0 = this mode, the ADV7174/ADV7179 accepts horizontal SYNC and odd/even FIELD signals. A transition of the FIELD input DISPLAY 522 523 524 525 1 HSYNC BLANK FIELD DISPLAY 260 261 262 ...
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... Mode 1: Master Option HSYNC , BLANK , FIELD (Timing Register 0 TR0 = this mode, the ADV7174/ADV7179 can generate horizontal SYNC and odd/even FIELD signals. A transition of the FIELD input when HSYNC is low indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input ...
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... ADV7174/ADV7179 Mode 2: Slave Option HSYNC , VSYNC , BLANK (Timing Register 0 TR0 = this mode, the ADV7174/ADV7179 accepts horizontal and vertical SYNC signals. A coincident low transition of both and VSYNC inputs indicates the start of an odd field. A VSYNC low DISPLAY 522 ...
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... Mode 2: Master Option HSYNC , VSYNC , BLANK (Timing Register 0 TR0 = this mode, the ADV7174/ADV7179 can generate horizontal and vertical SYNC signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field ...
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... ADV7174/ADV7179 Mode 3: Master/Slave Option HSYNC , BLANK , FIELD (Timing Register 0 TR0 = this mode, the ADV7174/ADV7179 accepts or generates horizontal SYNC and odd/even FIELD signals. A transition of the FIELD input when HSYNC is high indicates a new frame, ...
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... These are unique addresses for each device and are illustrated in Figure 33 and Figure 34. The LSB sets either a read or write operation. Logic 1 corresponds to a read operation, while Logic 0 corresponds to a write operation set by setting the ALSB pin of the ADV7174/ ADV7179 to Logic 0 or Logic ...
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... If an invalid subaddress is issued by the user, the ADV7174/ ADV7179 cannot issue an acknowledge and returns to the idle condition auto-increment mode the user exceeds the highest subaddress, the following action is taken: 1 ...
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... The subaddress register determines to/from which register the operation takes place. SR7 SR6 SR5 SR4 SR7 – SR6(000) ZERO SHOULD BE WRITTEN TO THESE BITS ADV7179 SUBADDRESS REGISTER SR5 SR4 SR3 SR2 SR1 SR0 MODE REGISTER 0 0 ...
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... Figure 38. Mode Register 0 Description These bits are used to set up the ENCODE mode. The ADV7174/ADV7179 can be set up to output NTSC, PAL (B/D/G/H/I), and PAL (M and N) standard video. PAL M is available on the ADV7174 only. These bits specify which luminance filter selected. The filter selection is made independent of whether PAL or NTSC is selected ...
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... These bits control the fields on which closed captioning data is displayed; closed captioning information can be displayed on an odd field, even field, or both fields. These bits can be used to power down the DACs. Power-down can be used to reduce the power consumption of the ADV7174/ADV7179 if any of the DACs are not required in the application. A Logic 1 must be written to this register. ...
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... This bit is used to set up square pixel mode. This is available in slave mode only. For NTSC, a 24.5454 MHz clock must be supplied. For PAL, a 29.5 MHz clock must be supplied. These bits control the genlock feature of the ADV7174/ ADV7179. Setting MR21 to Logic 1 configures the SCRESET/RTC pin as an input. Setting MR22 to Logic 0 configures the SCRESET/RTC pin as a subcarrier reset input ...
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... CVBS C Y CVBS Rev Page ADV7174/ADV7179 MR32 MR31 MR30 MR30 MR31 DISABLE RESERVED ENABLE DAC OUTPUT DAC B DAC C BLUE/COMP/Pb RED/CHROMA/Pr BLUE/COMP/Pb RED/CHROMA/Pr CVBS: Composite Video Baseband Signal Y: Luminance Component Signal (For YPbPr or Y/C Mode) C: Chrominance Signal (For Y/C Mode) ...
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... When this bit is set (1), sleep mode is enabled. With this mode enabled, the ADV7174/ADV7179 power consumption is reduced to typically 200 nA. The I can be written to and read from when the ADV7174/ADV7179 is in sleep mode. If MR46 is set to a (0) when the device is in sleep mode, the ADV7174/ADV7179 comes out of sleep mode and resumes normal operation ...
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... Figure 43. Timing Register 0 Description This bit controls whether the ADV7174/ADV7179 is in master or slave mode. These bits control the timing mode of the ADV7174/ADV7179. These modes are described in more detail in the 3.3 V Timing Specifications table. This bit controls whether the BLANK input is used when the part is in slave mode. ...
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... These bits adjust the HSYNC pulse width. These bits adjust the position of the HSYNC output relative to the FIELD/VSYNC output. When the ADV7174/ADV7179 is in Timing Mode 1, these bits adjust the position of the HSYNC output relative to the FIELD output rising edge. When the ADV7174/ADV7179 is configured in Timing Mode 2, these bits adjust the VSYNC pulse width ...
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... REG 0 Figure 45. Subcarrier Frequency Register CED15 CED14 CED13 CED12 CED11 CED10 CED7 CED6 CED5 CED4 CED3 CED2 Figure 46. Closed Captioning Extended Data Register Rev Page ADV7174/ADV7179 FSC26 FSC25 FSC24 FSC18 FSC17 FSC16 FSC10 FSC9 FSC8 FSC2 FSC1 FSC0 CED9 CED8 ...
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... ADV7174/ADV7179 CLOSED CAPTIONING ODD FIELD DATA REGISTERS 1–0 Bits: CCD15–CCD0 Subaddress: SR4–SR0 = 10H–11H These 8-bit-wide registers are used to set up the closed captioning data bytes on odd fields. Figure 47 shows how the high and low bytes are set up in the registers. ...
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... CGMS data ONLY in these bit positions, i.e., WSS data does not share this location. When this bit is enabled (1), the last six bits of the CGMS data, i.e., the CRC check sequence, are calculated internally by the ADV7174/ADV7179. If this bit is disabled (0), the CRC values in the register are output to the CGMS data stream. ...
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... ADV7174/ADV7179 CGMS_WSS REGISTER 1 (C/W1) Bits: C/W17–C/W10 Address : SR4–SR0 = 17H CGMS_WSS Register 8-bit-wide register. Figure 52 shows the operations under the control of this register. C/W17 C/W17 – C/W16 CGMS DATA BITS Table 19. C/W1 Bit Description Bit Name Bit No. CGMS/WSS Data Bits C/W15– ...
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... The ground plane should encompass all ADV7174/ADV7179 ground pins, voltage reference circuitry, power supply bypass circuitry for the ADV7174/ADV7179, the analog output traces, and all the digital signal traces leading up to the ADV7174/ ADV7179. The ground plane is the board’s common ground plane. 3. ...
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... MHz clock. This 13.5 MHz clock can be used if the 13.5 MHz clock is required by the MPEG decoder. This guarantees that the Cr and Cb pixel information is input to the ADV7174/ADV7179 in the correct sequence. ) and not to the CC Note that the exposed metal paddle on the bottom side of the ...
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... FCC Code of Federal Regulations (CFR) 47 Section 15.119 and EIA-608 describe the closed captioning information for Lines 21 and 284. The ADV7174/ADV7179 uses a single buffering method. This means that the closed captioning buffer is only one byte deep, therefore there will be no frame delay in outputting the closed captioning data unlike other 2-byte deep buffering systems ...
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... C/W06 control whether or not CGMS data is output on odd and even fields. CGMS data can only be transmitted when the ADV7174/ ADV7179 is configured in NTSC mode. The CGMS data is 20 bits long, the function of each of these bits is as shown below. The CGMS data is preceded by a reference pulse of the same amplitude and duration as a CGMS bit (see Figure 57) ...
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... APPENDIX 4—WIDE SCREEN SIGNALING (WSS) The ADV7174/ADV7179 supports WSS, conforming to the standard. WSS data is transmitted on Line 23. WSS data can only be transmitted when the ADV7174/ ADV7179 is configured in PAL mode. The WSS data is 14 bits long, the function of each of these bits is as shown below. The WSS data is preceded by a run-in sequence and a start code (see Figure 58) ...
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... Thus, 37 TTX bits correspond to 144 clocks (27 MHz) and each bit has a width of almost four clock cycles. The ADV7174/ ADV7179 uses an internal sequencer and variable phase inter- polation filter to minimize the phase jitter and thus generate a band-limited signal that can be output on the CVBS and Y outputs ...
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... Figure 61. NTSC Composite Video Levels 714.2mV Figure 62. NTSC Luma Video Levels 629.7mV (p-p) Figure 63. NTSC Chroma Video Levels 720.8mV Figure 64. NTSC RGB Video Levels Rev Page ADV7174/ADV7179 1268.1mV PEAK COMPOSITE 1048.4mV REF WHITE BLACK LEVEL 387.6mV 334.2mV BLANK LEVEL SYNC LEVEL 48 ...
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... ADV7174/ADV7179 NTSC WAVEFORMS (WITHOUT PEDESTAL) 130.8 IRE 100 IRE 0 IRE –40 IRE 100 IRE 0 IRE –40 IRE 978mV 286mV (p-p) 650mV 299.3mV 0mV 100 IRE 0 IRE –40 IRE 714.2mV BLANK/BLACK LEVEL Figure 65. NTSC Composite Video Levels 714.2mV BLANK/BLACK LEVEL Figure 66. NTSC Luma Video Levels 694 ...
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... Figure 69. PAL Composite Video Levels 696.4mV Figure 70. PAL Luma Video Levels 672mV (p-p) Figure 71. PAL Chroma Video Levels 698.4mV Figure 72. PAL RGB Video Levels Rev Page ADV7174/ADV7179 PEAK CHROMA BLANK/BLACK LEVEL PEAK CHROMA REF WHITE BLANK/BLACK LEVEL SYNC LEVEL PEAK CHROMA ...
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... ADV7174/ADV7179 Pb Pr WAVEFORMS +334mV +171mV BETACAM LEVEL 0mV –171mV –334mV –05mV Figure 73. NTSC 100% Color Bars, No Pedestal Pb Levels +309mV +158mV BETACAM LEVEL 0mV –158mV –309mV –467mV Figure 74. NTSC 100% Color Bars with Pedestal Pb Levels +232mV +118mV SMPTE LEVEL 0mV –118mV –232mV – ...
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... APPENDIX 7—OPTIONAL OUTPUT FILTER If an output filter is required for the CVBS, Y, UV, chroma, and RGB outputs of the ADV7174/ADV7179, the filter shown in Figure 79 can be used. Plots of the filter characteristics are shown in Figure 80. An output filter is not required if the outputs of the ADV7174/ADV7179 are connected to most analog monitors or analog TVs ...
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... ADV7174/ADV7179 APPENDIX 8—RECOMMENDED REGISTER VALUES The ADV7174/ADV7179 registers can be set depending on the user standard required. The power-on reset values can be found in Figure 37. The following examples give the various register formats for several video standards. In each case, the output is set to compos- ite output with all DACs powered up and with the input control disabled ...
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... CGMS_WSS Register 1 00H 18H CGMS_WSS Register 2 00H 19H Teletext Request Control Register 1 On power-up, this register is set to 16h. 1Eh should be written here for correct Rev Page ADV7174/ADV7179 = 3.5795454 MHz) Data 00H 10H 00H 00H 10H 00H 00H 1 1EH 7CH ...
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... ORDERING GUIDE Model Temperature Range ADV7179KCP 0°C to 70°C ADV7179KCP-REEL 0°C to 70°C ADV7179BCP −40°C to +85°C ADV7179BCP-REEL −40°C to +85°C ADV7174KCP 0°C to 70°C ADV7174KCP-REEL 0°C to 70°C ADV7174BCP −40°C to +85°C ADV7174BCP-REEL −40°C to +85°C ...