XPC850DEZT50B Motorola, XPC850DEZT50B Datasheet

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Advance Information MPC850EC/D Rev. 0.2, 04/2002 MPC850 (Rev. A/B/C) Communications Controller Hardware Specifications This document contains detailed information on power considerations, AC/DC electrical characteristics, and AC timing specifications for revision A,B, and C of the MPC850. This document contains the ...

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... Additional documentation may be provided for parts listed in Table 1. 2 MPC850 (Rev. A/B/C) Hardware Specifications Table 1. MPC850 Functionality Matrix Ethernet ATM Support USB Support Support Yes - Yes - Yes Yes Number of Multi-channel PCMCIA Slots HDLC Support Supported Yes - Yes - Yes Yes MOTOROLA ...

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... The following list summarizes the main features of the MPC850: • Embedded single-issue, 32-bit MPC8xx core (implementing the PowerPC architecture) with thirty-two 32-bit general-purpose registers (GPRs) — Performs branch folding and branch prediction with conditional prefetch, but without conditional execution MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications 3 ...

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... Selectable write protection — On-chip bus arbiter supports one external bus master — Special features for burst mode support • General-purpose timers — Four 16-bit timers or two 32-bit timers — Gate mode can enable/disable counting 4 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA ...

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... Totally transparent (frame based with optional cyclic redundancy check (CRC)) • QUICC multichannel controller (QMC) microcode features — independent communication channels on a single SCC — Arbitrary mapping of 0–31 channels to any of 0–31 TDM time slots MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications stops transmission GRACEFUL STOP TRANSMIT CLOSE RXBD ...

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... Separate power supply input to operate internal logic at 2.2 V when operating at or below 25 MHz — Can be dynamically shifted between high frequency (3.3 V internal) and low frequency (2.2 V internal) operation • Debug interface — Eight comparators: four operate on instruction address, two operate on data address, and two operate on data 6 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA ...

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... Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either GND or V package thermal characteristics for the MPC850. MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications Table 2. Maximum Ratings Symbol VDDH -0 ...

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... TBD Table 5. DC Electrical Specifications Symbol VDDH, VDDL, KAPWR, VDDSYN VDDH, VDDL, KAPWR, VDDSYN Value Unit C/W 8 C/W available from your local Motorola sales , 1 watt MPC850 dissipation, and a board ) Maximum Unit 515 mW 590 mW 725 mW Min Max 3.0 3.6 3.135 3.465 VIH 2 ...

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... Package thermal resistance INT I watts—chip internal power , INT Power dissipation on input and output pins—user determined I/O MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications Symbol VIHC VOH VOL can be obtained from the equation ( junction to ambient C Min Max ...

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... If P INT I/O (2) • Using this value of K the values power supply should be bypassed to ground using at least four 0.1 CC and GND should be kept to less than half an inch CC is neglected an approximate relationship , and T can be obtained by solving D J and GND planes. CC MOTOROLA ...

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... B8b CLKOUT to BR, BG, VFLS[0–1], VF[0–2], IWP[0–2], FRZ, 4 LWP[0–1], STS valid B9 CLKOUT to A[6–31] RD/WR, BURST, D[0–31], DP[0–3], TSIZ[0–1], REG, RSV, AT[0–3], PTR high-Z MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications Table 6. Bus Operation Timing 50 MHz 66 MHz Min Max Min Max 20 — ...

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... Cap Load FFACT (default Unit Max 50 pF) 12.25 0.250 50.00 ns 9.25 — 50.00 ns 13.00 0.250 50.00 ns 11.00 — 50.00 ns 20.25 0.250 50.00 ns 15.00 — 50.00 ns 10.00 — 50.00 ns 15.00 — 50.00 ns — — 50.00 ns — — 50.00 ns — — 50.00 ns — — 50.00 ns — — 50.00 ns — — 50.00 ns — — 50.00 ns — — 50.00 ns — — — — 13.00 0.250 50.00 ns 8.00 — 50.00 ns 13.00 0.250 50.00 ns MOTOROLA ...

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... TRLX = 0,1 CSNT = 1, ACS = 10 or ACS = 11, EBDF = 1 B29 WE[0–3] negated to D[0–31], DP[0–3] high-Z GPCM write access, CSNT = 0 B29a WE[0–3] negated to D[0–31], DP[0–3] high-Z GPCM write access, TRLX = 0 CSNT = 1, EBDF = 0 MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications 1 (continued) 50 MHz 66 MHz 80 MHz Min Max Min ...

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... Cap Load FFACT (default Unit Max 50 pF) — 0.250 50.00 ns — 0.500 50.00 ns — 1.500 50.00 ns — 1.500 50.00 ns — 0.375 50.00 ns — 0.375 50.00 ns — 1.375 50.00 ns — 1.375 50.00 ns — 0.250 50.00 ns — 0.500 50.00 ns MOTOROLA ...

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... CLKOUT falling edge to BS valid - as requested by control bit BST4 in the corresponding word in the UPM B32a CLKOUT falling edge to BS valid - as requested by control bit BST1 in the corresponding word in the UPM, EBDF = 0 MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications 1 (continued) 50 MHz 66 MHz 80 MHz Min ...

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... Cap Load FFACT (default Unit Max 50 pF) 8.00 — 50.00 ns 13.00 0.250 50.00 ns 0.375 50.00 ns 6.00 — 50.00 ns 13.00 0.250 50.00 ns — 0.250 50.00 ns — 0.500 50.00 ns — 0.750 50.00 ns — 0.250 50.00 ns — 0.500 50.00 ns — 0.750 50.00 ns — 0.250 50.00 ns MOTOROLA ...

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... BG input is relevant when the MPC850 is selected to work with the external bus arbiter. 7 The D[0–31] and DP[0–3] input timings B20 and B21 refer to the rising edge of the CLKOUT in which the TA input signal is asserted. MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications 1 (continued) ...

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... The AS signal is considered asynchronous to CLKOUT. Figure 2 is the control timing diagram. CLKOUT Outputs Outputs Inputs Inputs A Maximum output delay specification B Minimum output hold time C Minimum input setup time specification D Minimum input hold time specification 18 MPC850 (Rev. A/B/C) Hardware Specifications A B Figure 2. Control Timing MOTOROLA ...

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... Figure 3 provides the timing for the external clock. Figure 4 provides the timing for the synchronous output signals. CLKOUT Output Signals Output Signals Output Signals Figure 4. Synchronous Output Signals Timing MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications Figure 3. External Clock Timing Layout Practices 19 ...

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... Figure 5 provides the timing for the synchronous active pull-up and open-drain output signals. Figure 5. Synchronous Active Pullup and Open-Drain Outputs Signals Timing Figure 6 provides the timing for the synchronous input signals. CLKOUT , , , , , Figure 6. Synchronous Input Signals Timing 20 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA ...

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... Figure 7 provides normal case timing for input data. Figure 7. Input Data Timing in Normal Case Figure 8 provides the timing for the input data controlled by the UPM in the memory controller. Figure 8. Input Data Timing when Controlled by UPM in the Memory Controller MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications Layout Practices 21 ...

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... Layout Practices Figure 9 through Figure 12 provide the timing for the external bus read controlled by various GPCM factors. CLKOUT TS A[6:31] CSx OE WE[0:3] D[0:31], DP[0:3] Figure 9. External Bus Read Timing (GPCM Controlled—ACS = 00) 22 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA ...

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... CLKOUT TS A[6:31] CSx OE D[0:31], DP[0:3] Figure 10. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 10) Figure 11. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 11) MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications B22a Layout Practices 23 ...

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... Layout Practices Figure 12. External Bus Read Timing (GPCM Controlled—TRLX = 1, ACS = 10, ACS = 11) 24 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA ...

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... Figure 13 through Figure 15 provide the timing for the external bus write controlled by various GPCM factors. Figure 13. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 0) MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications Layout Practices 25 ...

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... Layout Practices Figure 14. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 1) 26 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA ...

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... Figure 15. External Bus Write Timing (GPCM Controlled—TRLX = 1, CSNT = 1) Figure 16 provides the timing for the external bus controlled by the UPM. MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications Layout Practices 27 ...

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... Layout Practices Figure 16. External Bus Timing (UPM Controlled Signals) Figure 17 provides the timing for the asynchronous asserted UPWAIT signal controlled by the UPM. Figure 17. Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles Timing 28 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA ...

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... Figure 18 provides the timing for the asynchronous negated UPWAIT signal controlled by the UPM. Figure 18. Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Timing Figure 19 provides the timing for the synchronous external master access controlled by the GPCM. Figure 19. Synchronous External Master Access Timing (GPCM Handled ACS = 00) MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications Layout Practices 29 ...

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... MPC850 is able to support 30 MPC850 (Rev. A/B/C) Hardware Specifications Table 7. Interrupt Timing 50 MHz 1 Min Max 6.00 — 2.00 — 3.00 — 3.00 — 80.00 — 66MHz 80 MHz Unit Min Max Min Max 6.00 — 6.00 — ns 2.00 — 2.00 — ns 3.00 — 3.00 — ns 3.00 — 3.00 — ns 121.0 — 100.0 — ns MOTOROLA ...

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... CLKOUT to REG Invalid. CLKOUT to CE1, CE2 asserted. CLKOUT to CE1, CE2 negated. CLKOUT to PCOE, IORD, PCWE, IOWR assert time. CLKOUT to PCOE, IORD, PCWE, IOWR negate time. CLKOUT to ALE assert time MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications Table 8. PCMCIA Timing 50MHz 66MHz Min Max Min Max 13 ...

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... Figure 24. PCMCIA Access Cycles Timing External Bus Read 32 MPC850 (Rev. A/B/C) Hardware Specifications Table 8. PCMCIA Timing (continued) 50MHz 66MHz Min Max Min — 13.00 — 3.00 — 6.00 1 8.00 — 8.00 1 2.00 — 2.00 80 MHz FFACTOR Unit Max Min Max 16.00 — 14.00 0.250 — 4.00 — 0.250 — 8.00 — — — 2.00 — — MOTOROLA ...

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... Figure 25 provides the PCMCIA access cycle timing for the external bus write. Figure 25. PCMCIA Access Cycles Timing External Bus Write Figure 26 provides the PCMCIA WAIT signals detection timing. WAIT_B Figure 26. PCMCIA WAIT Signal Detection Timing MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications Layout Practices 33 ...

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... Figure 28 provides the PCMCIA output port timing for the MPC850. 34 MPC850 (Rev. A/B/C) Hardware Specifications Table 9. PCMCIA Port Timing 50 MHz Min Max — 19.00 1 18.00 — 5.00 — 1.00 — Figure 28. PCMCIA Input Port Timing 66 MHz 80 MHz Unit Min Max Min Max — 19.00 — 19.00 ns 26.00 — 22.00 — ns 5.00 — 5.00 — ns 1.00 — 1.00 — ns MOTOROLA ...

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... DSCK low to DSDO data valid DSCK low to DSDO invalid Figure 29 provides the input timing for the debug port clock. Figure 29. Debug Port Clock Input Timing Figure 30 provides the timing for the debug port. MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications Table 10. Debug Port Timing 50 MHz 66 MHz ...

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... MHz FFACTOR Unit Min Max — 20.00 — ns — 20.00 — ns 425.00 — 17.000 ns — — — 425.00 — 15.000 ns 350.00 — — ns 0.00 — — ns 0.00 — — ns — 25.00 — ns — 25.00 — ns — 25.00 — ns 75.00 — 3.000 ns 0.00 — — ns 200.00 — 8.000 ns MOTOROLA ...

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... Table 12 provides the JTAG timings for the MPC850 as shown in Figure 34 to Figure 37. Num Characteristic TCK cycle time TCK clock pulse width measured at 1.5 V TCK rise and fall times TMS, TDI data setup time MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications Table 12. JTAG Timing 50 MHz 66MHz Min Max Min 100 ...

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... MHz Min Max Min Max 25.00 — 25.00 — — 27.00 — 27.00 0.00 — 0.00 — — 20.00 — 20.00 100.00 — 100.00 — 40.00 — 40.00 — — 50.00 — 50.00 — 50.00 — 50.00 — 50.00 — 50.00 50.00 — 50.00 — 50.00 — 50.00 — MOTOROLA Unit ...

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... Table 13 provides the parallel I/O timings for the MPC850 as shown in Figure 38. Num 29 Data-in setup time to clock high 30 Data-in hold time from clock high 31 Clock low to data-out valid (CPU writes data, control, or direction) MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications Table 13. Parallel I/O Timing Characteristic PIO AC Electrical Specifications All Frequencies Unit Min ...

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... SDACK negation delay from clock high 46 TA assertion to falling edge of the clock setup time (applies to external TA) Figure 39. IDMA External Requests Timing Diagram 40 MPC850 (Rev. A/B/C) Hardware Specifications Table 14. IDMA Controller Timing Characteristic All Frequencies Unit Min Max 7.00 — ns 3.00 — ns — 12.00 ns — 12.00 ns — 20.00 ns — 15.00 ns 7.00 — ns MOTOROLA ...

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... Figure 40. SDACK Timing Diagram—Peripheral Write, TA Sampled Low at the Falling Edge Figure 41. SDACK Timing Diagram—Peripheral Write, TA Sampled High at the Falling Edge MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications IDMA Controller AC Electrical Specifications of the Clock of the Clock 41 ...

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... Table 15 provides the baud rate generator timings as shown in Figure 43. Table 15. Baud Rate Generator Timing Num 50 BRGO rise and fall time 51 BRGO duty cycle 52 BRGO cycle n Figure 43. Baud Rate Generator Timing Diagram 42 MPC850 (Rev. A/B/C) Hardware Specifications All Frequencies Characteristic Min — 40.00 40.00 Unit Max 10.00 ns 60.00 % — ns MOTOROLA ...

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... L1RCLK, L1TCLK width low (DSC = 0) 71a L1RCLK, L1TCLK width high (DSC = 0) 72 L1TXD, L1STn, L1RQ, L1xCLKO rise/fall time 73 L1RSYNC, L1TSYNC valid to L1xCLK edge Edge (SYNC setup time) MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications Timer AC Electrical Specifications Table 16. Timer Timing All Frequencies Characteristic Min 10.00 1 ...

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... MPC850 (Rev. A/B/C) Hardware Specifications Table 17. SI Timing (continued) All Frequencies Min 35.00 — 17.00 13.00 4 10.00 10.00 10.00 10.00 4 10.00 0.00 — — 4 1.00 42.00 42.00 — Unit Max — ns 15.00 ns — ns — ns 45.00 ns 45.00 ns 45.00 ns 55.00 ns 55.00 ns 42.00 ns 16.00 or MHz SYNCCLK/2 — ns — ns 30.00 ns — L1TCLK — ns — ns 0.00 ns MOTOROLA ...

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... L1RCLK (FE=0, CE=0) (Input) 71 L1RCLK (FE=1, CE=1) (Input) L1RSYNC (Input) 73 L1RxD (Input) 76 L1STn (Output) Figure 45. SI Receive Timing Diagram with Normal Clocking (DSC = 0) MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications Serial Interface AC Electrical Specifications 70 71a 72 RFSD BIT0 ...

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... Serial Interface AC Electrical Specifications L1RCLK (FE=1, CE=1) (Input) 82 L1RCLK (FE=0, CE=0) (Input) 75 L1RSYNC (Input L1RXD (Input) 76 L1ST(4-1) (Output) L1CLKO (Output) Figure 46. SI Receive Timing with Double-Speed Clocking (DSC = 1) 46 MPC850 (Rev. A/B/C) Hardware Specifications 72 83a RFSD=1 77 BIT0 MOTOROLA ...

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... L1TCLK (FE=0, CE=0) (Input) 71 L1TCLK (FE=1, CE=1) (Input) 73 L1TSYNC (Input) 80a L1TxD BIT0 (Output L1STn (Output) Figure 47. SI Transmit Timing Diagram MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications Serial Interface AC Electrical Specifications 70 72 TFSD ...

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... Serial Interface AC Electrical Specifications L1RCLK (FE=0, CE=0) (Input) L1RCLK (FE=1, CE=1) (Input) 75 L1RSYNC (Input L1TXD BIT0 (Output) 80 78a L1ST(4-1) (Output L1CLKO (Output) Figure 48. SI Transmit Timing with Double Speed Clocking (DSC = 1) 48 MPC850 (Rev. A/B/C) Hardware Specifications 72 83a 82 TFSD MOTOROLA ...

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... MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications Serial Interface AC Electrical Specifications Figure 49. IDL Timing 49 ...

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... Table 19. NMSI Internal Clock Timing Characteristic for all specs in this table) 2 All Frequencies Unit Min Max 1/SYNCCLK — ns 1/SYNCCLK +5 — ns — 15.00 ns 0.00 50.00 ns 0.00 50.00 ns 5.00 — ns 5.00 — ns 5.00 — ns 5.00 — ns All Frequencies Unit Min Max 0.00 SYNCCLK/3 MHz — — ns 0.00 30.00 ns 0.00 30.00 ns 40.00 — ns 40.00 — ns 0.00 — ns 40.00 — ns MOTOROLA ...

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... Figure 50 through Figure 52 show the NMSI timings. Figure 50. SCC NMSI Receive Timing Diagram Figure 51. SCC NMSI Transmit Timing Diagram MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications SCC in NMSI Mode Electrical Specifications 51 ...

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... TXDx inactive delay (from TCLKx rising edge) 52 MPC850 (Rev. A/B/C) Hardware Specifications Figure 52. HDLC Bus Timing Diagram Table 20. Ethernet Timing Characteristic All Frequencies Unit Min Max 40.00 — ns — 15.00 ns 40.00 — ns 80.00 120.00 ns 20.00 — ns 5.00 — ns 10.00 — ns 100.00 — ns — 15.00 ns 40.00 — ns 99.00 101.00 ns 10.00 50.00 ns 10.00 50.00 ns MOTOROLA ...

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... The ratios SyncCLK/RCLKx and SyncCLK/TCLKx must be greater or equal to 2/1. 2 SDACK is asserted whenever the SDMA writes the incoming frame destination address into memory. Figure 53. Ethernet Collision Timing Diagram Figure 54. Ethernet Receive Timing Diagram MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications Characteristic 2 2 Ethernet Electrical Specifications ...

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... SMTXDx active delay (from SMCLKx falling edge) 154 SMRXDx/SMSYNx setup time 155 SMRXDx/SMSYNx hold time 1 The ratio SyncCLK/SMCLKx must be greater or equal to 2/1. 54 MPC850 (Rev. A/B/C) Hardware Specifications All Frequencies Characteristic 1 Unit Min Max 100.00 — ns 50.00 — ns 50.00 — ns — 15.00 ns 10.00 50.00 ns 20.00 — ns 5.00 — ns MOTOROLA ...

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... Master data hold time (inputs) 164 Master data valid (after SCK edge) 165 Master data hold time (outputs) 166 Rise time output 167 Fall time output MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications SPI Master AC Electrical Specifications Table 22. SPI Master Timing All Frequencies Characteristic Min ...

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... SPI Master AC Electrical Specifications Figure 57. SPI Master ( Timing Diagram Figure 58. SPI Master ( Timing Diagram 56 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA ...

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... Slave data valid (after SPICLK edge) 180 Slave data hold time (outputs) 181 Rise time (input) 182 Fall time (input) MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications SPI Slave AC Electrical Specifications Table 23. SPI Slave Timing Characteristic All Frequencies Unit Min ...

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... SPI Slave AC Electrical Specifications Figure 59. SPI Slave ( Timing Diagram 58 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA ...

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... Bus free time between transmissions 203 Low period of SCL 204 High period of SCL 205 Start condition setup time 206 Start condition hold time 207 Data hold time MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications 2 Table 24 Timing (SCL < 100 KH Characteristic 1 I2C AC Electrical Specifications ) Z All Frequencies ...

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... CONTINUED All Frequencies Unit Min Max 250.00 — ns — 1.00 s — 300.00 ns 4.70 — All Frequencies Unit Min Max 0 BRGCLK/48 BRGCLK/48 — — — — — 0 — — — 1/(10 * fSCL) — 1/(33 * fSCL) — MOTOROLA ...

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... N/A MPC850DE Yes MPC850SAR Yes 1 Serial Communication Controller (SCC MHz version supports 64 time slots on a time division multiplexed line using one SCC MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications 2 Figure 61 Bus Timing Diagram Table 26. MPC850 Derivatives 32-Channel HDLC 1 Number of SCCs One ...

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... MPC850 (Rev. A/B/C) Hardware Specifications Frequency (MHz) Temperature (Tj) 50 0°C to 95°C 66 0°C to 95°C 80 0°C to 95°C 50 -40°C to 95° Order Number XPC850ZT50B XPC850DEZT50B XPC850SRZT50B XPC850ZT66B XPC850DEZT66B XPC850SRZT66B XPC850ZT80B XPC850DEZT80B XPC850SRZT80B XPC850CZT50B XPC850DECZT50B XPC850SRCZT50B XPC850CZT66B XPC850DECZT66B XPC850SRCZT66B XPC850CZT80B ...

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... CS4 CS7 CS2 N/C CS3 CS1 BDIP Figure 62. Pin Assignments for the PBGA (Top View)—non-JEDEC Standard MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications Pin Assignments and Mechanical Dimensions of the PBGA PB24 PB23 PA8 PA7 VDDL PA5 TDI PC11 PC9 PB19 ...

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... Figure 63. Pin Assignments for the PBGA (Top View)—JEDEC Standard For more information on the printed circuit board layout of the PBGA package, including thermal via design and suggested pad layout, please refer to AN-1231/D, Plastic Ball Grid Array Application Note available from your local Motorola sales office. 64 MPC850 (Rev. A/B/C) Hardware Specifications ...

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... SEATING PLANE SIDE VIEW e 15X (E1 Figure 64. Package Dimensions for the Plastic Ball Grid Array (PBGA)—non-JEDEC Standard MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications Pin Assignments and Mechanical Dimensions of the PBGA TOP VIEW (D1) e 15X ...

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... SOLDER BALL DIAMETER, PARALLEL TO PRIMARY DATUM C. 4. PRIMARY DATUM C AND THE SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. MILLIMETERS DIM MIN MAX A 1.91 2.35 A1 0.50 0.70 A2 1.12 1.22 A3 0.29 0.43 b 0.60 0.90 D 23.00 BSC D1 19.05 REF D2 19.00 20.00 E 23.00 BSC E1 19.05 REF E2 19.00 20.00 e 1.27 BSC MOTOROLA ...

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... Removed reference to 5 Volt tolerance capability on peripheral interface pins. Replaced SI and IDL timing diagrams with better images. Put into new template, added this revision table. 0.2 04/2002 Put in the new power numbers and added Rev MPC850 (Rev. A/B/C) Hardware Specifications Table 28. Document Revision History Change MOTOROLA ...

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... Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. digital dna is a trademark of Motorola, Inc. All other product or service names are the property of their respective owners. Motorola, Inc Equal Opportunity/Affirmative Action Employer. ...