UPD444012AGY-B70X-MJH NEC, UPD444012AGY-B70X-MJH Datasheet
UPD444012AGY-B70X-MJH
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UPD444012AGY-B70X-MJH Summary of contents
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... EXTENDED TEMPERATURE OPERATION Description The PD444012A high speed, low power, 4,194,304 bits (262,144 words by 16 bits) CMOS static RAM. The PD444012A-X has two chip enable pins (/CE1, CE2) to extend the capacity. ...
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Ordering Information Part number PD444012AGY-B55X-MJH 48-pin PLASTIC TSOP (I) PD444012AGY-B70X-MJH (12 18) (Normal bent) PD444012AGY-B85X-MJH PD444012AGY-B10X-MJH PD444012AGY-C70X-MJH PD444012AGY-C85X-MJH PD444012AGY-C10X-MJH PD444012AGY-C12X-MJH Note V 3 Package Access time Operating ns (MAX.) supply voltage Note 55, 50 2.7 to 3.6 ...
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... Remark Refer to Package Drawing for the 1-pin index mark. [ PD444012AGY-BxxX-MJH ] [ PD444012AGY-CxxX-MJH ] A0 - A17 : Address inputs I/O1 - I/O16 : Data inputs / outputs /CE1, CE2 : Chip Enable 1, 2 /WE : Write Enable /OE : Output Enable /LB, /UB : Byte data select V : Power supply CC GND : Ground Connection Data Sheet M14464EJ5V0DS PD444012A-X 48 A16 GND 45 I/O16 44 I/O8 43 I/O15 42 I/O7 41 I/O14 40 ...
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Block Diagram V CC GND A0 Address buffer A17 I/O1 - I/O8 I/O9 - I/O16 /CE1 CE2 /LB /UB /WE /OE Truth Table /CE1 CE2 /OE /WE / ...
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Electrical Specifications Absolute Maximum Ratings Parameter Symbol Supply voltage V CC Input / Output voltage V T Operating ambient temperature T A Storage temperature T stg Note –3.0 V (MIN.) (Pulse width : 30 ns) Caution Exposing the device to ...
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DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)(1/2) Parameter Symbol Input leakage current I/O leakage current I/O CE2 = V Operating supply current ...
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DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)(2/2) Parameter Symbol Input leakage current I/O leakage current I/O CE2 = V Operating supply current ...
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AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) AC Test Conditions [ PD444012A-B55X, PD444012A-B70X, PD444012A-B85X, PD444012A-B10X ] Input Waveform (Rise and Fall Time 0 0 Output Waveform V CC Output Load 1TTL + 50 ...
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Read Cycle (1/2) (B version) Parameter Symbol Read cycle time t Address access time t /CE1 access time t CO1 CE2 access time t CO2 /OE to output valid t /LB, /UB to output valid t Output hold from address ...
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Read Cycle Timing Chart Address (Input) /CE1 (Input) CE2 (Input) /OE (Input) /LB, /UB (Input) I/O (Output) Remark In read cycle, /WE should be fixed to high level CO1 t LZ1 t CO2 t ...
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Write Cycle (1/2) (B version) Parameter Symbol Write cycle time t WC /CE1 to end of write t CW1 CE2 to end of write t CW2 /LB, /UB to end of write t BW Address valid to end of write ...
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Write Cycle Timing Chart 1 (/WE Controlled) Address (Input) /CE1 (Input) CE2 (Input /WE (Input) /LB, /UB (Input) I/O (Input / Output) Indefinite data out Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE ...
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Write Cycle Timing Chart 2 (/CE1 Controlled) Address (Input) /CE1 (Input) CE2 (Input) /WE (Input) /LB, /UB (Input) High impedance I/O (Input) Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated ...
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Write Cycle Timing Chart 3 (CE2 Controlled) Address (Input) /CE1 (Input) CE2 (Input) /WE (Input) /LB, /UB (Input) High impedance I/O (Input) Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated ...
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Write Cycle Timing Chart 4 (/LB, /UB Controlled) Address (Input) /CE1 (Input) CE2 (Input) /WE (Input) /LB, /UB (Input) High impedance I/O (Input) Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. ...
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Low V Data Retention Characteristics (T CC Parameter Symbol Data retention V /CE1 V CCDR1 CC supply voltage V CE2 0.2 V CCDR2 V /LB = /UB CCDR3 /CE1 0.2 V, CE2 Data retention 1.5 V, /CE1 ...
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Data Retention Timing Chart (1) /CE1 Controlled t CDR V CC Note V (MIN.) CC /CE1 V (MIN (MIN.) CCDR V (MAX.) IL GND Note B version : 2 version : 2.2 V Remark On the ...
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Controlled t CDR V CC Note V (MIN.) CC /LB, /UB V (MIN (MIN.) CCDR V (MAX.) IL GND Note B version : 2 version : 2.2 V Remark On the data retention ...
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Package Drawing 48-PIN PLASTIC TSOP(I) (12x18 NOTES 1. Each lead centerline is located within 0. its true position (T.P.) at maximum material condition. 2. "A" excludes mold flash. (Includes mold flash : 12.4 ...
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Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the PD444012A-X. Types of Surface Mount Device PD444012AGY-BxxX-MJH: 48-pin PLASTIC TSOP (I) (12 18) (Normal bent) PD444012AGY-CxxX-MJH: 48-pin PLASTIC TSOP (I) (12 18) (Normal bent) 20 Data ...
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MEMO ] Data Sheet M14464EJ5V0DS PD444012A-X 21 ...
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MEMO ] 22 Data Sheet M14464EJ5V0DS PD444012A-X ...
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... HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry ...
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... NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others ...