UPD754302 NEC, UPD754302 Datasheet
UPD754302
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UPD754302 Summary of contents
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PD754302,754304,754302(A),754304(A) 4-BIT SINGLE-CHIP MICROCONTROLLER The PD754304 is one of the “75XL Series” 4-bit single-chip microcontrollers with data processing capability comparable to that of 8-bit microcontrollers. The PD754303(A) has a higher reliability than the PD754304. The microcontrollers in the 75XL Series ...
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... SOP (300 mil, 0.8 mm pitch) Remark indicates a ROM code number. Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. Difference between PD75430 and PD75430 (A) Parts Number PD754302 ...
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Functional Outline Parameter Instruction execution time • 0.95, 1.91, 3.81, 15 4.19 MHz with system clock) • 0.67, 1.33, 2.67, 10 6.0 MHz with system clock) On-chip memory ROM 2048 4096 RAM 256 General-purpose register • ...
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... 3 ...
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APPENDIX A. COMPARISON OF FUNCTIONS AMONG PD750004, 754304, AND 75P4308 ·········· 65 APPENDIX B. DEVELOPMENT TOOLS ································································································· 67 APPENDIX C. RELATED DOCUMENTS ································································································ 70 PD754302, 754304, 754302(A), 754304(A) 5 ...
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... RESET 4 P33 5 P32 6 P31 7 P30 8 P81 9 P80 10 P23 11 P22/PCL 12 P21/PTO1 13 P20/PTO0 14 P03/SI 15 P02/SO/SB0 16 P01/SCK 17 P00/INT4 18 IC: Internally Connected (Connect directly this pin PD754302, 754304, 754302(A), 754304(A) 36 P50 35 P51 34 P52 33 P53 32 P60/KR0 31 P61/KR1 30 P62/KR2 29 P63/KR3 28 P70/KR4 27 P71/KR5 26 P72/KR6 25 P73/KR7 24 P13/TI0/TI1 23 ...
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... PD754302, 754304, 754302(A), 754304(A) RESET : Reset Input TI0, TI1 : Timer Input 0, 1 PTO0, PTO1 : Programmable Timer Output 0, 1 PCL : Programmable Clock INT0 External Vectored Interrupt INT2 : External Test Input GND SS X1 System Clock Oscillation Internally Connected V : Positive Power Supply DD 7 ...
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BASIC INTERVAL TIMER/ WATCHDOG TIMER INTBT TOUT0 INTT0 COUNTER TI0/TI1/P13 8-BIT CASCADED TIMER/EVENT PTO0/P20 16-BIT COUNTER#0 TIMER/ 8-BIT EVENT TIMER/EVENT PTO1/P21 COUNTER COUNTER#1 INTT1 SI/P03 CLOCKED SO/SB0/P02 SERIAL INTERFACE SCK/P01 INTCSI TOUT0 INT0/P10 INT1/P11 INTERRUPT INT2/P12 CONTROL INT4/P00 KR0-KR3/P60-P63 8 ...
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PIN FUNCTION 3.1 Port Pins Alternate Pin Name Input/Output Function P00 Input INT4 P01 Input/Output SCK P02 Input/Output SO/SB0 P03 Input SI P10 Input INT0 P11 INT1 P12 INT2 P13 TI0/TI1 P20 Input/Output PTO0 P21 PTO1 P22 PCL P23 ...
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... Crystal/ceramic connection pin for the system clock oscillator. When inputting the external clock, input the external clock to pin X1, and the inverted phase of the external clock to pin X2. System reset input (low-level active) Internally connected. Connect directly to V Positive power supply Ground potential I/O Circuit After Reset Note ...
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Pin Input/Output Circuits The PD754304 pin input/output circuits are shown schematically. TYPE P-ch IN N-ch CMOS specification input buffer. TYPE B IN Schmitt trigger input having hysteresis characteristic. TYPE B P.U.R. P.U.R. P-ch enable ...
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... V DD P.U.R. (Mask Option) P-ch data DD output disable P-ch Input IN/OUT instruction N-ch P.U.R. : Pull-Up Resistor Note If this pull-up resistor is not connected using the mask option it operates only when the input instruction is executed (if the pin is low, current flows from V pin P.U.R. IN/OUT N-ch (+ P-ch Note P.U.R. Voltage ...
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... Recommended Connections for Unused Pins Table 3-1. List of Recommended Connections for Unused Pins Pin P00/INT4 P01/SCK P02/SO/SB0 P03/SI P10/INT0-P12/INT2 P13/TI0/TI1 P20/PTO0 P21/PTO1 P22/PCL P23 P30-P33 P50-P53 P60/KR0-P63/KR3 P70/KR4-P73/KR7 P80, P81 IC PD754302, 754304, 754302(A), 754304(A) Recommended Connection Connect Connect to V ...
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SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE 4.1 Difference between Mk I and Mk II Modes The CPU of PD754304 has the following two modes and Mk II, either of which can be selected. ...
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Setting Method of Stack Bank Select Register (SBS) Switching between the Mk I mode and Mk II mode can be done by the SBS. Figure 4-1 shows the format. The SBS is set by a 4-bit memory manipulation instruction. ...
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MEMORY CONFIGURATION • Program Memory (ROM) .... .... • Addresses 0000H and 0001H Vector table wherein the program start address and the values set for the RBE and MBE at the time a RESET signal is generated are written. ...
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Figure 5-1. Program Memory Map (1/2) Address MBE RBE 0 0 Internal reset start address Internal reset start address MBE RBE 0 0 INTBT/INT4 INTBT/INT4 0 ...
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Figure 5-1. Program Memory Map (2/2) Address MBE RBE 0 0 Internal reset start address Internal reset start address MBE RBE 0 0 INTBT/INT4 INTBT/INT4 0 ...
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PD754302, 754304, 754302(A), 754304(A) Figure 5-2. Data Memory Map General-purpose register area Data area static RAM (256 4) Stack area Peripheral hardware area F ...
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... Can be set in input or output mode in 4-bit units. PORT3 Can be set in input or output mode in 1-bit units. PORT5 4-bit I/O Can be set in input or output mode in 4-bit units. Pull-up (N-ch open- resistor can be connected in 1-bit units by mask option. drain PORT6 4-bit I/O Can be set in input or output mode in 1-bit units. PORT7 Can be set in input or output mode in 4-bit units ...
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Clock Generator • Clock generator configuration The clock generator provides the clock signals to the CPU and peripheral hardware and its configuration is shown in Figure 6-1. The operation of the clock generator is set with the processor clock ...
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Clock Output Circuit The clock output circuit outputs clock pulses from the P22/PCL pin, and is used to apply for remote controller waveform output or to supply clock pulse peripheral LSIs. • Clock output (PCL 524, 262, ...
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Basic Interval Timer/Watchdog Timer The basic interval timer/watchdog timer has the following functions. • Interval timer operation to generate a reference time interrupt • Watchdog timer operation to detect a runaway of program and reset the CPU • Selects ...
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Timer/Event Counter The PD754304 has two channels of timer/event counters. Its configuration is shown in Figures 6-4 and 6-5. The timer/event counter has the following functions. • Programmable interval timer operation • Square wave output of any frequency to ...
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TM06 TM05 TM04 TM03 TM02 TM01 TM00 PORT1.3 Decoder Input buffer TI0/TI1/P13 From clock X MPX generator Timer/event counter (channel ...
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TM16 TM15 TM14 TM13 TM12 TM11 TM10 PORT1.3 Input buffer TI0/TI1/P13 Timer/event counter (channel 0) output MPX From clock generator ...
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Serial Interface The PD754304 incorporates the clocked 8-bit serial interface, and the following three modes are provided. • Operation stop mode • 3-wire serial I/O mode • 2-wire serial I/O mode PD754302, 754304, 754302(A), 754304(A) 27 ...
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Bit test CSIM P03/SI Selector P02/SO/SB0 P01/SCK P01 output Iatch Figure 6-6. Serial Interface Block Diagram Internal bus Slave address register (SVA) (8) Matching RELT signal Address comparator (8) D Shift register (SIO) (8) INTCSI Serial ...
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Bit Sequential Buffer ....... 16 Bits The bit sequential buffer (BSB special data memory for bit manipulation and the bit manipulation can be easily performed by changing the address specification and bit specification in sequence, therefore it ...
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INTERRUPT FUNCTION AND TEST FUNCTION The PD754304 has seven kinds of interrupt sources and one kind of test source. Two types of edge detection testable inputs are provided for INT2 of the test source. The interrupt control circuit of ...
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IM2 IM1 IM0 INTBT IRQBT Both edge INT4/P00 IRQ4 detector Edge INT0/P10 Note Selec- IRQ0 tor detector Edge IRQ1 INT1/P11 detector INTCSI IRQCSI INTT0 IRQT0 INTT1 IRQT1 Rising edge INT2/P12 IRQ2 Selec- detector tor KR0/P60 Falling edge ...
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STANDBY FUNCTION In order to save dissipation power while a program standby mode, two types of standby modes (STOP mode and HALT mode) are provided for the PD754304. Table 8-1. Operation Status in Standby Mode Mode ...
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RESET FUNCTION There are two reset inputs: external RESET signal and RESET signal sent from the basic interval timer/ watchdog timer. When either one of the RESET signals are input, an internal RESET signal is generated. Figure 9-1 shows ...
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Table 9-1. Status of Each Hardware After Reset (1/2) Hardware Program counter (PC) PSW Carry flag (CY) Skip flag (SK0-SK2) Interrupt status flag (IST0, IST1) Bank enable flag (MBE, RBE) Stack pointer (SP) Stack bank select register (SBS) Data memory ...
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Table 9-1. Status of Each Hardware After Reset (2/2) Hardware Interrupt Interrupt request flag (IRQ function Interrupt enable flag (IE Interrupt priority select register (IPS) INT0 mode registers (IM0, IM1, IM2) Digital port Output buffer Output latch I/O ...
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... The PD754304 has the following mask options: • Mask option of P50 through P53 Pull-up resistors can be connected to these pins. (1) Specify connection of a pull-up resistor in 1-bit units. (2) Do not specify connection of a pull-up resistor. • Standby function mask option The wait time when the RESET signal is input can be selected. ...
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INSTRUCTION SETS (1) Expression formats and description methods of operands The operand is described in the operand column of each instruction in accordance with the description method for the operand expression format of the instruction. For details, refer to ...
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Legend in explanation of operation register; 4-bit accumulator register register register register register register register ...
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Explanation of symbols under addressing area column * MBE•MBS (MBS = 0, 15 MBE = (000H-07FH (F80H-FFFH) MBE = MBS ...
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Instruction Mnemonic Operand group Transfer MOV A, #n4 reg1, #n4 XA, #n8 HL, #n8 rp2, #n8 A, @HL A, @HL+ A, @HL– A, @rpa XA, @HL @HL, A @HL mem XA, mem mem, A mem reg1 ...
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Instruction Number Mnemonic Operand group of bytes Bit transfer MOV1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit fmem.bit, CY pmem.@L, CY @H+mem.bit, CY Operation ADDS A, #n4 XA, #n8 A, @HL XA, rp' rp'1, XA ADDC A, @HL XA, rp' rp'1, ...
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Instruction Mnemonic Operand group Comparison SKE reg, #n4 @HL, #n4 A, @HL XA, @HL A, reg XA, rp' Carry flag SET1 CY manipulation CLR1 CY SKT CY NOT1 CY Memory bit SET1 mem.bit manipulation fmem.bit pmem.@L @H+mem.bit CLR1 mem.bit fmem.bit ...
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Instruction Mnemonic Operand group Note Branch BR addr addr1 !addr $addr $addr1 PCDE PCXA Note The above operations in the double boxes can be performed only in the Mk II mode. PD754302, 754304, 754302(A), 754304(A) Number Number of machine Operation ...
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Instruction Mnemonic Operand group Branch BR BCDE BCXA Note3 BRA !addr1 BRCB !caddr Note3 Subroutine CALLA !addr1 stack control Note3 CALL !addr Notes 1. “0” must be set to the most significant bit of the register C and register B. ...
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Instruction Mnemonic Operand group Note Subroutine CALLF !faddr stack control Note RET Note RETS Note The above operations in the double boxes can be performed only in the Mk II mode. The other operations can be performed only in the ...
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Instruction Mnemonic Operand group Note1 Subroutine RETS stack control Note1 RETI PUSH rp BS POP rp BS Interrupt EI control Note2 Input/output IN A, PORTn XA, PORTn Note2 OUT PORTn, A PORTn, XA Notes 1. The above ...
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Instruction Mnemonic Operand group CPU control HALT STOP NOP Special SEL RBn MBn Notes 1, 2 GETI taddr Notes 1. The TBR and TCALL instructions are the table definition assembler directives of the GETI instruction. 2. The above operations in ...
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Instruction Mnemonic Operand group Notes 1, 2 Special GETI taddr Notes 1. The TBR and TCALL instructions are the table definition assembler directives of the GETI instruction. 2. The above operations in the double boxes can be performed only in ...
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ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings ( Parameter Symbol Supply voltage V DD Input voltage V Except port Port 5 I2 Output voltage V O Output current, high I Per pin OH For ...
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... Always keep the ground point of the capacitor of the oscillation circuit as the same potential • Do not connect the power source pattern through which a high current flows. • Do not extract signals from the oscillation circuit. 50 PD754302, 754304, 754302(A), 754304(A) = – ...
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Recommended Oscillation Circuit Constants Ceramic Resonator (T = – Manufacturer Product Frequency Recommended Circuit Constants (pF) Oscillation Voltage Range (V (MHz) Murata CSB1000J Note 1.0 Mfg. Co., Ltd CSA2.00MG 2.0 CST2.00MG CSA3.58MG 3.58 CST3.58MGW CSA3.58MGU CST3.58MGWU ...
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... Caution The oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation, but do not guarantee oscillation frequency accuracy. If oscillation frequency accu- racy is required for actual circuits necessary to adjust the oscillation frequency of the resonator in the circuit. Please inquire directly to the maker of the resonator for data as needed. ...
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DC Characteristics (T = – Parameter Symbol Output current, low I Per pin OL For all pins Input voltage, high V Ports IH1 V Ports RESET IH2 ...
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DC Characteristics (T = – Parameter Symbol Note1 Supply current I 6.00 MHz DD1 Crystal resonator DD2 I 4.19 MHz DD1 Crystal resonator ...
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... RSL Notes 1. The CPU clock ( ) cycle time (minimum instruction execution time) is determined by the ocillation frequency of the con- nected resonator and the processor clock control register (PCC). The figure on the right shows the cycle time t characteristics against the supply voltage V when the system clock is used. ...
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Serial Transfer Operation 2-wire and 3-wire Serial I/O Mode (SCK...Internal clock output) (T Parameter Symbol SCK cycle time 2.7 to 5.5 V KCY1 DD SCK high- and 2.7 to 5.5 V KL1 DD ...
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AC Timing Test Points (Excluding X1 Input) V (MIN (MAX (MIN (MAX.) OL Note For the values, refer to the DC Characteristics. Clock Timing X1 input TI0, TI1 Timing TI0, TI1 PD754302, 754304, 754302(A), ...
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Serial Transfer Timing 3-wire Serial I/O Mode SCK SI t KSO1 2-wire Serial I/O Mode SCK SB0 58 PD754302, 754304, 754302(A), 754304(A) t KCY1 KL1, 2 KH1 SIK1, 2 KSI1, 2 Input ...
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Interrupt Input Timing INT0,1,2,4 KR0-7 RESET Input Timing RESET Data Memory STOP Mode Low-Supply Voltage Data Retention Characteristics (T Parameter Symbol Release signal set time t SREL Oscillation stabilization t Release by RESET WAIT Note1 wait time Release by interrupt ...
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Data Retention Timing (on releasing STOP mode by RESET Execution of STOP instruction RESET Data Retention Timing (Standby release signal: on releasing STOP mode by interrupt signal Execution of STOP instruction Standby release signal (interrupt request) ...
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CHARACTERISTICS CURVES (REFERENCE VALUES 5.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 PD754302, 754304, 754302(A), 754304(A) (System Clock: 6.0-MHz Crystal Resonator) PCC = 0011 PCC = 0010 PCC = 0001 ...
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5.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 PD754302, 754304, 754302(A), 754304(A) (System Clock: 4.19-MHz Crystal Resonator) PCC = 0011 PCC = 0010 PCC = 0001 PCC = 0000 System ...
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PACKAGE DRAWING 36 PIN PLASTIC SHRINK SOP (300 mil NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. PD754302, 754304, ...
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... The PD754304 should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 15-1. Surface Mounting Type Soldering Conditions PD754302GS- : 36-pin plastic shrink SOP (300 mil, 0 ...
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... MHz) time w/subsystem clock • 122 s (at 32.768 kHz) I/O port CMOS input 8 (of which 7 can be connected with on-chip pull-up resistor via software) CMOS I/O 18 (on-chip pull-up resistor can be connected via software) N-ch open-drain I/O 8 (pull-up resistor can be (withstand 13 V) connected by mask option) ...
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Item TM0, 1 registers Bits 0, 1, and 7 are fixed to 0 Vectored interrupt External: 3, internal: 4 Test input External: 1, internal: 1 Test enable flag (IEW) Provided Test request flag (IRQW) Supply voltage V DD Operating ambient ...
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... PA-75P4308GS This is a PROM programmer adapter dedicated to the PD75P4308GS and connected to the PG-1500. Software PG-1500 controller This connects the PG-1500 and a host machine with a serial or parallel interface to control the PG-1500 from the host machine. Host machine PC-9800 series IBM PC/AT or compatible machine Note Although Ver ...
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... When developing a PD754304 subseries, the emulation board IE-75300-R-EM and emulation probe which are sold separately must be used with the IE-75001-R. It can debug the system efficiently by connecting the host machine and PROM program- mer. IE-75300-R-EM Emulation board for evaluating the application systems that use a PD754304 subseries ...
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OS for IBM PC The following IBM PC OS’s are supported. OS Version TM PC DOS Ver. 5.02 to Ver. 6.3 Note Note J6.1/V to J6.3/V MS-DOS Ver. 5.0 to Ver. 6.22 Note Note 5.0/V to 6.2/V TM Note IBM ...
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... Document Name IC Package Manual Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Static Electricity Discharge (ESD) Test Guide to Quality Assurance for Semiconductor Devices Microcomputer Related Product Guide - Other Manufacturers Caution These documents are subject to change without notice. Be sure to read the latest documents. ...
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PD754302, 754304, 754302(A), 754304(A) 71 ...
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... Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices ...
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... Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • ...
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... The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. ...